modify sin led gpio

hc

2024-05-13 9d77db3c730780c8ef5ccd4b66403ff5675cfe4e

 kernel/Documentation/devicetree/bindings/mtd/marvell-nand.txt
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@@ -36,29 +36,29 @@
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 Required properties:
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 - reg: shall contain the native Chip Select ids (0-3).
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-- nand-rb: see nand.txt (0-1).
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+- nand-rb: see nand-controller.yaml (0-1).
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 Optional properties:
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 - marvell,nand-keep-config: orders the driver not to take the timings
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   from the core and leaving them completely untouched. Bootloader
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   timings will then be used.
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 - label: MTD name.
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-- nand-on-flash-bbt: see nand.txt.
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-- nand-ecc-mode: see nand.txt. Will use hardware ECC if not specified.
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-- nand-ecc-algo: see nand.txt. This property is essentially useful when
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+- nand-on-flash-bbt: see nand-controller.yaml.
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+- nand-ecc-mode: see nand-controller.yaml. Will use hardware ECC if not specified.
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+- nand-ecc-algo: see nand-controller.yaml. This property is essentially useful when
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   not using hardware ECC. Howerver, it may be added when using hardware
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   ECC for clarification but will be ignored by the driver because ECC
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   mode is chosen depending on the page size and the strength required by
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   the NAND chip. This value may be overwritten with nand-ecc-strength
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   property.
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-- nand-ecc-strength: see nand.txt.
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-- nand-ecc-step-size: see nand.txt. Marvell's NAND flash controller does
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+- nand-ecc-strength: see nand-controller.yaml.
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+- nand-ecc-step-size: see nand-controller.yaml. Marvell's NAND flash controller does
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   use fixed strength (1-bit for Hamming, 16-bit for BCH), so the actual
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   step size will shrink or grow in order to fit the required strength.
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   Step sizes are not completely random for all and follow certain
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   patterns described in AN-379, "Marvell SoC NFC ECC".
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-See Documentation/devicetree/bindings/mtd/nand.txt for more details on
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+See Documentation/devicetree/bindings/mtd/nand-controller.yaml for more details on
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 generic bindings.
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