modify sin led gpio

hc

2024-05-13 9d77db3c730780c8ef5ccd4b66403ff5675cfe4e

 kernel/Documentation/devicetree/bindings/mtd/fsl-upm-nand.txt
..
..
@@ -7,14 +7,16 @@
7
7
 - fsl,upm-cmd-offset : UPM pattern offset for the command latch.
8
8
 
9
9
 Optional properties:
10
-- fsl,upm-wait-flags : add chip-dependent short delays after running the
11
-	UPM pattern (0x1), after writing a data byte (0x2) or after
12
-	writing out a buffer (0x4).
13
10
 - fsl,upm-addr-line-cs-offsets : address offsets for multi-chip support.
14
11
 	The corresponding address lines are used to select the chip.
15
12
 - gpios : may specify optional GPIOs connected to the Ready-Not-Busy pins
16
13
 	(R/B#). For multi-chip devices, "n" GPIO definitions are required
17
14
 	according to the number of chips.
15
+
16
+Deprecated properties:
17
+- fsl,upm-wait-flags : add chip-dependent short delays after running the
18
+	UPM pattern (0x1), after writing a data byte (0x2) or after
19
+	writing out a buffer (0x4).
18
20
 - chip-delay : chip dependent delay for transferring data from array to
19
21
 	read registers (tR). Required if property "gpios" is not used
20
22
 	(R/B# pins not connected).
..
..
@@ -52,8 +54,6 @@
52
54
 	fsl,upm-cmd-offset = <0x08>;
53
55
 	/* Multi-chip NAND device */
54
56
 	fsl,upm-addr-line-cs-offsets = <0x0 0x200>;
55
-	fsl,upm-wait-flags = <0x5>;
56
-	chip-delay = <25>; // in micro-seconds
57
57
 
58
58
 	nand@0 {
59
59
 		#address-cells = <1>;