modify sin led gpio

hc

2024-05-13 9d77db3c730780c8ef5ccd4b66403ff5675cfe4e

 kernel/Documentation/devicetree/bindings/dma/fsl-edma.txt
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@@ -9,15 +9,18 @@
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 Required properties:
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 - compatible :
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 	- "fsl,vf610-edma" for eDMA used similar to that on Vybrid vf610 SoC
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+	- "fsl,imx7ulp-edma" for eDMA2 used similar to that on i.mx7ulp
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+	- "fsl,ls1028a-edma" followed by "fsl,vf610-edma" for eDMA used on the
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+	  LS1028A SoC.
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 - reg : Specifies base physical address(s) and size of the eDMA registers.
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 	The 1st region is eDMA control register's address and size.
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 	The 2nd and the 3rd regions are programmable channel multiplexing
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 	control register's address and size.
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 - interrupts : A list of interrupt-specifiers, one for each entry in
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-	interrupt-names.
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-- interrupt-names : Should contain:
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-	"edma-tx" - the transmission interrupt
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-	"edma-err" - the error interrupt
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+	interrupt-names on vf610 similar SoC. But for i.mx7ulp per channel
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+	per transmission interrupt, total 16 channel interrupt and 1
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+	error interrupt(located in the last), no interrupt-names list on
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+	i.mx7ulp for clean on dts.
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 - #dma-cells : Must be <2>.
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 	The 1st cell specifies the DMAMUX(0 for DMAMUX0 and 1 for DMAMUX1).
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 	Specific request source can only be multiplexed by specific channels
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@@ -28,6 +31,7 @@
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 - clock-names : A list of channel group clock names. Should contain:
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 	"dmamux0" - clock name of mux0 group
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 	"dmamux1" - clock name of mux1 group
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+	Note: No dmamux0 on i.mx7ulp, but another 'dma' clk added on i.mx7ulp.
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 - clocks : A list of phandle and clock-specifier pairs, one for each entry in
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 	clock-names.
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@@ -35,6 +39,10 @@
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 - big-endian: If present registers and hardware scatter/gather descriptors
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 	of the eDMA are implemented in big endian mode, otherwise in little
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 	mode.
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+- interrupt-names : Should contain the below on vf610 similar SoC but not used
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+	on i.mx7ulp similar SoC:
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+	"edma-tx" - the transmission interrupt
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+	"edma-err" - the error interrupt
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 Examples:
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@@ -52,8 +60,36 @@
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 	clock-names = "dmamux0", "dmamux1";
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 	clocks = <&clks VF610_CLK_DMAMUX0>,
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 		<&clks VF610_CLK_DMAMUX1>;
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-};
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+}; /* vf610 */
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+edma1: dma-controller@40080000 {
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+	#dma-cells = <2>;
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+	compatible = "fsl,imx7ulp-edma";
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+	reg = <0x40080000 0x2000>,
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+		<0x40210000 0x1000>;
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+	dma-channels = <32>;
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+	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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+		     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
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+		     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
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+		     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
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+		     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
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+		     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
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+		     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
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+		     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
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+		     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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+		     <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
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+		     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
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+		     <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
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+		     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
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+		     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
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+		     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
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+		     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
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+		     /* last is eDMA2-ERR interrupt */
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+		     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
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+	clock-names = "dma", "dmamux0";
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+	clocks = <&pcc2 IMX7ULP_CLK_DMA1>,
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+		 <&pcc2 IMX7ULP_CLK_DMA_MUX1>;
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+}; /* i.mx7ulp */
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 * DMA clients
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 DMA client drivers that uses the DMA function must use the format described