modify sin led gpio

hc

2024-05-13 9d77db3c730780c8ef5ccd4b66403ff5675cfe4e

 kernel/Documentation/devicetree/bindings/display/rockchip/rockchip-lvds.txt
..
..
@@ -1,19 +1,30 @@
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-Rockchip SoCs LVDS interface
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+Rockchip RK3288 LVDS interface
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2
 ================================
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3
 
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 Required properties:
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5
 - compatible: matching the soc type, one of
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-	- "rockchip,px30-lvds",
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-	- "rockchip,rk3126-lvds",
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-	- "rockchip,rk3288-lvds",
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-	- "rockchip,rk3368-lvds";
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-	- "rockchip,rk3568-lvds";
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-- phys : phandle for the PHY device
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-- phy-names : should be "phy"
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+	- "rockchip,rk3288-lvds";
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+	- "rockchip,px30-lvds";
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+
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+- reg: physical base address of the controller and length
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+	of memory mapped region.
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+- clocks: must include clock specifiers corresponding to entries in the
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+	clock-names property.
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+- clock-names: must contain "pclk_lvds"
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+
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+- avdd1v0-supply: regulator phandle for 1.0V analog power
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+- avdd1v8-supply: regulator phandle for 1.8V analog power
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+- avdd3v3-supply: regulator phandle for 3.3V analog power
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+
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+- rockchip,grf: phandle to the general register files syscon
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+- rockchip,output: "rgb", "lvds" or "duallvds", This describes the output interface
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+
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+- phys: LVDS/DSI DPHY (px30 only)
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+- phy-names: name of the PHY, must be "dphy" (px30 only)
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24
 
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 Optional properties:
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-- dual-channel: boolean. if it exists, enable dual channel mode
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-- rockchip,data-swap: boolean to enable odd/even data swap in dual channel mode
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+- pinctrl-names: must contain a "lcdc" entry.
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+- pinctrl-0: pin control group to be used for this controller.
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 Required nodes:
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30
 
..
..
@@ -27,34 +38,55 @@
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38
 
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 Example:
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40
 
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-&grf {
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-	status = "okay";
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+lvds_panel: lvds-panel {
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+	compatible = "auo,b101ean01";
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+	enable-gpios = <&gpio7 21 GPIO_ACTIVE_HIGH>;
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+	data-mapping = "jeida-24";
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45
 
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-	lvds: lvds {
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+	ports {
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+		panel_in_lvds: endpoint {
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+			remote-endpoint = <&lvds_out_panel>;
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+		};
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+	};
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+};
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+
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+For Rockchip RK3288:
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+
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+	lvds: lvds@ff96c000 {
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 		compatible = "rockchip,rk3288-lvds";
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-		phys = <&video_phy>;
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-		phy-names = "phy";
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-		status = "disabled";
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-
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+		rockchip,grf = <&grf>;
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+		reg = <0xff96c000 0x4000>;
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+		clocks = <&cru PCLK_LVDS_PHY>;
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+		clock-names = "pclk_lvds";
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+		pinctrl-names = "lcdc";
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+		pinctrl-0 = <&lcdc_ctl>;
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+		avdd1v0-supply = <&vdd10_lcd>;
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+		avdd1v8-supply = <&vcc18_lcd>;
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+		avdd3v3-supply = <&vcca_33>;
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+		rockchip,output = "rgb";
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 		ports {
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 			#address-cells = <1>;
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 			#size-cells = <0>;
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70
 
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-			port@0 {
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+			lvds_in: port@0 {
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 				reg = <0>;
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-				#address-cells = <1>;
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-				#size-cells = <0>;
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 				lvds_in_vopb: endpoint@0 {
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 					reg = <0>;
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 					remote-endpoint = <&vopb_out_lvds>;
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 				};
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-
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 				lvds_in_vopl: endpoint@1 {
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 					reg = <1>;
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 					remote-endpoint = <&vopl_out_lvds>;
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 				};
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 			};
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+
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+			lvds_out: port@1 {
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+				reg = <1>;
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+
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+				lvds_out_panel: endpoint {
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+					remote-endpoint = <&panel_in_lvds>;
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+				};
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+			};
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 		};
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 	};
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-};