.. | .. |
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3 | 3 | Required Properties: |
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4 | 4 | |
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5 | 5 | - compatible: must be one of the following. |
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| 6 | + - "renesas,du-r8a7742" for R8A7742 (RZ/G1H) compatible DU |
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6 | 7 | - "renesas,du-r8a7743" for R8A7743 (RZ/G1M) compatible DU |
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| 8 | + - "renesas,du-r8a7744" for R8A7744 (RZ/G1N) compatible DU |
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7 | 9 | - "renesas,du-r8a7745" for R8A7745 (RZ/G1E) compatible DU |
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| 10 | + - "renesas,du-r8a77470" for R8A77470 (RZ/G1C) compatible DU |
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| 11 | + - "renesas,du-r8a774a1" for R8A774A1 (RZ/G2M) compatible DU |
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| 12 | + - "renesas,du-r8a774b1" for R8A774B1 (RZ/G2N) compatible DU |
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| 13 | + - "renesas,du-r8a774c0" for R8A774C0 (RZ/G2E) compatible DU |
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| 14 | + - "renesas,du-r8a774e1" for R8A774E1 (RZ/G2H) compatible DU |
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8 | 15 | - "renesas,du-r8a7779" for R8A7779 (R-Car H1) compatible DU |
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9 | 16 | - "renesas,du-r8a7790" for R8A7790 (R-Car H2) compatible DU |
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10 | 17 | - "renesas,du-r8a7791" for R8A7791 (R-Car M2-W) compatible DU |
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.. | .. |
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13 | 20 | - "renesas,du-r8a7794" for R8A7794 (R-Car E2) compatible DU |
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14 | 21 | - "renesas,du-r8a7795" for R8A7795 (R-Car H3) compatible DU |
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15 | 22 | - "renesas,du-r8a7796" for R8A7796 (R-Car M3-W) compatible DU |
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| 23 | + - "renesas,du-r8a77961" for R8A77961 (R-Car M3-W+) compatible DU |
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16 | 24 | - "renesas,du-r8a77965" for R8A77965 (R-Car M3-N) compatible DU |
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17 | 25 | - "renesas,du-r8a77970" for R8A77970 (R-Car V3M) compatible DU |
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| 26 | + - "renesas,du-r8a77980" for R8A77980 (R-Car V3H) compatible DU |
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| 27 | + - "renesas,du-r8a77990" for R8A77990 (R-Car E3) compatible DU |
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18 | 28 | - "renesas,du-r8a77995" for R8A77995 (R-Car D3) compatible DU |
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19 | 29 | |
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20 | 30 | - reg: the memory-mapped I/O registers base address and length |
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.. | .. |
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34 | 44 | supplied they must be named "dclkin.x" with "x" being the input clock |
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35 | 45 | numerical index. |
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36 | 46 | |
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37 | | - - vsps: A list of phandle and channel index tuples to the VSPs that handle |
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38 | | - the memory interfaces for the DU channels. The phandle identifies the VSP |
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39 | | - instance that serves the DU channel, and the channel index identifies the |
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40 | | - LIF instance in that VSP. |
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| 47 | + - renesas,cmms: A list of phandles to the CMM instances present in the SoC, |
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| 48 | + one for each available DU channel. The property shall not be specified for |
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| 49 | + SoCs that do not provide any CMM (such as V3M and V3H). |
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| 50 | + |
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| 51 | + - renesas,vsps: A list of phandle and channel index tuples to the VSPs that |
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| 52 | + handle the memory interfaces for the DU channels. The phandle identifies the |
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| 53 | + VSP instance that serves the DU channel, and the channel index identifies |
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| 54 | + the LIF instance in that VSP. |
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| 55 | + |
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| 56 | +Optional properties: |
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| 57 | + - resets: A list of phandle + reset-specifier pairs, one for each entry in |
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| 58 | + the reset-names property. |
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| 59 | + - reset-names: Names of the resets. This property is model-dependent. |
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| 60 | + - All but R8A7779 use one reset for a group of one or more successive |
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| 61 | + channels. The resets must be named "du.x" with "x" being the numerical |
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| 62 | + index of the lowest channel in the group. |
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41 | 63 | |
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42 | 64 | Required nodes: |
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43 | 65 | |
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.. | .. |
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49 | 71 | |
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50 | 72 | Port0 Port1 Port2 Port3 |
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51 | 73 | ----------------------------------------------------------------------------- |
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| 74 | + R8A7742 (RZ/G1H) DPAD 0 LVDS 0 LVDS 1 - |
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52 | 75 | R8A7743 (RZ/G1M) DPAD 0 LVDS 0 - - |
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| 76 | + R8A7744 (RZ/G1N) DPAD 0 LVDS 0 - - |
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53 | 77 | R8A7745 (RZ/G1E) DPAD 0 DPAD 1 - - |
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| 78 | + R8A77470 (RZ/G1C) DPAD 0 DPAD 1 LVDS 0 - |
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| 79 | + R8A774A1 (RZ/G2M) DPAD 0 HDMI 0 LVDS 0 - |
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| 80 | + R8A774B1 (RZ/G2N) DPAD 0 HDMI 0 LVDS 0 - |
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| 81 | + R8A774C0 (RZ/G2E) DPAD 0 LVDS 0 LVDS 1 - |
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| 82 | + R8A774E1 (RZ/G2H) DPAD 0 HDMI 0 LVDS 0 - |
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54 | 83 | R8A7779 (R-Car H1) DPAD 0 DPAD 1 - - |
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55 | 84 | R8A7790 (R-Car H2) DPAD 0 LVDS 0 LVDS 1 - |
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56 | 85 | R8A7791 (R-Car M2-W) DPAD 0 LVDS 0 - - |
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.. | .. |
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59 | 88 | R8A7794 (R-Car E2) DPAD 0 DPAD 1 - - |
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60 | 89 | R8A7795 (R-Car H3) DPAD 0 HDMI 0 HDMI 1 LVDS 0 |
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61 | 90 | R8A7796 (R-Car M3-W) DPAD 0 HDMI 0 LVDS 0 - |
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| 91 | + R8A77961 (R-Car M3-W+) DPAD 0 HDMI 0 LVDS 0 - |
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62 | 92 | R8A77965 (R-Car M3-N) DPAD 0 HDMI 0 LVDS 0 - |
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63 | 93 | R8A77970 (R-Car V3M) DPAD 0 LVDS 0 - - |
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| 94 | + R8A77980 (R-Car V3H) DPAD 0 LVDS 0 - - |
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| 95 | + R8A77990 (R-Car E3) DPAD 0 LVDS 0 LVDS 1 - |
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64 | 96 | R8A77995 (R-Car D3) DPAD 0 LVDS 0 LVDS 1 - |
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65 | 97 | |
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66 | 98 | |
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.. | .. |
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78 | 110 | <&cpg CPG_MOD 722>, |
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79 | 111 | <&cpg CPG_MOD 721>; |
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80 | 112 | clock-names = "du.0", "du.1", "du.2", "du.3"; |
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81 | | - vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, <&vspd0 1>; |
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| 113 | + resets = <&cpg 724>, <&cpg 722>; |
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| 114 | + reset-names = "du.0", "du.2"; |
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| 115 | + renesas,cmms = <&cmm0>, <&cmm1>, <&cmm2>, <&cmm3>; |
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| 116 | + renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, <&vspd0 1>; |
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82 | 117 | |
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83 | 118 | ports { |
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84 | 119 | #address-cells = <1>; |
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