modify sin led gpio

hc

2024-05-13 9d77db3c730780c8ef5ccd4b66403ff5675cfe4e

 kernel/Documentation/devicetree/bindings/display/msm/dsi.txt
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@@ -87,7 +87,11 @@
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   * "qcom,dsi-phy-20nm"
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   * "qcom,dsi-phy-28nm-8960"
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   * "qcom,dsi-phy-14nm"
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+  * "qcom,dsi-phy-14nm-660"
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   * "qcom,dsi-phy-10nm"
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+  * "qcom,dsi-phy-10nm-8998"
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+  * "qcom,dsi-phy-7nm"
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+  * "qcom,dsi-phy-7nm-8150"
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 - reg: Physical base address and length of the registers of PLL, PHY. Some
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   revisions require the PHY regulator base address, whereas others require the
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   PHY lane base address. See below for each PHY revision.
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@@ -96,7 +100,7 @@
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   * "dsi_pll"
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   * "dsi_phy"
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   * "dsi_phy_regulator"
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-  For DSI 14nm and 10nm PHYs:
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+  For DSI 14nm, 10nm and 7nm PHYs:
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   * "dsi_pll"
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   * "dsi_phy"
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   * "dsi_phy_lane"
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@@ -106,6 +110,7 @@
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 - clocks: Phandles to device clocks. See [1] for details on clock bindings.
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 - clock-names: the following clocks are required:
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   * "iface"
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+  * "ref" (only required for new DTS files/entries)
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   For 28nm HPM/LP, 28nm 8960 PHYs:
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 - vddio-supply: phandle to vdd-io regulator device node
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   For 20nm PHY:
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@@ -113,7 +118,7 @@
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 - vcca-supply: phandle to vcca regulator device node
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   For 14nm PHY:
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 - vcca-supply: phandle to vcca regulator device node
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-  For 10nm PHY:
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+  For 10nm and 7nm PHY:
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 - vdds-supply: phandle to vdds regulator device node
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 Optional properties: