modify sin led gpio

hc

2024-05-13 9d77db3c730780c8ef5ccd4b66403ff5675cfe4e

 kernel/Documentation/devicetree/bindings/display/msm/dpu.txt
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@@ -8,7 +8,7 @@
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 MDSS:
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 Required properties:
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-- compatible: "qcom,sdm845-mdss"
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+- compatible:  "qcom,sdm845-mdss", "qcom,sc7180-mdss"
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 - reg: physical base address and length of contoller's registers.
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 - reg-names: register region names. The following region is required:
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   * "mdss"
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@@ -28,6 +28,11 @@
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 - #address-cells: number of address cells for the MDSS children. Should be 1.
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 - #size-cells: Should be 1.
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 - ranges: parent bus address space is the same as the child bus address space.
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+- interconnects : interconnect path specifier for MDSS according to
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+  Documentation/devicetree/bindings/interconnect/interconnect.txt. Should be
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+  2 paths corresponding to 2 AXI ports.
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+- interconnect-names : MDSS will have 2 port names to differentiate between the
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+  2 interconnect paths defined with interconnect specifier.
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 Optional properties:
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 - assigned-clocks: list of clock specifiers for clocks needing rate assignment
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@@ -36,7 +41,7 @@
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 MDP:
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 Required properties:
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-- compatible: "qcom,sdm845-dpu"
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+- compatible: "qcom,sdm845-dpu", "qcom,sc7180-dpu"
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 - reg: physical base address and length of controller's registers.
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 - reg-names : register region names. The following region is required:
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   * "mdp"
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@@ -86,6 +91,11 @@
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 		interrupt-controller;
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 		#interrupt-cells = <1>;
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+		interconnects = <&rsc_hlos MASTER_MDP0 &rsc_hlos SLAVE_EBI1>,
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+				<&rsc_hlos MASTER_MDP1 &rsc_hlos SLAVE_EBI1>;
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+
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+		interconnect-names = "mdp0-mem", "mdp1-mem";
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+
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 		iommus = <&apps_iommu 0>;
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 		#address-cells = <2>;