forked from ~ljy/RK356X_SDK_RELEASE

hc
2024-05-13 9d77db3c730780c8ef5ccd4b66403ff5675cfe4e
kernel/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
....@@ -7,7 +7,7 @@
77
88 Required properties:
99 - compatible: "mediatek,<chip>-dsi"
10
- the supported chips are mt2701 and mt8173.
10
+- the supported chips are mt2701, mt7623, mt8173 and mt8183.
1111 - reg: Physical base address and length of the controller's registers
1212 - interrupts: The interrupt signal from the function block.
1313 - clocks: device clocks
....@@ -26,12 +26,19 @@
2626
2727 Required properties:
2828 - compatible: "mediatek,<chip>-mipi-tx"
29
- the supported chips are mt2701 and mt8173.
29
+- the supported chips are mt2701, 7623, mt8173 and mt8183.
3030 - reg: Physical base address and length of the controller's registers
3131 - clocks: PLL reference clock
3232 - clock-output-names: name of the output clock line to the DSI encoder
3333 - #clock-cells: must be <0>;
3434 - #phy-cells: must be <0>.
35
+
36
+Optional properties:
37
+- drive-strength-microamp: adjust driving current, should be 3000 ~ 6000. And
38
+ the step is 200.
39
+- nvmem-cells: A phandle to the calibration data provided by a nvmem device. If
40
+ unspecified default values shall be used.
41
+- nvmem-cell-names: Should be "calibration-data"
3542
3643 Example:
3744
....@@ -42,6 +49,9 @@
4249 clock-output-names = "mipi_tx0_pll";
4350 #clock-cells = <0>;
4451 #phy-cells = <0>;
52
+ drive-strength-microamp = <4600>;
53
+ nvmem-cells= <&mipi_tx_calibration>;
54
+ nvmem-cell-names = "calibration-data";
4555 };
4656
4757 dsi0: dsi@1401b000 {