modify sin led gpio

hc

2024-05-13 9d77db3c730780c8ef5ccd4b66403ff5675cfe4e

 kernel/Documentation/devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt
..
..
@@ -9,11 +9,9 @@
9
9
   See ../clocks/clock-bindings.txt for details.
10
10
 - clock-names: Must include the following entries:
11
11
   - cpu_g: Clock mux for the fast CPU cluster.
12
-  - cpu_lp: Clock mux for the low-power CPU cluster.
13
12
   - pll_x: Fast PLL clocksource.
14
13
   - pll_p: Auxiliary PLL used during fast PLL rate changes.
15
14
   - dfll: Fast DFLL clocksource that also automatically scales CPU voltage.
16
-- vdd-cpu-supply: Regulator for CPU voltage
17
15
 
18
16
 Optional properties:
19
17
 - clock-latency: Specify the possible maximum transition latency for clock,
..
..
@@ -31,13 +29,11 @@
31
29
 		reg = <0>;
32
30
 
33
31
 		clocks = <&tegra_car TEGRA124_CLK_CCLK_G>,
34
-			 <&tegra_car TEGRA124_CLK_CCLK_LP>,
35
32
 			 <&tegra_car TEGRA124_CLK_PLL_X>,
36
33
 			 <&tegra_car TEGRA124_CLK_PLL_P>,
37
34
 			 <&dfll>;
38
-		clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll";
35
+		clock-names = "cpu_g", "pll_x", "pll_p", "dfll";
39
36
 		clock-latency = <300000>;
40
-		vdd-cpu-supply: <&vdd_cpu>;
41
37
 	};
42
38
 
43
39
 	<...>