modify sin led gpio

hc

2024-05-13 9d77db3c730780c8ef5ccd4b66403ff5675cfe4e

 kernel/Documentation/devicetree/bindings/bus/imx-weim.txt
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@@ -44,12 +44,16 @@
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 			what bootloader sets up in IOMUXC_GPR1[11:0] will be
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 			used.
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+ - fsl,burst-clk-enable	For "fsl,imx50-weim" and "fsl,imx6q-weim" type of
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+			devices, the presence of this property indicates that
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+			the weim bus should operate in Burst Clock Mode.
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+
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 Timing property for child nodes. It is mandatory, not optional.
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  - fsl,weim-cs-timing:	The timing array, contains timing values for the
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-			child node. We can get the CS index from the child
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-			node's "reg" property. The number of registers depends
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-			on the selected chip.
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+			child node. We get the CS indexes from the address
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+			ranges in the child node's "reg" property.
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+			The number of registers depends on the selected chip:
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 			For i.MX1, i.MX21 ("fsl,imx1-weim") there are two
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 			registers: CSxU, CSxL.
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 			For i.MX25, i.MX27, i.MX31 and i.MX35 ("fsl,imx27-weim")
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@@ -80,3 +84,29 @@
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 					0x0000c000 0x1404a38e 0x00000000>;
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 		};
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 	};
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+
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+Example for an imx6q-based board, a multi-chipselect device connected to WEIM:
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+
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+In this case, both chip select 0 and 1 will be configured with the same timing
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+array values.
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+
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+	weim: weim@21b8000 {
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+		compatible = "fsl,imx6q-weim";
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+		reg = <0x021b8000 0x4000>;
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+		clocks = <&clks 196>;
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+		#address-cells = <2>;
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+		#size-cells = <1>;
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+		ranges = <0 0 0x08000000 0x02000000
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+			  1 0 0x0a000000 0x02000000
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+			  2 0 0x0c000000 0x02000000
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+			  3 0 0x0e000000 0x02000000>;
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+		fsl,weim-cs-gpr = <&gpr>;
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+
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+		acme@0 {
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+			compatible = "acme,whatever";
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+			reg = <0 0 0x100>, <0 0x400000 0x800>,
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+				<1 0x400000 0x800>;
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+			fsl,weim-cs-timing = <0x024400b1 0x00001010 0x20081100
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+				0x00000000 0xa0000240 0x00000000>;
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+		};
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+	};