.. | .. |
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21 | 21 | the register region. An optional second element specifies |
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22 | 22 | the base address and size of the alias register region. |
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23 | 23 | |
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| 24 | +- clocks: |
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| 25 | + Usage: required |
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| 26 | + Value type: <prop-encoded-array> |
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| 27 | + Definition: reference to the pll parents. |
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| 28 | + |
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| 29 | +- clock-names: |
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| 30 | + Usage: required |
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| 31 | + Value type: <stringlist> |
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| 32 | + Definition: must be "pll8_vote", "pxo". |
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| 33 | + |
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| 34 | +- clock-output-names: |
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| 35 | + Usage: optional |
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| 36 | + Value type: <string> |
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| 37 | + Definition: Name of the output clock. Typically acpuX_aux where X is a |
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| 38 | + CPU number starting at 0. |
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| 39 | + |
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24 | 40 | Example: |
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25 | 41 | |
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26 | 42 | clock-controller@2088000 { |
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27 | 43 | compatible = "qcom,kpss-acc-v2"; |
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28 | 44 | reg = <0x02088000 0x1000>, |
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29 | 45 | <0x02008000 0x1000>; |
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| 46 | + clocks = <&gcc PLL8_VOTE>, <&gcc PXO_SRC>; |
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| 47 | + clock-names = "pll8_vote", "pxo"; |
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| 48 | + clock-output-names = "acpu0_aux"; |
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30 | 49 | }; |
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