add ax88772_rst

hc

2024-05-10 9999e48639b3cecb08ffb37358bcba3b48161b29

 u-boot/drivers/video/drm/dw_hdmi_qp.c
..
..
@@ -175,6 +175,9 @@
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 	case MEDIA_BUS_FMT_UYVY8_1X16:
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 	case MEDIA_BUS_FMT_UYVY10_1X20:
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 	case MEDIA_BUS_FMT_UYVY12_1X24:
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+	case MEDIA_BUS_FMT_YUYV8_1X16:
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+	case MEDIA_BUS_FMT_YUYV10_1X20:
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+	case MEDIA_BUS_FMT_YUYV12_1X24:
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 		return true;
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 	default:
..
..
@@ -1047,6 +1050,9 @@
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 	/* HDMI Initialization Step B.2 */
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 	hdmi->phy.ops->set_pll(conn, hdmi->rk_hdmi, state);
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1052
 
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+	/* Mark yuv422 10bit */
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+	if (hdmi->hdmi_data.enc_out_bus_format == MEDIA_BUS_FMT_YUYV10_1X20)
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+		hdmi_writel(hdmi, BIT(20), VIDEO_INTERFACE_CONFIG0);
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 	rk3588_set_grf_cfg(hdmi->rk_hdmi);
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 	link_cfg = dw_hdmi_rockchip_get_link_cfg(hdmi->rk_hdmi);
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1058
 
..
..
@@ -1094,6 +1100,9 @@
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 		hdmi->phy.enabled = true;
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 		printf("%s DVI mode\n", __func__);
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 	}
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+
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+	/* Mark uboot hdmi is enabled */
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+	hdmi_writel(hdmi, BIT(21), VIDEO_INTERFACE_CONFIG0);
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 	return 0;
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 }
..
..
@@ -1239,9 +1248,23 @@
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 	return 0;
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 }
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1242
-int rockchip_dw_hdmi_qp_get_timing(struct rockchip_connector *conn, struct display_state *state)
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+static void rockchip_dw_hdmi_qp_mode_valid(struct dw_hdmi_qp *hdmi)
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 {
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-	int ret, i;
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+	struct hdmi_edid_data *edid_data = &hdmi->edid_data;
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+	int i;
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+
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+	for (i = 0; i < edid_data->modes; i++) {
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+		if (edid_data->mode_buf[i].invalid)
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+			continue;
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+		if (edid_data->mode_buf[i].clock <= 25000)
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+			edid_data->mode_buf[i].invalid = true;
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+	}
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+}
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+
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+static int _rockchip_dw_hdmi_qp_get_timing(struct rockchip_connector *conn,
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+					   struct display_state *state, int edid_status)
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+{
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+	int i;
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 	struct connector_state *conn_state = &state->conn_state;
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 	struct drm_display_mode *mode = &conn_state->mode;
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 	struct dw_hdmi_qp *hdmi = conn->data;
..
..
@@ -1254,14 +1277,13 @@
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 	if (!hdmi)
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 		return -EFAULT;
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1279
 
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-	ret = drm_do_get_edid(&hdmi->adap, conn_state->edid);
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-	if (!ret) {
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+	if (!edid_status) {
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 		hdmi->sink_is_hdmi =
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 			drm_detect_hdmi_monitor(edid);
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 		hdmi->sink_has_audio = drm_detect_monitor_audio(edid);
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-		ret = drm_add_edid_modes(&hdmi->edid_data, conn_state->edid);
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+		edid_status = drm_add_edid_modes(&hdmi->edid_data, conn_state->edid);
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 	}
1264
-	if (ret < 0) {
1286
+	if (edid_status < 0) {
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 		hdmi->sink_is_hdmi = true;
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1288
 		hdmi->sink_has_audio = true;
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 		do_cea_modes(&hdmi->edid_data, def_modes_vic,
..
..
@@ -1270,8 +1292,7 @@
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 		printf("failed to get edid\n");
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 	}
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 	drm_rk_filter_whitelist(&hdmi->edid_data);
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-	if (hdmi->phy.ops->mode_valid)
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-		hdmi->phy.ops->mode_valid(hdmi->rk_hdmi, state);
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+	rockchip_dw_hdmi_qp_mode_valid(hdmi);
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 	drm_mode_max_resolution_filter(&hdmi->edid_data,
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 				       &state->crtc_state.max_output);
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 	if (!drm_mode_prune_invalid(&hdmi->edid_data)) {
..
..
@@ -1298,15 +1319,17 @@
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1319
 	hdmi->hdmi_data.enc_out_bus_format = bus_format;
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1320
 
1300
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 	switch (bus_format) {
1301
-	case MEDIA_BUS_FMT_UYVY10_1X20:
1302
-		conn_state->bus_format = MEDIA_BUS_FMT_YUV10_1X30;
1322
+	case MEDIA_BUS_FMT_YUYV10_1X20:
1323
+		conn_state->bus_format = MEDIA_BUS_FMT_YUYV10_1X20;
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 		hdmi->hdmi_data.enc_in_bus_format =
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-			MEDIA_BUS_FMT_YUV10_1X30;
1325
+			MEDIA_BUS_FMT_YUYV10_1X20;
1326
+		conn_state->output_mode = ROCKCHIP_OUT_MODE_YUV422;
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 		break;
1306
-	case MEDIA_BUS_FMT_UYVY8_1X16:
1307
-		conn_state->bus_format = MEDIA_BUS_FMT_YUV8_1X24;
1328
+	case MEDIA_BUS_FMT_YUYV8_1X16:
1329
+		conn_state->bus_format = MEDIA_BUS_FMT_YUYV8_1X16;
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1330
 		hdmi->hdmi_data.enc_in_bus_format =
1309
-			MEDIA_BUS_FMT_YUV8_1X24;
1331
+			MEDIA_BUS_FMT_YUYV8_1X16;
1332
+		conn_state->output_mode = ROCKCHIP_OUT_MODE_YUV422;
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1333
 		break;
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1334
 	case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
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1335
 	case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
..
..
@@ -1334,6 +1357,21 @@
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 	return 0;
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1358
 }
1336
1359
 
1360
+int rockchip_dw_hdmi_qp_get_timing(struct rockchip_connector *conn, struct display_state *state)
1361
+{
1362
+	struct connector_state *conn_state = &state->conn_state;
1363
+	struct dw_hdmi_qp *hdmi = conn->data;
1364
+	int ret;
1365
+
1366
+	ret = drm_do_get_edid(&hdmi->adap, conn_state->edid);
1367
+
1368
+	if (conn_state->secondary)
1369
+		_rockchip_dw_hdmi_qp_get_timing(conn_state->secondary, state, ret);
1370
+
1371
+	return _rockchip_dw_hdmi_qp_get_timing(conn, state, ret);
1372
+}
1373
+
1374
+
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1375
 int rockchip_dw_hdmi_qp_detect(struct rockchip_connector *conn, struct display_state *state)
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1376
 {
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 	int ret;