forked from ~ljy/RK356X_SDK_RELEASE
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hc
2024-05-10 9999e48639b3cecb08ffb37358bcba3b48161b29 
 u-boot/drivers/crypto/rockchip/crypto_v2.c
....@@ -8,6 +8,7 @@
88 #include <crypto.h>
99 #include <dm.h>
1010 #include <asm/io.h>
11
+#include <clk-uclass.h>
1112 #include <asm/arch/hardware.h>
1213 #include <asm/arch/clock.h>
1314 #include <rockchip/crypto_hash_cache.h>
....@@ -54,6 +55,7 @@
5455 	char				*clocks;
5556 	u32				*frequencies;
5657 	u32				nclocks;
58
+	u32				freq_nclocks;
5759 	u32				length;
5860 	struct rk_hash_ctx		*hw_ctx;
5961 	struct rk_crypto_soc_data	*soc_data;
....@@ -217,6 +219,43 @@
217219 
218220 	for (i = 0; i < tag_len / 4; i++, chn_base += 4)
219221 		word2byte_be(crypto_read(chn_base), tag + 4 * i);
222
+}
223
+
224
+static int rk_crypto_do_enable_clk(struct udevice *dev, int enable)
225
+{
226
+	struct rockchip_crypto_priv *priv = dev_get_priv(dev);
227
+	struct clk clk;
228
+	int i, ret;
229
+
230
+	for (i = 0; i < priv->nclocks; i++) {
231
+		ret = clk_get_by_index(dev, i, &clk);
232
+		if (ret < 0) {
233
+			printf("Failed to get clk index %d, ret=%d\n", i, ret);
234
+			return ret;
235
+		}
236
+
237
+		if (enable)
238
+			ret = clk_enable(&clk);
239
+		else
240
+			ret = clk_disable(&clk);
241
+		if (ret < 0 && ret != -ENOSYS) {
242
+			printf("Failed to enable(%d) clk(%ld): ret=%d\n",
243
+			       enable, clk.id, ret);
244
+			return ret;
245
+		}
246
+	}
247
+
248
+	return 0;
249
+}
250
+
251
+static int rk_crypto_enable_clk(struct udevice *dev)
252
+{
253
+	return rk_crypto_do_enable_clk(dev, 1);
254
+}
255
+
256
+static int rk_crypto_disable_clk(struct udevice *dev)
257
+{
258
+	return rk_crypto_do_enable_clk(dev, 0);
220259 }
221260 
222261 static u32 crypto_v3_dynamic_cap(void)
....@@ -397,7 +436,7 @@
397436 
398437 	if (!(*started_flag)) {
399438 		lli->user_define |=
400
-			(LLI_USER_STRING_START | LLI_USER_CPIHER_START);
439
+			(LLI_USER_STRING_START | LLI_USER_CIPHER_START);
401440 		crypto_write((u32)virt_to_phys(lli), CRYPTO_DMA_LLI_ADDR);
402441 		crypto_write((CRYPTO_HASH_ENABLE << CRYPTO_WRITE_MASK_SHIFT) |
403442 			     CRYPTO_HASH_ENABLE, CRYPTO_HASH_CTL);
....@@ -520,6 +559,7 @@
520559 {
521560 	struct rockchip_crypto_priv *priv = dev_get_priv(dev);
522561 	struct rk_hash_ctx *hash_ctx = priv->hw_ctx;
562
+	int ret = 0;
523563 
524564 	if (!ctx)
525565 		return -EINVAL;
....@@ -535,7 +575,12 @@
535575 	if (!hash_ctx->hash_cache)
536576 		return -EFAULT;
537577 
538
-	return rk_hash_init(hash_ctx, ctx->algo);
578
+	rk_crypto_enable_clk(dev);
579
+	ret = rk_hash_init(hash_ctx, ctx->algo);
580
+	if (ret)
581
+		rk_crypto_disable_clk(dev);
582
+
583
+	return ret;
539584 }
540585 
541586 static int rockchip_crypto_sha_update(struct udevice *dev,
....@@ -545,8 +590,10 @@
545590 	int ret, i;
546591 	u8 *p;
547592 
548
-	if (!len)
549
-		return -EINVAL;
593
+	if (!len) {
594
+		ret = -EINVAL;
595
+		goto exit;
596
+	}
550597 
551598 	p = (u8 *)input;
552599 
....@@ -560,6 +607,9 @@
560607 		ret = rk_hash_update(priv->hw_ctx, p, len % HASH_UPDATE_LIMIT);
561608 
562609 exit:
610
+	if (ret)
611
+		rk_crypto_disable_clk(dev);
612
+
563613 	return ret;
564614 }
565615 
....@@ -583,6 +633,8 @@
583633 
584634 exit:
585635 	hw_hash_clean_ctx(priv->hw_ctx);
636
+	rk_crypto_disable_clk(dev);
637
+
586638 	return ret;
587639 }
588640 
....@@ -614,6 +666,7 @@
614666 {
615667 	struct rockchip_crypto_priv *priv = dev_get_priv(dev);
616668 	struct rk_hash_ctx *hash_ctx = priv->hw_ctx;
669
+	int ret = 0;
617670 
618671 	if (!ctx)
619672 		return -EINVAL;
....@@ -629,7 +682,12 @@
629682 	if (!hash_ctx->hash_cache)
630683 		return -EFAULT;
631684 
632
-	return rk_hmac_init(priv->hw_ctx, ctx->algo, key, key_len);
685
+	rk_crypto_enable_clk(dev);
686
+	ret = rk_hmac_init(priv->hw_ctx, ctx->algo, key, key_len);
687
+	if (ret)
688
+		rk_crypto_disable_clk(dev);
689
+
690
+	return ret;
633691 }
634692 
635693 static int rockchip_crypto_hmac_update(struct udevice *dev,
....@@ -763,6 +821,11 @@
763821 {
764822 	u32 i;
765823 
824
+	if (aad_len == 0) {
825
+		*padding_size = 0;
826
+		return;
827
+	}
828
+
766829 	i = aad_len < (0x10000 - 0x100) ? 2 : 6;
767830 
768831 	if (i == 2) {
....@@ -779,7 +842,7 @@
779842 	*padding_size = i;
780843 }
781844 
782
-static int ccm_compose_aad_iv(u8 *aad_iv, u32 data_len, u32 tag_size)
845
+static int ccm_compose_aad_iv(u8 *aad_iv, u32 data_len, u32 aad_len, u32 tag_size)
783846 {
784847 	aad_iv[0] |= ((u8)(((tag_size - 2) / 2) & 7) << 3);
785848 
....@@ -788,7 +851,8 @@
788851 	aad_iv[14] = (u8)(data_len >> 8);
789852 	aad_iv[15] = (u8)data_len;
790853 
791
-	aad_iv[0] |= 0x40;	//set aad flag
854
+	if (aad_len)
855
+		aad_iv[0] |= 0x40;	//set aad flag
792856 
793857 	return 0;
794858 }
....@@ -925,12 +989,14 @@
925989 		data_desc->dma_ctrl |= LLI_DMA_CTRL_DST_DONE;
926990 	}
927991 
992
+	data_desc->user_define = LLI_USER_CIPHER_START |
993
+				 LLI_USER_STRING_START |
994
+				 LLI_USER_STRING_LAST |
995
+				 (key_chn << 4);
996
+	crypto_write((u32)virt_to_phys(data_desc), CRYPTO_DMA_LLI_ADDR);
997
+
928998 	if (rk_mode == RK_MODE_CCM || rk_mode == RK_MODE_GCM) {
929999 		u32 aad_tmp_len = 0;
930
-
931
-		data_desc->user_define = LLI_USER_STRING_START |
932
-					 LLI_USER_STRING_LAST |
933
-					 (key_chn << 4);
9341000 
9351001 		aad_desc = align_malloc(sizeof(*aad_desc), LLI_ADDR_ALIGN_SIZE);
9361002 		if (!aad_desc)
....@@ -938,7 +1004,7 @@
9381004 
9391005 		memset(aad_desc, 0x00, sizeof(*aad_desc));
9401006 		aad_desc->next_addr = (u32)virt_to_phys(data_desc);
941
-		aad_desc->user_define = LLI_USER_CPIHER_START |
1007
+		aad_desc->user_define = LLI_USER_CIPHER_START |
9421008 					 LLI_USER_STRING_START |
9431009 					 LLI_USER_STRING_LAST |
9441010 					 LLI_USER_STRING_AAD |
....@@ -958,12 +1024,15 @@
9581024 			if (!aad_tmp)
9591025 				goto exit;
9601026 
961
-			/* read iv data from reg */
962
-			get_iv_reg(key_chn, aad_tmp, AES_BLOCK_SIZE);
963
-			ccm_compose_aad_iv(aad_tmp, tmp_len, tag_len);
964
-			memcpy(aad_tmp + AES_BLOCK_SIZE, padding, padding_size);
1027
+			/* clear last block */
9651028 			memset(aad_tmp + aad_tmp_len - AES_BLOCK_SIZE,
9661029 			       0x00, AES_BLOCK_SIZE);
1030
+
1031
+			/* read iv data from reg */
1032
+			get_iv_reg(key_chn, aad_tmp, AES_BLOCK_SIZE);
1033
+			ccm_compose_aad_iv(aad_tmp, tmp_len, aad_len, tag_len);
1034
+			memcpy(aad_tmp + AES_BLOCK_SIZE, padding, padding_size);
1035
+
9671036 			memcpy(aad_tmp + AES_BLOCK_SIZE + padding_size,
9681037 			       aad, aad_len);
9691038 		} else {
....@@ -985,15 +1054,15 @@
9851054 
9861055 		aad_desc->src_addr = (u32)virt_to_phys(aad_tmp);
9871056 		aad_desc->src_len  = aad_tmp_len;
988
-		crypto_write((u32)virt_to_phys(aad_desc), CRYPTO_DMA_LLI_ADDR);
989
-		cache_op_inner(DCACHE_AREA_CLEAN, aad_tmp, aad_tmp_len);
990
-		cache_op_inner(DCACHE_AREA_CLEAN, aad_desc, sizeof(*aad_desc));
991
-	} else {
992
-		data_desc->user_define = LLI_USER_CPIHER_START |
993
-					 LLI_USER_STRING_START |
994
-					 LLI_USER_STRING_LAST |
995
-					 (key_chn << 4);
996
-		crypto_write((u32)virt_to_phys(data_desc), CRYPTO_DMA_LLI_ADDR);
1057
+
1058
+		if (aad_tmp_len) {
1059
+			data_desc->user_define = LLI_USER_STRING_START |
1060
+						 LLI_USER_STRING_LAST |
1061
+						 (key_chn << 4);
1062
+			crypto_write((u32)virt_to_phys(aad_desc), CRYPTO_DMA_LLI_ADDR);
1063
+			cache_op_inner(DCACHE_AREA_CLEAN, aad_tmp, aad_tmp_len);
1064
+			cache_op_inner(DCACHE_AREA_CLEAN, aad_desc, sizeof(*aad_desc));
1065
+		}
9971066 	}
9981067 
9991068 	cache_op_inner(DCACHE_AREA_CLEAN, data_desc, sizeof(*data_desc));
....@@ -1175,21 +1244,29 @@
11751244 int rockchip_crypto_cipher(struct udevice *dev, cipher_context *ctx,
11761245 			   const u8 *in, u8 *out, u32 len, bool enc)
11771246 {
1247
+	int ret;
1248
+
1249
+	rk_crypto_enable_clk(dev);
1250
+
11781251 	switch (ctx->algo) {
11791252 	case CRYPTO_DES:
1180
-		return rk_crypto_des(dev, ctx->mode, ctx->key, ctx->key_len,
1181
-				     ctx->iv, in, out, len, enc);
1253
+		ret = rk_crypto_des(dev, ctx->mode, ctx->key, ctx->key_len,
1254
+				    ctx->iv, in, out, len, enc);
11821255 	case CRYPTO_AES:
1183
-		return rk_crypto_aes(dev, ctx->mode,
1184
-				     ctx->key, ctx->twk_key, ctx->key_len,
1185
-				     ctx->iv, ctx->iv_len, in, out, len, enc);
1256
+		ret = rk_crypto_aes(dev, ctx->mode,
1257
+				    ctx->key, ctx->twk_key, ctx->key_len,
1258
+				    ctx->iv, ctx->iv_len, in, out, len, enc);
11861259 	case CRYPTO_SM4:
1187
-		return rk_crypto_sm4(dev, ctx->mode,
1188
-				     ctx->key, ctx->twk_key, ctx->key_len,
1189
-				     ctx->iv, ctx->iv_len, in, out, len, enc);
1260
+		ret = rk_crypto_sm4(dev, ctx->mode,
1261
+				    ctx->key, ctx->twk_key, ctx->key_len,
1262
+				    ctx->iv, ctx->iv_len, in, out, len, enc);
11901263 	default:
1191
-		return -EINVAL;
1264
+		ret = -EINVAL;
11921265 	}
1266
+
1267
+	rk_crypto_disable_clk(dev);
1268
+
1269
+	return ret;
11931270 }
11941271 
11951272 int rk_crypto_mac(struct udevice *dev, u32 algo, u32 mode,
....@@ -1223,8 +1300,16 @@
12231300 int rockchip_crypto_mac(struct udevice *dev, cipher_context *ctx,
12241301 			const u8 *in, u32 len, u8 *tag)
12251302 {
1226
-	return rk_crypto_mac(dev, ctx->algo, ctx->mode,
1227
-			     ctx->key, ctx->key_len, in, len, tag);
1303
+	int ret = 0;
1304
+
1305
+	rk_crypto_enable_clk(dev);
1306
+
1307
+	ret = rk_crypto_mac(dev, ctx->algo, ctx->mode,
1308
+			    ctx->key, ctx->key_len, in, len, tag);
1309
+
1310
+	rk_crypto_disable_clk(dev);
1311
+
1312
+	return ret;
12281313 }
12291314 
12301315 int rk_crypto_ae(struct udevice *dev, u32 algo, u32 mode,
....@@ -1236,6 +1321,9 @@
12361321 	int ret;
12371322 
12381323 	if (!IS_AE_MODE(rk_mode))
1324
+		return -EINVAL;
1325
+
1326
+	if (len == 0)
12391327 		return -EINVAL;
12401328 
12411329 	if (algo != CRYPTO_AES && algo != CRYPTO_SM4)
....@@ -1261,9 +1349,17 @@
12611349 		       u8 *out, u8 *tag)
12621350 
12631351 {
1264
-	return rk_crypto_ae(dev, ctx->algo, ctx->mode, ctx->key, ctx->key_len,
1265
-			    ctx->iv, ctx->iv_len, in, len,
1266
-			    aad, aad_len, out, tag);
1352
+	int ret = 0;
1353
+
1354
+	rk_crypto_enable_clk(dev);
1355
+
1356
+	ret = rk_crypto_ae(dev, ctx->algo, ctx->mode, ctx->key, ctx->key_len,
1357
+			   ctx->iv, ctx->iv_len, in, len,
1358
+			   aad, aad_len, out, tag);
1359
+
1360
+	rk_crypto_disable_clk(dev);
1361
+
1362
+	return ret;
12671363 }
12681364 
12691365 #endif
....@@ -1312,9 +1408,11 @@
13121408 	if (ret)
13131409 		goto exit;
13141410 
1411
+	rk_crypto_enable_clk(dev);
13151412 	ret = rk_exptmod_np(mpa_m, mpa_e, mpa_n, mpa_c, mpa_result);
13161413 	if (!ret)
13171414 		memcpy(output, mpa_result->d, BITS2BYTE(n_bits));
1415
+	rk_crypto_disable_clk(dev);
13181416 
13191417 exit:
13201418 	rk_mpa_free(&mpa_m);
....@@ -1378,7 +1476,7 @@
13781476 	if (!priv->clocks)
13791477 		return -ENOMEM;
13801478 
1381
-	priv->nclocks = len / sizeof(u32);
1479
+	priv->nclocks = len / (2 * sizeof(u32));
13821480 	if (dev_read_u32_array(dev, "clocks", (u32 *)priv->clocks,
13831481 			       priv->nclocks)) {
13841482 		printf("Can't read \"clocks\" property\n");
....@@ -1386,24 +1484,19 @@
13861484 		goto exit;
13871485 	}
13881486 
1389
-	if (!dev_read_prop(dev, "clock-frequency", &len)) {
1390
-		printf("Can't find \"clock-frequency\" property\n");
1391
-		ret = -EINVAL;
1392
-		goto exit;
1393
-	}
1394
-
1395
-	priv->frequencies = malloc(len);
1396
-	if (!priv->frequencies) {
1397
-		ret = -ENOMEM;
1398
-		goto exit;
1399
-	}
1400
-
1401
-	priv->nclocks = len / sizeof(u32);
1402
-	if (dev_read_u32_array(dev, "clock-frequency", priv->frequencies,
1403
-			       priv->nclocks)) {
1404
-		printf("Can't read \"clock-frequency\" property\n");
1405
-		ret = -EINVAL;
1406
-		goto exit;
1487
+	if (dev_read_prop(dev, "clock-frequency", &len)) {
1488
+		priv->frequencies = malloc(len);
1489
+		if (!priv->frequencies) {
1490
+			ret = -ENOMEM;
1491
+			goto exit;
1492
+		}
1493
+		priv->freq_nclocks = len / sizeof(u32);
1494
+		if (dev_read_u32_array(dev, "clock-frequency", priv->frequencies,
1495
+				       priv->freq_nclocks)) {
1496
+			printf("Can't read \"clock-frequency\" property\n");
1497
+			ret = -EINVAL;
1498
+			goto exit;
1499
+		}
14071500 	}
14081501 
14091502 	return 0;
....@@ -1423,10 +1516,15 @@
14231516 	struct clk clk;
14241517 	int i, ret;
14251518 
1426
-	if (!priv->clocks && priv->nclocks == 0)
1519
+	/* use standard "assigned-clock-rates" props */
1520
+	if (dev_read_size(dev, "assigned-clock-rates") > 0)
1521
+		return clk_set_defaults(dev);
1522
+
1523
+	/* use "clock-frequency" props */
1524
+	if (priv->freq_nclocks == 0)
14271525 		return 0;
14281526 
1429
-	for (i = 0; i < priv->nclocks; i++) {
1527
+	for (i = 0; i < priv->freq_nclocks; i++) {
14301528 		ret = clk_get_by_index(dev, i, &clk);
14311529 		if (ret < 0) {
14321530 			printf("Failed to get clk index %d, ret=%d\n", i, ret);
....@@ -1465,7 +1563,11 @@
14651563 	if (ret)
14661564 		return ret;
14671565 
1566
+	rk_crypto_enable_clk(dev);
1567
+
14681568 	hw_crypto_reset();
1569
+
1570
+	rk_crypto_disable_clk(dev);
14691571 
14701572 	return 0;
14711573 }
....@@ -1557,6 +1659,10 @@
15571659 		.compatible = "rockchip,crypto-v3",
15581660 		.data = (ulong)&soc_data_cryptov3
15591661 	},
1662
+	{
1663
+		.compatible = "rockchip,crypto-v4",
1664
+		.data = (ulong)&soc_data_cryptov3 /* reuse crypto v3 config */
1665
+	},
15601666 	{ }
15611667 };
15621668