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| 56 | 56 | unsigned int next; |
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| 57 | 57 | |
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| 58 | 58 | /* |
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| 59 | | - * The IPI requires a seperate HW irq on each CPU. We require |
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| 59 | + * The IPI requires a separate HW irq on each CPU. We require |
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| 60 | 60 | * that the destination mask is consecutive. If an |
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| 61 | 61 | * implementation needs to support holes, it can reserve |
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| 62 | 62 | * several IPI ranges. |
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| .. | .. |
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| 172 | 172 | |
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| 173 | 173 | /* |
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| 174 | 174 | * Get the real hardware irq number if the underlying implementation |
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| 175 | | - * uses a seperate irq per cpu. If the underlying implementation uses |
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| 175 | + * uses a separate irq per cpu. If the underlying implementation uses |
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| 176 | 176 | * a single hardware irq for all cpus then the IPI send mechanism |
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| 177 | 177 | * needs to take care of the cpu destinations. |
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| 178 | 178 | */ |
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