.. | .. |
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| 1 | +/* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | + |
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1 | 3 | #ifndef __TI_SYSC_DATA_H__ |
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2 | 4 | #define __TI_SYSC_DATA_H__ |
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3 | 5 | |
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.. | .. |
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15 | 17 | TI_SYSC_OMAP4_MCASP, |
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16 | 18 | TI_SYSC_OMAP4_USB_HOST_FS, |
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17 | 19 | TI_SYSC_DRA7_MCAN, |
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| 20 | + TI_SYSC_PRUSS, |
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18 | 21 | }; |
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19 | 22 | |
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20 | 23 | struct ti_sysc_cookie { |
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21 | 24 | void *data; |
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| 25 | + void *clkdm; |
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22 | 26 | }; |
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23 | 27 | |
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24 | 28 | /** |
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.. | .. |
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46 | 50 | s8 emufree_shift; |
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47 | 51 | }; |
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48 | 52 | |
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49 | | -#define SYSC_QUIRK_RESOURCE_PROVIDER BIT(9) |
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50 | | -#define SYSC_QUIRK_LEGACY_IDLE BIT(8) |
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51 | | -#define SYSC_QUIRK_RESET_STATUS BIT(7) |
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| 53 | +#define SYSC_QUIRK_REINIT_ON_CTX_LOST BIT(28) |
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| 54 | +#define SYSC_QUIRK_REINIT_ON_RESUME BIT(27) |
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| 55 | +#define SYSC_QUIRK_GPMC_DEBUG BIT(26) |
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| 56 | +#define SYSC_MODULE_QUIRK_ENA_RESETDONE BIT(25) |
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| 57 | +#define SYSC_MODULE_QUIRK_PRUSS BIT(24) |
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| 58 | +#define SYSC_MODULE_QUIRK_DSS_RESET BIT(23) |
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| 59 | +#define SYSC_MODULE_QUIRK_RTC_UNLOCK BIT(22) |
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| 60 | +#define SYSC_QUIRK_CLKDM_NOAUTO BIT(21) |
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| 61 | +#define SYSC_QUIRK_FORCE_MSTANDBY BIT(20) |
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| 62 | +#define SYSC_MODULE_QUIRK_AESS BIT(19) |
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| 63 | +#define SYSC_MODULE_QUIRK_SGX BIT(18) |
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| 64 | +#define SYSC_MODULE_QUIRK_HDQ1W BIT(17) |
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| 65 | +#define SYSC_MODULE_QUIRK_I2C BIT(16) |
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| 66 | +#define SYSC_MODULE_QUIRK_WDT BIT(15) |
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| 67 | +#define SYSS_QUIRK_RESETDONE_INVERTED BIT(14) |
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| 68 | +#define SYSC_QUIRK_SWSUP_MSTANDBY BIT(13) |
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| 69 | +#define SYSC_QUIRK_SWSUP_SIDLE_ACT BIT(12) |
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| 70 | +#define SYSC_QUIRK_SWSUP_SIDLE BIT(11) |
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| 71 | +#define SYSC_QUIRK_EXT_OPT_CLOCK BIT(10) |
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| 72 | +#define SYSC_QUIRK_LEGACY_IDLE BIT(9) |
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| 73 | +#define SYSC_QUIRK_RESET_STATUS BIT(8) |
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| 74 | +#define SYSC_QUIRK_NO_IDLE BIT(7) |
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52 | 75 | #define SYSC_QUIRK_NO_IDLE_ON_INIT BIT(6) |
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53 | 76 | #define SYSC_QUIRK_NO_RESET_ON_INIT BIT(5) |
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54 | 77 | #define SYSC_QUIRK_OPT_CLKS_NEEDED BIT(4) |
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.. | .. |
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61 | 84 | |
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62 | 85 | /** |
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63 | 86 | * struct sysc_capabilities - capabilities for an interconnect target module |
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64 | | - * |
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| 87 | + * @type: sysc type identifier for the module |
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65 | 88 | * @sysc_mask: bitmask of supported SYSCONFIG register bits |
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66 | 89 | * @regbits: bitmask of SYSCONFIG register bits |
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67 | 90 | * @mod_quirks: bitmask of module specific quirks |
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.. | .. |
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76 | 99 | /** |
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77 | 100 | * struct sysc_config - configuration for an interconnect target module |
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78 | 101 | * @sysc_val: configured value for sysc register |
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| 102 | + * @syss_mask: configured mask value for SYSSTATUS register |
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79 | 103 | * @midlemodes: bitmask of supported master idle modes |
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80 | | - * @sidlemodes: bitmask of supported master idle modes |
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| 104 | + * @sidlemodes: bitmask of supported slave idle modes |
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81 | 105 | * @srst_udelay: optional delay needed after OCP soft reset |
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82 | 106 | * @quirks: bitmask of enabled quirks |
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83 | 107 | */ |
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.. | .. |
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121 | 145 | }; |
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122 | 146 | |
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123 | 147 | struct device; |
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| 148 | +struct clk; |
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124 | 149 | |
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125 | 150 | struct ti_sysc_platform_data { |
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126 | 151 | struct of_dev_auxdata *auxdata; |
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| 152 | + bool (*soc_type_gp)(void); |
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| 153 | + int (*init_clockdomain)(struct device *dev, struct clk *fck, |
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| 154 | + struct clk *ick, struct ti_sysc_cookie *cookie); |
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| 155 | + void (*clkdm_deny_idle)(struct device *dev, |
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| 156 | + const struct ti_sysc_cookie *cookie); |
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| 157 | + void (*clkdm_allow_idle)(struct device *dev, |
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| 158 | + const struct ti_sysc_cookie *cookie); |
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127 | 159 | int (*init_module)(struct device *dev, |
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128 | 160 | const struct ti_sysc_module_data *data, |
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129 | 161 | struct ti_sysc_cookie *cookie); |
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