add ax88772_rst

hc

2024-05-10 9999e48639b3cecb08ffb37358bcba3b48161b29

 kernel/drivers/usb/host/xhci-mem.c
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@@ -2236,7 +2236,7 @@
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 {
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 	u32 temp, port_offset, port_count;
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 	int i;
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-	u8 major_revision, minor_revision;
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+	u8 major_revision, minor_revision, tmp_minor_revision;
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 	struct xhci_hub *rhub;
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 	struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
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 	struct xhci_port_cap *port_cap;
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@@ -2256,6 +2256,15 @@
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 		 */
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 		if (minor_revision > 0x00 && minor_revision < 0x10)
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 			minor_revision <<= 4;
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+		/*
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+		 * Some zhaoxin's xHCI controller that follow usb3.1 spec
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+		 * but only support Gen1.
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+		 */
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+		if (xhci->quirks & XHCI_ZHAOXIN_HOST) {
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+			tmp_minor_revision = minor_revision;
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+			minor_revision = 0;
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+		}
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+
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 	} else if (major_revision <= 0x02) {
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 		rhub = &xhci->usb2_rhub;
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 	} else {
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@@ -2265,10 +2274,6 @@
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 		/* Ignoring port protocol we can't understand. FIXME */
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 		return;
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 	}
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-	rhub->maj_rev = XHCI_EXT_PORT_MAJOR(temp);
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-
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-	if (rhub->min_rev < minor_revision)
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-		rhub->min_rev = minor_revision;
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 	/* Port offset and count in the third dword, see section 7.2 */
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 	temp = readl(addr + 2);
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@@ -2287,8 +2292,6 @@
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 	if (xhci->num_port_caps > max_caps)
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 		return;
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-	port_cap->maj_rev = major_revision;
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-	port_cap->min_rev = minor_revision;
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 	port_cap->psi_count = XHCI_EXT_PORT_PSIC(temp);
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 	if (port_cap->psi_count) {
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@@ -2309,6 +2312,11 @@
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 				  XHCI_EXT_PORT_PSIV(port_cap->psi[i - 1])))
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 				port_cap->psi_uid_count++;
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+			if (xhci->quirks & XHCI_ZHAOXIN_HOST &&
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+			    major_revision == 0x03 &&
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+			    XHCI_EXT_PORT_PSIV(port_cap->psi[i]) >= 5)
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+				minor_revision = tmp_minor_revision;
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+
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 			xhci_dbg(xhci, "PSIV:%d PSIE:%d PLT:%d PFD:%d LP:%d PSIM:%d\n",
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 				  XHCI_EXT_PORT_PSIV(port_cap->psi[i]),
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 				  XHCI_EXT_PORT_PSIE(port_cap->psi[i]),
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@@ -2318,6 +2326,15 @@
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 				  XHCI_EXT_PORT_PSIM(port_cap->psi[i]));
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 		}
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 	}
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+
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+	rhub->maj_rev = major_revision;
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+
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+	if (rhub->min_rev < minor_revision)
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+		rhub->min_rev = minor_revision;
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+
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+	port_cap->maj_rev = major_revision;
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+	port_cap->min_rev = minor_revision;
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+
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 	/* cache usb2 port capabilities */
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 	if (major_revision < 0x03 && xhci->num_ext_caps < max_caps)
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 		xhci->ext_caps[xhci->num_ext_caps++] = temp;
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@@ -2568,8 +2585,12 @@
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 	 * and our use of dma addresses in the trb_address_map radix tree needs
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 	 * TRB_SEGMENT_SIZE alignment, so we pick the greater alignment need.
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 	 */
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-	xhci->segment_pool = dma_pool_create("xHCI ring segments", dev,
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-			TRB_SEGMENT_SIZE, TRB_SEGMENT_SIZE, xhci->page_size);
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+	if (xhci->quirks & XHCI_ZHAOXIN_TRB_FETCH)
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+		xhci->segment_pool = dma_pool_create("xHCI ring segments", dev,
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+				TRB_SEGMENT_SIZE * 2, TRB_SEGMENT_SIZE * 2, xhci->page_size * 2);
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+	else
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+		xhci->segment_pool = dma_pool_create("xHCI ring segments", dev,
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+				TRB_SEGMENT_SIZE, TRB_SEGMENT_SIZE, xhci->page_size);
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 	/* See Table 46 and Note on Figure 55 */
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 	xhci->device_pool = dma_pool_create("xHCI input/output contexts", dev,