add ax88772_rst

hc

2024-05-10 9999e48639b3cecb08ffb37358bcba3b48161b29

 kernel/drivers/net/phy/rk630phy.c
..
..
@@ -16,6 +16,7 @@
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 #include <linux/mfd/core.h>
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 #include <linux/mii.h>
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 #include <linux/netdevice.h>
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+#include <linux/nvmem-consumer.h>
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 #include <linux/of_irq.h>
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 #include <linux/phy.h>
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 #include <linux/platform_device.h>
..
..
@@ -24,6 +25,8 @@
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 #define RK630_PHY_ID				0x00441400
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26
 
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 /* PAGE 0 */
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+#define REG_MMD_ACCESS_CONTROL			0x0d
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+#define REG_MMD_ACCESS_DATA_ADDRESS		0x0e
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 #define REG_INTERRUPT_STATUS			0X10
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 #define REG_INTERRUPT_MASK			0X11
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 #define REG_GLOBAL_CONFIGURATION		0X13
..
..
@@ -50,6 +53,7 @@
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 #define REG_PAGE6_CP_CURRENT			0x17
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 #define REG_PAGE6_ADC_OP_BIAS			0x18
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 #define REG_PAGE6_RX_DECTOR			0x19
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+#define REG_PAGE6_TX_MOS_DRV			0x1B
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 #define REG_PAGE6_AFE_PDCW			0x1c
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58
 
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 /* PAGE 8 */
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@@ -61,15 +65,51 @@
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  * Addr: 1 --- RK630@S40
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  *       2 --- RV1106@T22
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  */
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-#define PHY_ADDR_S40 1
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-#define PHY_ADDR_T22 2
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+#define PHY_ADDR_S40				1
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+#define PHY_ADDR_T22				2
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+
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+#define T22_TX_LEVEL_100M			0x2d
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+#define T22_TX_LEVEL_10M			0x32
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73
 
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 struct rk630_phy_priv {
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 	struct phy_device *phydev;
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 	bool ieee;
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 	int wol_irq;
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 	struct wake_lock wol_wake_lock;
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+	int tx_level_100M;
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+	int tx_level_10M;
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 };
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+
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+static void rk630_phy_t22_get_tx_level_from_efuse(struct phy_device *phydev)
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+{
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+	struct rk630_phy_priv *priv = phydev->priv;
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+	unsigned int tx_level_100M = T22_TX_LEVEL_100M;
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+	unsigned int tx_level_10M = T22_TX_LEVEL_10M;
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+	unsigned char *efuse_buf;
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+	struct nvmem_cell *cell;
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+	size_t len;
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+
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+	cell = nvmem_cell_get(&phydev->mdio.dev, "txlevel");
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+	if (IS_ERR(cell)) {
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+		phydev_err(phydev, "failed to get txlevel cell: %ld, use default\n",
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+			   PTR_ERR(cell));
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+	} else {
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+		efuse_buf = nvmem_cell_read(cell, &len);
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+		nvmem_cell_put(cell);
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+		if (!IS_ERR(efuse_buf)) {
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+			if (len == 2 && efuse_buf[0] > 0 && efuse_buf[1] > 0) {
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+				tx_level_100M = efuse_buf[1];
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+				tx_level_10M = efuse_buf[0];
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+			}
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+			kfree(efuse_buf);
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+		} else {
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+			phydev_err(phydev, "failed to get efuse buf, use default\n");
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+		}
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+	}
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+
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+	priv->tx_level_100M = tx_level_100M;
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+	priv->tx_level_10M = tx_level_10M;
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+}
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113
 
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 static void rk630_phy_wol_enable(struct phy_device *phydev)
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 {
..
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@@ -120,14 +160,33 @@
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 	phy_write(phydev, REG_PAGE_SEL, 0x0000);
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 }
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162
 
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-static void rk630_phy_set_uaps(struct phy_device *phydev)
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+static void rk630_phy_set_aps(struct phy_device *phydev, bool enable)
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+{
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+	u32 value;
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+
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+	/* Switch to page 1 */
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+	phy_write(phydev, REG_PAGE_SEL, 0x0100);
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+	value = phy_read(phydev, REG_PAGE1_APS_CTRL);
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+	if (enable)
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+		value |= BIT(15);
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+	else
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+		value &= ~BIT(15);
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+	phy_write(phydev, REG_PAGE1_APS_CTRL, value);
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+	/* Switch to page 0 */
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+	phy_write(phydev, REG_PAGE_SEL, 0x0000);
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+}
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+
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+static void rk630_phy_set_uaps(struct phy_device *phydev, bool enable)
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 {
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 	u32 value;
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 	/* Switch to page 1 */
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 	phy_write(phydev, REG_PAGE_SEL, 0x0100);
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 	value = phy_read(phydev, REG_PAGE1_UAPS_CONFIGURE);
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-	value |= BIT(15);
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+	if (enable)
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+		value |= BIT(15);
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+	else
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+		value &= ~BIT(15);
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 	phy_write(phydev, REG_PAGE1_UAPS_CONFIGURE, value);
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 	/* Switch to page 0 */
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 	phy_write(phydev, REG_PAGE_SEL, 0x0000);
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@@ -164,8 +223,12 @@
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223
 
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 static void rk630_phy_t22_config_init(struct phy_device *phydev)
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 {
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+	struct rk630_phy_priv *priv = phydev->priv;
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+
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 	/* Switch to page 1 */
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 	phy_write(phydev, REG_PAGE_SEL, 0x0100);
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+	/* Enable offset clock */
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+	phy_write(phydev, 0x10, 0xfbfe);
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 	/* Disable APS */
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 	phy_write(phydev, REG_PAGE1_APS_CTRL, 0x4824);
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 	/* Switch to page 2 */
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@@ -180,8 +243,13 @@
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 	phy_write(phydev, REG_PAGE6_GAIN_ANONTROL, 0x0400);
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 	/* PHYAFE EQ optimization */
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 	phy_write(phydev, REG_PAGE6_AFE_TX_CTRL, 0x1088);
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+
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+	if (priv->tx_level_100M <= 0 || priv->tx_level_10M <= 0)
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+		rk630_phy_t22_get_tx_level_from_efuse(phydev);
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+
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 	/* PHYAFE TX optimization */
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-	phy_write(phydev, REG_PAGE6_AFE_DRIVER2, 0x3030);
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+	phy_write(phydev, REG_PAGE6_AFE_DRIVER2,
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+		  (priv->tx_level_100M << 8) | priv->tx_level_10M);
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 	/* PHYAFE CP current optimization */
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 	phy_write(phydev, REG_PAGE6_CP_CURRENT, 0x0575);
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 	/* ADC OP BIAS optimization */
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@@ -190,14 +258,24 @@
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 	phy_write(phydev, REG_PAGE6_RX_DECTOR, 0x0408);
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 	/* PHYAFE PDCW optimization */
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 	phy_write(phydev, REG_PAGE6_AFE_PDCW, 0x8880);
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+	/* Add PHY Tx mos drive, reduce power noise/jitter */
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+	phy_write(phydev, REG_PAGE6_TX_MOS_DRV, 0x888e);
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 	/* Switch to page 8 */
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 	phy_write(phydev, REG_PAGE_SEL, 0x0800);
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 	/* Disable auto-cal */
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 	phy_write(phydev, REG_PAGE8_AUTO_CAL, 0x0844);
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+	/* Reatart offset calibration */
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+	phy_write(phydev, 0x13, 0xc096);
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 	/* Switch to page 0 */
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 	phy_write(phydev, REG_PAGE_SEL, 0x0000);
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+
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+	/* Disable eee mode advertised */
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+	phy_write(phydev, REG_MMD_ACCESS_CONTROL, 0x0007);
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+	phy_write(phydev, REG_MMD_ACCESS_DATA_ADDRESS, 0x003c);
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+	phy_write(phydev, REG_MMD_ACCESS_CONTROL, 0x4007);
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+	phy_write(phydev, REG_MMD_ACCESS_DATA_ADDRESS, 0x0000);
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 }
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 static int rk630_phy_config_init(struct phy_device *phydev)
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@@ -205,9 +283,16 @@
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 	switch (phydev->mdio.addr) {
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 	case PHY_ADDR_S40:
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 		rk630_phy_s40_config_init(phydev);
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+		/*
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+		 * Ultra Auto-Power Saving Mode (UAPS) is designed to
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+		 * save power when cable is not plugged into PHY.
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+		 */
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+		rk630_phy_set_uaps(phydev, true);
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 		break;
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 	case PHY_ADDR_T22:
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 		rk630_phy_t22_config_init(phydev);
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+		rk630_phy_set_aps(phydev, false);
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+		rk630_phy_set_uaps(phydev, false);
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 		break;
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 	default:
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 		phydev_err(phydev, "Unsupported address for current phy: %d\n",
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@@ -216,13 +301,25 @@
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 	}
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 	rk630_phy_ieee_set(phydev, true);
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-	/*
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-	 * Ultra Auto-Power Saving Mode (UAPS) is designed to
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-	 * save power when cable is not plugged into PHY.
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-	 */
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-	rk630_phy_set_uaps(phydev);
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 	return 0;
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+}
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+
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+static void rk630_link_change_notify(struct phy_device *phydev)
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+{
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+	unsigned int val;
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+
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+	if (phydev->state == PHY_RUNNING || phydev->state == PHY_NOLINK) {
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+		/* Switch to page 6 */
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+		phy_write(phydev, REG_PAGE_SEL, 0x0600);
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+		val = phy_read(phydev, REG_PAGE6_AFE_TX_CTRL);
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+		val &= ~GENMASK(14, 13);
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+		if (phydev->speed == SPEED_10 && phydev->link)
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+			val |= BIT(13);
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+		phy_write(phydev, REG_PAGE6_AFE_TX_CTRL, val);
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+		/* Switch to page 0 */
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+		phy_write(phydev, REG_PAGE_SEL, 0x0000);
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+	}
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 }
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 static irqreturn_t rk630_wol_irq_thread(int irq, void *dev_id)
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@@ -310,6 +407,7 @@
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 	.name			= "RK630 PHY",
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 	.features		= PHY_BASIC_FEATURES,
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 	.flags			= 0,
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+	.link_change_notify	= rk630_link_change_notify,
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 	.probe			= rk630_phy_probe,
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 	.remove			= rk630_phy_remove,
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 	.soft_reset		= genphy_soft_reset,
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@@ -326,7 +424,7 @@
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 	{ }
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 };
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-MODULE_DEVICE_TABLE(mdio, rockchip_phy_tbl);
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+MODULE_DEVICE_TABLE(mdio, rk630_phy_tbl);
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 module_phy_driver(rk630_phy_driver);
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