add ax88772_rst

hc

2024-05-10 9999e48639b3cecb08ffb37358bcba3b48161b29

 kernel/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c
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@@ -26,16 +26,17 @@
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 				  struct dma_desc *p)
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 {
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 	unsigned int rdes3 = le32_to_cpu(p->des3);
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-	int ret = good_frame;
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 	if (unlikely(rdes3 & XGMAC_RDES3_OWN))
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 		return dma_own;
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-	if (likely(!(rdes3 & XGMAC_RDES3_LD)))
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+	if (unlikely(rdes3 & XGMAC_RDES3_CTXT))
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 		return discard_frame;
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-	if (unlikely(rdes3 & XGMAC_RDES3_ES))
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-		ret = discard_frame;
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+	if (likely(!(rdes3 & XGMAC_RDES3_LD)))
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+		return rx_not_ls;
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+	if (unlikely((rdes3 & XGMAC_RDES3_ES) && (rdes3 & XGMAC_RDES3_LD)))
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+		return discard_frame;
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-	return ret;
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+	return good_frame;
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 }
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41
 
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 static int dwxgmac2_get_tx_len(struct dma_desc *p)
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@@ -55,7 +56,7 @@
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 static void dwxgmac2_set_rx_owner(struct dma_desc *p, int disable_rx_ic)
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 {
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-	p->des3 = cpu_to_le32(XGMAC_RDES3_OWN);
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+	p->des3 |= cpu_to_le32(XGMAC_RDES3_OWN);
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 	if (!disable_rx_ic)
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 		p->des3 |= cpu_to_le32(XGMAC_RDES3_IOC);
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@@ -98,11 +99,17 @@
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 	unsigned int rdes3 = le32_to_cpu(p->des3);
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 	bool desc_valid, ts_valid;
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+	dma_rmb();
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+
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 	desc_valid = !(rdes3 & XGMAC_RDES3_OWN) && (rdes3 & XGMAC_RDES3_CTXT);
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 	ts_valid = !(rdes3 & XGMAC_RDES3_TSD) && (rdes3 & XGMAC_RDES3_TSA);
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-	if (likely(desc_valid && ts_valid))
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+	if (likely(desc_valid && ts_valid)) {
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+		if ((p->des0 == 0xffffffff) && (p->des1 == 0xffffffff))
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+			return -EINVAL;
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 		return 0;
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+	}
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+
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 	return -EINVAL;
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 }
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@@ -113,13 +120,10 @@
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 	unsigned int rdes3 = le32_to_cpu(p->des3);
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 	int ret = -EBUSY;
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-	if (likely(rdes3 & XGMAC_RDES3_CDA)) {
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+	if (likely(rdes3 & XGMAC_RDES3_CDA))
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 		ret = dwxgmac2_rx_check_timestamp(next_desc);
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-		if (ret)
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-			return ret;
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-	}
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-	return ret;
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+	return !ret;
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 }
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 static void dwxgmac2_init_rx_desc(struct dma_desc *p, int disable_rx_ic,
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@@ -144,7 +148,7 @@
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 	p->des2 |= cpu_to_le32(len & XGMAC_TDES2_B1L);
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-	tdes3 = tot_pkt_len & XGMAC_TDES3_FL;
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+	tdes3 |= tot_pkt_len & XGMAC_TDES3_FL;
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 	if (is_fs)
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 		tdes3 |= XGMAC_TDES3_FD;
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 	else
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@@ -242,8 +246,8 @@
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 static void dwxgmac2_set_addr(struct dma_desc *p, dma_addr_t addr)
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 {
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-	p->des0 = cpu_to_le32(addr);
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-	p->des1 = 0;
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+	p->des0 = cpu_to_le32(lower_32_bits(addr));
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+	p->des1 = cpu_to_le32(upper_32_bits(addr));
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 }
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 static void dwxgmac2_clear(struct dma_desc *p)
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@@ -252,6 +256,94 @@
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 	p->des1 = 0;
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 	p->des2 = 0;
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 	p->des3 = 0;
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+}
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+
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+static int dwxgmac2_get_rx_hash(struct dma_desc *p, u32 *hash,
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+				enum pkt_hash_types *type)
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+{
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+	unsigned int rdes3 = le32_to_cpu(p->des3);
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+	u32 ptype;
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+
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+	if (rdes3 & XGMAC_RDES3_RSV) {
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+		ptype = (rdes3 & XGMAC_RDES3_L34T) >> XGMAC_RDES3_L34T_SHIFT;
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+
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+		switch (ptype) {
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+		case XGMAC_L34T_IP4TCP:
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+		case XGMAC_L34T_IP4UDP:
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+		case XGMAC_L34T_IP6TCP:
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+		case XGMAC_L34T_IP6UDP:
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+			*type = PKT_HASH_TYPE_L4;
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+			break;
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+		default:
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+			*type = PKT_HASH_TYPE_L3;
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+			break;
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+		}
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+
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+		*hash = le32_to_cpu(p->des1);
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+		return 0;
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+	}
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+
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+	return -EINVAL;
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+}
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+
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+static void dwxgmac2_get_rx_header_len(struct dma_desc *p, unsigned int *len)
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+{
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+	if (le32_to_cpu(p->des3) & XGMAC_RDES3_L34T)
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+		*len = le32_to_cpu(p->des2) & XGMAC_RDES2_HL;
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+}
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+
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+static void dwxgmac2_set_sec_addr(struct dma_desc *p, dma_addr_t addr, bool is_valid)
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+{
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+	p->des2 = cpu_to_le32(lower_32_bits(addr));
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+	p->des3 = cpu_to_le32(upper_32_bits(addr));
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+}
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+
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+static void dwxgmac2_set_sarc(struct dma_desc *p, u32 sarc_type)
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+{
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+	sarc_type <<= XGMAC_TDES3_SAIC_SHIFT;
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+
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+	p->des3 |= cpu_to_le32(sarc_type & XGMAC_TDES3_SAIC);
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+}
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+
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+static void dwxgmac2_set_vlan_tag(struct dma_desc *p, u16 tag, u16 inner_tag,
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+				  u32 inner_type)
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+{
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+	p->des0 = 0;
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+	p->des1 = 0;
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+	p->des2 = 0;
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+	p->des3 = 0;
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+
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+	/* Inner VLAN */
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+	if (inner_type) {
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+		u32 des = inner_tag << XGMAC_TDES2_IVT_SHIFT;
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+
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+		des &= XGMAC_TDES2_IVT;
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+		p->des2 = cpu_to_le32(des);
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+
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+		des = inner_type << XGMAC_TDES3_IVTIR_SHIFT;
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+		des &= XGMAC_TDES3_IVTIR;
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+		p->des3 = cpu_to_le32(des | XGMAC_TDES3_IVLTV);
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+	}
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+
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+	/* Outer VLAN */
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+	p->des3 |= cpu_to_le32(tag & XGMAC_TDES3_VT);
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+	p->des3 |= cpu_to_le32(XGMAC_TDES3_VLTV);
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+
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+	p->des3 |= cpu_to_le32(XGMAC_TDES3_CTXT);
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+}
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+
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+static void dwxgmac2_set_vlan(struct dma_desc *p, u32 type)
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+{
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+	type <<= XGMAC_TDES2_VTIR_SHIFT;
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+	p->des2 |= cpu_to_le32(type & XGMAC_TDES2_VTIR);
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+}
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+
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+static void dwxgmac2_set_tbs(struct dma_edesc *p, u32 sec, u32 nsec)
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+{
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+	p->des4 = cpu_to_le32((sec & XGMAC_TDES0_LT) | XGMAC_TDES0_LTV);
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+	p->des5 = cpu_to_le32(nsec & XGMAC_TDES1_LT);
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+	p->des6 = 0;
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+	p->des7 = 0;
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 }
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 const struct stmmac_desc_ops dwxgmac210_desc_ops = {
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@@ -277,4 +369,11 @@
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 	.get_addr = dwxgmac2_get_addr,
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 	.set_addr = dwxgmac2_set_addr,
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 	.clear = dwxgmac2_clear,
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+	.get_rx_hash = dwxgmac2_get_rx_hash,
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+	.get_rx_header_len = dwxgmac2_get_rx_header_len,
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+	.set_sec_addr = dwxgmac2_set_sec_addr,
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+	.set_sarc = dwxgmac2_set_sarc,
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+	.set_vlan_tag = dwxgmac2_set_vlan_tag,
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+	.set_vlan = dwxgmac2_set_vlan,
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+	.set_tbs = dwxgmac2_set_tbs,
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 };