add ax88772_rst

hc

2024-05-10 9999e48639b3cecb08ffb37358bcba3b48161b29

 kernel/drivers/net/ethernet/stmicro/stmmac/dwmac5.c
..
..
@@ -520,9 +520,9 @@
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 		return 0;
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 	}
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-	val |= PPSCMDx(index, 0x2);
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 	val |= TRGTMODSELx(index, 0x2);
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 	val |= PPSEN0;
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+	writel(val, ioaddr + MAC_PPS_CONTROL);
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 	writel(cfg->start.tv_sec, ioaddr + MAC_PPSx_TARGET_TIME_SEC(index));
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..
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@@ -547,6 +547,82 @@
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 	writel(period - 1, ioaddr + MAC_PPSx_WIDTH(index));
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 	/* Finally, activate it */
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+	val |= PPSCMDx(index, 0x2);
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 	writel(val, ioaddr + MAC_PPS_CONTROL);
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 	return 0;
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 }
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+
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+static int dwmac5_est_write(void __iomem *ioaddr, u32 reg, u32 val, bool gcl)
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+{
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+	u32 ctrl;
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+
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+	writel(val, ioaddr + MTL_EST_GCL_DATA);
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+
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+	ctrl = (reg << ADDR_SHIFT);
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+	ctrl |= gcl ? 0 : GCRR;
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+
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+	writel(ctrl, ioaddr + MTL_EST_GCL_CONTROL);
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+
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+	ctrl |= SRWO;
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+	writel(ctrl, ioaddr + MTL_EST_GCL_CONTROL);
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+
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+	return readl_poll_timeout(ioaddr + MTL_EST_GCL_CONTROL,
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+				  ctrl, !(ctrl & SRWO), 100, 5000);
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+}
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+
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+int dwmac5_est_configure(void __iomem *ioaddr, struct stmmac_est *cfg,
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+			 unsigned int ptp_rate)
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+{
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+	int i, ret = 0x0;
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+	u32 ctrl;
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+
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+	ret |= dwmac5_est_write(ioaddr, BTR_LOW, cfg->btr[0], false);
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+	ret |= dwmac5_est_write(ioaddr, BTR_HIGH, cfg->btr[1], false);
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+	ret |= dwmac5_est_write(ioaddr, TER, cfg->ter, false);
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+	ret |= dwmac5_est_write(ioaddr, LLR, cfg->gcl_size, false);
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+	ret |= dwmac5_est_write(ioaddr, CTR_LOW, cfg->ctr[0], false);
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+	ret |= dwmac5_est_write(ioaddr, CTR_HIGH, cfg->ctr[1], false);
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+	if (ret)
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+		return ret;
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+
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+	for (i = 0; i < cfg->gcl_size; i++) {
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+		ret = dwmac5_est_write(ioaddr, i, cfg->gcl[i], true);
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+		if (ret)
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+			return ret;
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+	}
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+
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+	ctrl = readl(ioaddr + MTL_EST_CONTROL);
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+	ctrl &= ~PTOV;
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+	ctrl |= ((1000000000 / ptp_rate) * 6) << PTOV_SHIFT;
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+	if (cfg->enable)
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+		ctrl |= EEST | SSWL;
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+	else
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+		ctrl &= ~EEST;
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+
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+	writel(ctrl, ioaddr + MTL_EST_CONTROL);
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+	return 0;
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+}
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+
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+void dwmac5_fpe_configure(void __iomem *ioaddr, u32 num_txq, u32 num_rxq,
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+			  bool enable)
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+{
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+	u32 value;
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+
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+	if (!enable) {
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+		value = readl(ioaddr + MAC_FPE_CTRL_STS);
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+
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+		value &= ~EFPE;
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+
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+		writel(value, ioaddr + MAC_FPE_CTRL_STS);
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+		return;
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+	}
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+
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+	value = readl(ioaddr + GMAC_RXQ_CTRL1);
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+	value &= ~GMAC_RXQCTRL_FPRQ;
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+	value |= (num_rxq - 1) << GMAC_RXQCTRL_FPRQ_SHIFT;
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+	writel(value, ioaddr + GMAC_RXQ_CTRL1);
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+
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+	value = readl(ioaddr + MAC_FPE_CTRL_STS);
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+	value |= EFPE;
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+	writel(value, ioaddr + MAC_FPE_CTRL_STS);
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+}