add ax88772_rst

hc

2024-05-10 9999e48639b3cecb08ffb37358bcba3b48161b29

 kernel/drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c
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@@ -1,14 +1,12 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * Copyright (C) 2007-2015  STMicroelectronics Ltd
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- *
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- * This program is free software; you can redistribute it and/or modify it
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- * under the terms and conditions of the GNU General Public License,
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- * version 2, as published by the Free Software Foundation.
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  *
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  * Author: Alexandre Torgue <alexandre.torgue@st.com>
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  */
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 #include <linux/io.h>
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+#include <linux/iopoll.h>
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 #include <linux/delay.h>
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 #include "common.h"
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 #include "dwmac4_dma.h"
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@@ -17,22 +15,14 @@
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 int dwmac4_dma_reset(void __iomem *ioaddr)
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 {
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 	u32 value = readl(ioaddr + DMA_BUS_MODE);
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-	int limit;
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 	/* DMA SW reset */
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 	value |= DMA_BUS_MODE_SFT_RESET;
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 	writel(value, ioaddr + DMA_BUS_MODE);
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-	limit = 10;
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-	while (limit--) {
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-		if (!(readl(ioaddr + DMA_BUS_MODE) & DMA_BUS_MODE_SFT_RESET))
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-			break;
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-		mdelay(10);
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-	}
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-	if (limit < 0)
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-		return -EBUSY;
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-
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-	return 0;
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+	return readl_poll_timeout(ioaddr + DMA_BUS_MODE, value,
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+				 !(value & DMA_BUS_MODE_SFT_RESET),
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+				 500, 1000000);
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 }
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 void dwmac4_set_rx_tail_ptr(void __iomem *ioaddr, u32 tail_ptr, u32 chan)
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@@ -84,10 +74,6 @@
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 	value &= ~DMA_CONTROL_SR;
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 	writel(value, ioaddr + DMA_CHAN_RX_CONTROL(chan));
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-
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-	value = readl(ioaddr + GMAC_CONFIG);
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-	value &= ~GMAC_CONFIG_RE;
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-	writel(value, ioaddr + GMAC_CONFIG);
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 }
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 void dwmac4_set_tx_ring_len(void __iomem *ioaddr, u32 len, u32 chan)
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@@ -100,29 +86,60 @@
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 	writel(len, ioaddr + DMA_CHAN_RX_RING_LEN(chan));
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 }
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-void dwmac4_enable_dma_irq(void __iomem *ioaddr, u32 chan)
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+void dwmac4_enable_dma_irq(void __iomem *ioaddr, u32 chan, bool rx, bool tx)
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 {
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-	writel(DMA_CHAN_INTR_DEFAULT_MASK, ioaddr +
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-	       DMA_CHAN_INTR_ENA(chan));
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+	u32 value = readl(ioaddr + DMA_CHAN_INTR_ENA(chan));
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+
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+	if (rx)
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+		value |= DMA_CHAN_INTR_DEFAULT_RX;
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+	if (tx)
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+		value |= DMA_CHAN_INTR_DEFAULT_TX;
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+
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+	writel(value, ioaddr + DMA_CHAN_INTR_ENA(chan));
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 }
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-void dwmac410_enable_dma_irq(void __iomem *ioaddr, u32 chan)
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+void dwmac410_enable_dma_irq(void __iomem *ioaddr, u32 chan, bool rx, bool tx)
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 {
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-	writel(DMA_CHAN_INTR_DEFAULT_MASK_4_10,
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-	       ioaddr + DMA_CHAN_INTR_ENA(chan));
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+	u32 value = readl(ioaddr + DMA_CHAN_INTR_ENA(chan));
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+
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+	if (rx)
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+		value |= DMA_CHAN_INTR_DEFAULT_RX_4_10;
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+	if (tx)
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+		value |= DMA_CHAN_INTR_DEFAULT_TX_4_10;
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+
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+	writel(value, ioaddr + DMA_CHAN_INTR_ENA(chan));
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 }
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-void dwmac4_disable_dma_irq(void __iomem *ioaddr, u32 chan)
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+void dwmac4_disable_dma_irq(void __iomem *ioaddr, u32 chan, bool rx, bool tx)
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 {
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-	writel(0, ioaddr + DMA_CHAN_INTR_ENA(chan));
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+	u32 value = readl(ioaddr + DMA_CHAN_INTR_ENA(chan));
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+
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+	if (rx)
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+		value &= ~DMA_CHAN_INTR_DEFAULT_RX;
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+	if (tx)
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+		value &= ~DMA_CHAN_INTR_DEFAULT_TX;
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+
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+	writel(value, ioaddr + DMA_CHAN_INTR_ENA(chan));
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+}
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+
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+void dwmac410_disable_dma_irq(void __iomem *ioaddr, u32 chan, bool rx, bool tx)
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+{
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+	u32 value = readl(ioaddr + DMA_CHAN_INTR_ENA(chan));
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+
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+	if (rx)
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+		value &= ~DMA_CHAN_INTR_DEFAULT_RX_4_10;
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+	if (tx)
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+		value &= ~DMA_CHAN_INTR_DEFAULT_TX_4_10;
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+
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+	writel(value, ioaddr + DMA_CHAN_INTR_ENA(chan));
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 }
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 int dwmac4_dma_interrupt(void __iomem *ioaddr,
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 			 struct stmmac_extra_stats *x, u32 chan)
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 {
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-	int ret = 0;
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-
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 	u32 intr_status = readl(ioaddr + DMA_CHAN_STATUS(chan));
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+	u32 intr_en = readl(ioaddr + DMA_CHAN_INTR_ENA(chan));
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+	int ret = 0;
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 	/* ABNORMAL interrupts */
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 	if (unlikely(intr_status & DMA_CHAN_STATUS_AIS)) {
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@@ -147,16 +164,11 @@
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 	if (likely(intr_status & DMA_CHAN_STATUS_NIS)) {
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 		x->normal_irq_n++;
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 		if (likely(intr_status & DMA_CHAN_STATUS_RI)) {
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-			u32 value;
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-
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-			value = readl(ioaddr + DMA_CHAN_INTR_ENA(chan));
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-			/* to schedule NAPI on real RIE event. */
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-			if (likely(value & DMA_CHAN_INTR_ENA_RIE)) {
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-				x->rx_normal_irq_n++;
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-				ret |= handle_rx;
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-			}
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+			x->rx_normal_irq_n++;
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+			ret |= handle_rx;
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 		}
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-		if (likely(intr_status & DMA_CHAN_STATUS_TI)) {
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+		if (likely(intr_status & (DMA_CHAN_STATUS_TI |
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+					  DMA_CHAN_STATUS_TBU))) {
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 			x->tx_normal_irq_n++;
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 			ret |= handle_tx;
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 		}
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@@ -164,12 +176,7 @@
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 			x->rx_early_irq++;
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 	}
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-	/* Clear the interrupt by writing a logic 1 to the chanX interrupt
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-	 * status [21-0] expect reserved bits [5-3]
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-	 */
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-	writel((intr_status & 0x3fffc7),
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-	       ioaddr + DMA_CHAN_STATUS(chan));
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-
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+	writel(intr_status & intr_en, ioaddr + DMA_CHAN_STATUS(chan));
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 	return ret;
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 }
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