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2024-05-10 9999e48639b3cecb08ffb37358bcba3b48161b29 
 kernel/drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c
....@@ -1,14 +1,12 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  * Copyright (C) 2007-2015  STMicroelectronics Ltd
3
- *
4
- * This program is free software; you can redistribute it and/or modify it
5
- * under the terms and conditions of the GNU General Public License,
6
- * version 2, as published by the Free Software Foundation.
74  *
85  * Author: Alexandre Torgue <alexandre.torgue@st.com>
96  */
107 
118 #include <linux/io.h>
9
+#include <linux/iopoll.h>
1210 #include <linux/delay.h>
1311 #include "common.h"
1412 #include "dwmac4_dma.h"
....@@ -17,22 +15,14 @@
1715 int dwmac4_dma_reset(void __iomem *ioaddr)
1816 {
1917 	u32 value = readl(ioaddr + DMA_BUS_MODE);
20
-	int limit;
2118 
2219 	/* DMA SW reset */
2320 	value |= DMA_BUS_MODE_SFT_RESET;
2421 	writel(value, ioaddr + DMA_BUS_MODE);
25
-	limit = 10;
26
-	while (limit--) {
27
-		if (!(readl(ioaddr + DMA_BUS_MODE) & DMA_BUS_MODE_SFT_RESET))
28
-			break;
29
-		mdelay(10);
30
-	}
3122 
32
-	if (limit < 0)
33
-		return -EBUSY;
34
-
35
-	return 0;
23
+	return readl_poll_timeout(ioaddr + DMA_BUS_MODE, value,
24
+				 !(value & DMA_BUS_MODE_SFT_RESET),
25
+				 500, 1000000);
3626 }
3727 
3828 void dwmac4_set_rx_tail_ptr(void __iomem *ioaddr, u32 tail_ptr, u32 chan)
....@@ -63,10 +53,6 @@
6353 
6454 	value &= ~DMA_CONTROL_ST;
6555 	writel(value, ioaddr + DMA_CHAN_TX_CONTROL(chan));
66
-
67
-	value = readl(ioaddr + GMAC_CONFIG);
68
-	value &= ~GMAC_CONFIG_TE;
69
-	writel(value, ioaddr + GMAC_CONFIG);
7056 }
7157 
7258 void dwmac4_dma_start_rx(void __iomem *ioaddr, u32 chan)
....@@ -88,10 +74,6 @@
8874 
8975 	value &= ~DMA_CONTROL_SR;
9076 	writel(value, ioaddr + DMA_CHAN_RX_CONTROL(chan));
91
-
92
-	value = readl(ioaddr + GMAC_CONFIG);
93
-	value &= ~GMAC_CONFIG_RE;
94
-	writel(value, ioaddr + GMAC_CONFIG);
9577 }
9678 
9779 void dwmac4_set_tx_ring_len(void __iomem *ioaddr, u32 len, u32 chan)
....@@ -104,29 +86,60 @@
10486 	writel(len, ioaddr + DMA_CHAN_RX_RING_LEN(chan));
10587 }
10688 
107
-void dwmac4_enable_dma_irq(void __iomem *ioaddr, u32 chan)
89
+void dwmac4_enable_dma_irq(void __iomem *ioaddr, u32 chan, bool rx, bool tx)
10890 {
109
-	writel(DMA_CHAN_INTR_DEFAULT_MASK, ioaddr +
110
-	       DMA_CHAN_INTR_ENA(chan));
91
+	u32 value = readl(ioaddr + DMA_CHAN_INTR_ENA(chan));
92
+
93
+	if (rx)
94
+		value |= DMA_CHAN_INTR_DEFAULT_RX;
95
+	if (tx)
96
+		value |= DMA_CHAN_INTR_DEFAULT_TX;
97
+
98
+	writel(value, ioaddr + DMA_CHAN_INTR_ENA(chan));
11199 }
112100 
113
-void dwmac410_enable_dma_irq(void __iomem *ioaddr, u32 chan)
101
+void dwmac410_enable_dma_irq(void __iomem *ioaddr, u32 chan, bool rx, bool tx)
114102 {
115
-	writel(DMA_CHAN_INTR_DEFAULT_MASK_4_10,
116
-	       ioaddr + DMA_CHAN_INTR_ENA(chan));
103
+	u32 value = readl(ioaddr + DMA_CHAN_INTR_ENA(chan));
104
+
105
+	if (rx)
106
+		value |= DMA_CHAN_INTR_DEFAULT_RX_4_10;
107
+	if (tx)
108
+		value |= DMA_CHAN_INTR_DEFAULT_TX_4_10;
109
+
110
+	writel(value, ioaddr + DMA_CHAN_INTR_ENA(chan));
117111 }
118112 
119
-void dwmac4_disable_dma_irq(void __iomem *ioaddr, u32 chan)
113
+void dwmac4_disable_dma_irq(void __iomem *ioaddr, u32 chan, bool rx, bool tx)
120114 {
121
-	writel(0, ioaddr + DMA_CHAN_INTR_ENA(chan));
115
+	u32 value = readl(ioaddr + DMA_CHAN_INTR_ENA(chan));
116
+
117
+	if (rx)
118
+		value &= ~DMA_CHAN_INTR_DEFAULT_RX;
119
+	if (tx)
120
+		value &= ~DMA_CHAN_INTR_DEFAULT_TX;
121
+
122
+	writel(value, ioaddr + DMA_CHAN_INTR_ENA(chan));
123
+}
124
+
125
+void dwmac410_disable_dma_irq(void __iomem *ioaddr, u32 chan, bool rx, bool tx)
126
+{
127
+	u32 value = readl(ioaddr + DMA_CHAN_INTR_ENA(chan));
128
+
129
+	if (rx)
130
+		value &= ~DMA_CHAN_INTR_DEFAULT_RX_4_10;
131
+	if (tx)
132
+		value &= ~DMA_CHAN_INTR_DEFAULT_TX_4_10;
133
+
134
+	writel(value, ioaddr + DMA_CHAN_INTR_ENA(chan));
122135 }
123136 
124137 int dwmac4_dma_interrupt(void __iomem *ioaddr,
125138 			 struct stmmac_extra_stats *x, u32 chan)
126139 {
127
-	int ret = 0;
128
-
129140 	u32 intr_status = readl(ioaddr + DMA_CHAN_STATUS(chan));
141
+	u32 intr_en = readl(ioaddr + DMA_CHAN_INTR_ENA(chan));
142
+	int ret = 0;
130143 
131144 	/* ABNORMAL interrupts */
132145 	if (unlikely(intr_status & DMA_CHAN_STATUS_AIS)) {
....@@ -151,16 +164,11 @@
151164 	if (likely(intr_status & DMA_CHAN_STATUS_NIS)) {
152165 		x->normal_irq_n++;
153166 		if (likely(intr_status & DMA_CHAN_STATUS_RI)) {
154
-			u32 value;
155
-
156
-			value = readl(ioaddr + DMA_CHAN_INTR_ENA(chan));
157
-			/* to schedule NAPI on real RIE event. */
158
-			if (likely(value & DMA_CHAN_INTR_ENA_RIE)) {
159
-				x->rx_normal_irq_n++;
160
-				ret |= handle_rx;
161
-			}
167
+			x->rx_normal_irq_n++;
168
+			ret |= handle_rx;
162169 		}
163
-		if (likely(intr_status & DMA_CHAN_STATUS_TI)) {
170
+		if (likely(intr_status & (DMA_CHAN_STATUS_TI |
171
+					  DMA_CHAN_STATUS_TBU))) {
164172 			x->tx_normal_irq_n++;
165173 			ret |= handle_tx;
166174 		}
....@@ -168,12 +176,7 @@
168176 			x->rx_early_irq++;
169177 	}
170178 
171
-	/* Clear the interrupt by writing a logic 1 to the chanX interrupt
172
-	 * status [21-0] expect reserved bits [5-3]
173
-	 */
174
-	writel((intr_status & 0x3fffc7),
175
-	       ioaddr + DMA_CHAN_STATUS(chan));
176
-
179
+	writel(intr_status & intr_en, ioaddr + DMA_CHAN_STATUS(chan));
177180 	return ret;
178181 }
179182