add ax88772_rst

hc

2024-05-10 9999e48639b3cecb08ffb37358bcba3b48161b29

 kernel/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
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@@ -1,3 +1,4 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
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  * DWC Ether MAC version 4.xx  has been used for  developing this code.
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@@ -5,10 +6,6 @@
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  * This contains the functions to handle the dma.
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  *
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  * Copyright (C) 2015  STMicroelectronics Ltd
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- *
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- * This program is free software; you can redistribute it and/or modify it
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- * under the terms and conditions of the GNU General Public License,
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- * version 2, as published by the Free Software Foundation.
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  *
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  * Author: Alexandre Torgue <alexandre.torgue@st.com>
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  */
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@@ -73,7 +70,7 @@
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70
 
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 static void dwmac4_dma_init_rx_chan(void __iomem *ioaddr,
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 				    struct stmmac_dma_cfg *dma_cfg,
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-				    u32 dma_rx_phy, u32 chan)
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+				    dma_addr_t dma_rx_phy, u32 chan)
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 {
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 	u32 value;
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 	u32 rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl;
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@@ -82,12 +79,16 @@
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 	value = value | (rxpbl << DMA_BUS_MODE_RPBL_SHIFT);
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 	writel(value, ioaddr + DMA_CHAN_RX_CONTROL(chan));
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-	writel(dma_rx_phy, ioaddr + DMA_CHAN_RX_BASE_ADDR(chan));
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+	if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) && likely(dma_cfg->eame))
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+		writel(upper_32_bits(dma_rx_phy),
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+		       ioaddr + DMA_CHAN_RX_BASE_ADDR_HI(chan));
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+
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+	writel(lower_32_bits(dma_rx_phy), ioaddr + DMA_CHAN_RX_BASE_ADDR(chan));
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 }
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 static void dwmac4_dma_init_tx_chan(void __iomem *ioaddr,
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 				    struct stmmac_dma_cfg *dma_cfg,
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-				    u32 dma_tx_phy, u32 chan)
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+				    dma_addr_t dma_tx_phy, u32 chan)
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 {
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 	u32 value;
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 	u32 txpbl = dma_cfg->txpbl ?: dma_cfg->pbl;
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@@ -100,7 +101,11 @@
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 	writel(value, ioaddr + DMA_CHAN_TX_CONTROL(chan));
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-	writel(dma_tx_phy, ioaddr + DMA_CHAN_TX_BASE_ADDR(chan));
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+	if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) && likely(dma_cfg->eame))
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+		writel(upper_32_bits(dma_tx_phy),
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+		       ioaddr + DMA_CHAN_TX_BASE_ADDR_HI(chan));
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+
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+	writel(lower_32_bits(dma_tx_phy), ioaddr + DMA_CHAN_TX_BASE_ADDR(chan));
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 }
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 static void dwmac4_dma_init_channel(void __iomem *ioaddr,
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@@ -119,6 +124,23 @@
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 	       ioaddr + DMA_CHAN_INTR_ENA(chan));
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 }
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+static void dwmac410_dma_init_channel(void __iomem *ioaddr,
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+				      struct stmmac_dma_cfg *dma_cfg, u32 chan)
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+{
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+	u32 value;
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+
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+	/* common channel control register config */
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+	value = readl(ioaddr + DMA_CHAN_CONTROL(chan));
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+	if (dma_cfg->pblx8)
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+		value = value | DMA_BUS_MODE_PBL;
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+
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+	writel(value, ioaddr + DMA_CHAN_CONTROL(chan));
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+
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+	/* Mask interrupts by writing to CSR7 */
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+	writel(DMA_CHAN_INTR_DEFAULT_MASK_4_10,
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+	       ioaddr + DMA_CHAN_INTR_ENA(chan));
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+}
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+
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 static void dwmac4_dma_init(void __iomem *ioaddr,
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 			    struct stmmac_dma_cfg *dma_cfg, int atds)
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 {
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@@ -134,6 +156,9 @@
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 	if (dma_cfg->aal)
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 		value |= DMA_SYS_BUS_AAL;
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+
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+	if (dma_cfg->eame)
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+		value |= DMA_SYS_BUS_EAME;
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 	writel(value, ioaddr + DMA_SYS_BUS_MODE);
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 }
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@@ -197,7 +222,7 @@
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 				       u32 channel, int fifosz, u8 qmode)
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 {
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 	unsigned int rqs = fifosz / 256 - 1;
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-	u32 mtl_rx_op, mtl_rx_int;
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+	u32 mtl_rx_op;
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 	mtl_rx_op = readl(ioaddr + MTL_CHAN_RX_OP_MODE(channel));
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@@ -244,19 +269,9 @@
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 			rfa = 0x01; /* Full-1.5K */
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 			break;
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-		case 8192:
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-			rfd = 0x06; /* Full-4K */
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-			rfa = 0x0a; /* Full-6K */
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-			break;
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-
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-		case 16384:
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-			rfd = 0x06; /* Full-4K */
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-			rfa = 0x12; /* Full-10K */
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-			break;
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-
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 		default:
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-			rfd = 0x06; /* Full-4K */
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-			rfa = 0x1e; /* Full-16K */
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+			rfd = 0x07; /* Full-4.5K */
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+			rfa = 0x04; /* Full-3K */
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 			break;
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 		}
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@@ -268,11 +283,6 @@
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 	}
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 	writel(mtl_rx_op, ioaddr + MTL_CHAN_RX_OP_MODE(channel));
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-
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-	/* Enable MTL RX overflow */
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-	mtl_rx_int = readl(ioaddr + MTL_CHAN_INT_CTRL(channel));
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-	writel(mtl_rx_int | MTL_RX_OVERFLOW_INT_EN,
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-	       ioaddr + MTL_CHAN_INT_CTRL(channel));
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 }
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 static void dwmac4_dma_tx_chan_op_mode(void __iomem *ioaddr, int mode,
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@@ -327,8 +337,8 @@
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 	writel(mtl_tx_op, ioaddr +  MTL_CHAN_TX_OP_MODE(channel));
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 }
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-static void dwmac4_get_hw_feature(void __iomem *ioaddr,
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-				  struct dma_features *dma_cap)
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+static int dwmac4_get_hw_feature(void __iomem *ioaddr,
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+				 struct dma_features *dma_cap)
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 {
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 	u32 hw_cap = readl(ioaddr + GMAC_HW_FEATURE0);
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@@ -336,7 +346,7 @@
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 	dma_cap->mbps_10_100 = (hw_cap & GMAC_HW_FEAT_MIISEL);
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 	dma_cap->mbps_1000 = (hw_cap & GMAC_HW_FEAT_GMIISEL) >> 1;
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 	dma_cap->half_duplex = (hw_cap & GMAC_HW_FEAT_HDSEL) >> 2;
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-	dma_cap->hash_filter = (hw_cap & GMAC_HW_FEAT_VLHASH) >> 4;
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+	dma_cap->vlhash = (hw_cap & GMAC_HW_FEAT_VLHASH) >> 4;
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 	dma_cap->multi_addr = (hw_cap & GMAC_HW_FEAT_ADDMAC) >> 18;
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 	dma_cap->pcs = (hw_cap & GMAC_HW_FEAT_PCSSEL) >> 3;
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 	dma_cap->sma_mdio = (hw_cap & GMAC_HW_FEAT_SMASEL) >> 5;
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@@ -351,11 +361,33 @@
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 	/* TX and RX csum */
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 	dma_cap->tx_coe = (hw_cap & GMAC_HW_FEAT_TXCOSEL) >> 14;
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 	dma_cap->rx_coe =  (hw_cap & GMAC_HW_FEAT_RXCOESEL) >> 16;
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+	dma_cap->vlins = (hw_cap & GMAC_HW_FEAT_SAVLANINS) >> 27;
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+	dma_cap->arpoffsel = (hw_cap & GMAC_HW_FEAT_ARPOFFSEL) >> 9;
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 	/* MAC HW feature1 */
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 	hw_cap = readl(ioaddr + GMAC_HW_FEATURE1);
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+	dma_cap->l3l4fnum = (hw_cap & GMAC_HW_FEAT_L3L4FNUM) >> 27;
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+	dma_cap->hash_tb_sz = (hw_cap & GMAC_HW_HASH_TB_SZ) >> 24;
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 	dma_cap->av = (hw_cap & GMAC_HW_FEAT_AVSEL) >> 20;
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 	dma_cap->tsoen = (hw_cap & GMAC_HW_TSOEN) >> 18;
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+	dma_cap->sphen = (hw_cap & GMAC_HW_FEAT_SPHEN) >> 17;
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+
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+	dma_cap->addr64 = (hw_cap & GMAC_HW_ADDR64) >> 14;
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+	switch (dma_cap->addr64) {
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+	case 0:
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+		dma_cap->addr64 = 32;
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+		break;
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+	case 1:
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+		dma_cap->addr64 = 40;
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+		break;
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+	case 2:
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+		dma_cap->addr64 = 48;
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+		break;
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+	default:
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+		dma_cap->addr64 = 32;
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+		break;
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+	}
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+
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 	/* RX and TX FIFO sizes are encoded as log2(n / 128). Undo that by
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 	 * shifting and store the sizes in bytes.
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 	 */
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@@ -384,9 +416,17 @@
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 	/* 5.10 Features */
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 	dma_cap->asp = (hw_cap & GMAC_HW_FEAT_ASP) >> 28;
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+	dma_cap->tbssel = (hw_cap & GMAC_HW_FEAT_TBSSEL) >> 27;
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+	dma_cap->fpesel = (hw_cap & GMAC_HW_FEAT_FPESEL) >> 26;
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+	dma_cap->estwid = (hw_cap & GMAC_HW_FEAT_ESTWID) >> 20;
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+	dma_cap->estdep = (hw_cap & GMAC_HW_FEAT_ESTDEP) >> 17;
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+	dma_cap->estsel = (hw_cap & GMAC_HW_FEAT_ESTSEL) >> 16;
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 	dma_cap->frpes = (hw_cap & GMAC_HW_FEAT_FRPES) >> 13;
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 	dma_cap->frpbs = (hw_cap & GMAC_HW_FEAT_FRPBS) >> 11;
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 	dma_cap->frpsel = (hw_cap & GMAC_HW_FEAT_FRPSEL) >> 10;
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+	dma_cap->dvlan = (hw_cap & GMAC_HW_FEAT_DVLAN) >> 5;
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+
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+	return 0;
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 }
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 /* Enable/disable TSO feature and set MSS */
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@@ -430,6 +470,41 @@
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 	writel(value, ioaddr + DMA_CHAN_RX_CONTROL(chan));
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 }
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+static void dwmac4_enable_sph(void __iomem *ioaddr, bool en, u32 chan)
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+{
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+	u32 value = readl(ioaddr + GMAC_EXT_CONFIG);
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+
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+	value &= ~GMAC_CONFIG_HDSMS;
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+	value |= GMAC_CONFIG_HDSMS_256; /* Segment max 256 bytes */
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+	writel(value, ioaddr + GMAC_EXT_CONFIG);
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+
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+	value = readl(ioaddr + DMA_CHAN_CONTROL(chan));
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+	if (en)
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+		value |= DMA_CONTROL_SPH;
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+	else
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+		value &= ~DMA_CONTROL_SPH;
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+	writel(value, ioaddr + DMA_CHAN_CONTROL(chan));
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+}
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+
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+static int dwmac4_enable_tbs(void __iomem *ioaddr, bool en, u32 chan)
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+{
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+	u32 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan));
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+
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+	if (en)
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+		value |= DMA_CONTROL_EDSE;
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+	else
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+		value &= ~DMA_CONTROL_EDSE;
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+
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+	writel(value, ioaddr + DMA_CHAN_TX_CONTROL(chan));
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+
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+	value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)) & DMA_CONTROL_EDSE;
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+	if (en && !value)
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+		return -EIO;
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+
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+	writel(DMA_TBS_DEF_FTOS, ioaddr + DMA_TBS_CTRL);
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+	return 0;
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+}
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+
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 const struct stmmac_dma_ops dwmac4_dma_ops = {
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 	.reset = dwmac4_dma_reset,
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 	.init = dwmac4_dma_init,
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@@ -456,12 +531,13 @@
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 	.enable_tso = dwmac4_enable_tso,
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 	.qmode = dwmac4_qmode,
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 	.set_bfsize = dwmac4_set_bfsize,
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+	.enable_sph = dwmac4_enable_sph,
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 };
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 const struct stmmac_dma_ops dwmac410_dma_ops = {
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 	.reset = dwmac4_dma_reset,
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 	.init = dwmac4_dma_init,
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-	.init_chan = dwmac4_dma_init_channel,
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+	.init_chan = dwmac410_dma_init_channel,
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541
 	.init_rx_chan = dwmac4_dma_init_rx_chan,
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 	.init_tx_chan = dwmac4_dma_init_tx_chan,
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 	.axi = dwmac4_dma_axi,
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@@ -484,4 +560,6 @@
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 	.enable_tso = dwmac4_enable_tso,
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 	.qmode = dwmac4_qmode,
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 	.set_bfsize = dwmac4_set_bfsize,
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+	.enable_sph = dwmac4_enable_sph,
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+	.enable_tbs = dwmac4_enable_tbs,
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 };