.. | .. |
---|
| 1 | +// SPDX-License-Identifier: GPL-2.0-only |
---|
1 | 2 | /******************************************************************************* |
---|
2 | 3 | This is the driver for the MAC 10/100 on-chip Ethernet controller |
---|
3 | 4 | currently tested on all the ST boards based on STb7109 and stx7200 SoCs. |
---|
.. | .. |
---|
9 | 10 | |
---|
10 | 11 | Copyright (C) 2007-2009 STMicroelectronics Ltd |
---|
11 | 12 | |
---|
12 | | - This program is free software; you can redistribute it and/or modify it |
---|
13 | | - under the terms and conditions of the GNU General Public License, |
---|
14 | | - version 2, as published by the Free Software Foundation. |
---|
15 | | - |
---|
16 | | - This program is distributed in the hope it will be useful, but WITHOUT |
---|
17 | | - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
---|
18 | | - FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
---|
19 | | - more details. |
---|
20 | | - |
---|
21 | | - The full GNU General Public License is included in this distribution in |
---|
22 | | - the file called "COPYING". |
---|
23 | 13 | |
---|
24 | 14 | Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> |
---|
25 | 15 | *******************************************************************************/ |
---|
.. | .. |
---|
41 | 31 | |
---|
42 | 32 | static void dwmac100_dma_init_rx(void __iomem *ioaddr, |
---|
43 | 33 | struct stmmac_dma_cfg *dma_cfg, |
---|
44 | | - u32 dma_rx_phy, u32 chan) |
---|
| 34 | + dma_addr_t dma_rx_phy, u32 chan) |
---|
45 | 35 | { |
---|
46 | 36 | /* RX descriptor base addr lists must be written into DMA CSR3 */ |
---|
47 | | - writel(dma_rx_phy, ioaddr + DMA_RCV_BASE_ADDR); |
---|
| 37 | + writel(lower_32_bits(dma_rx_phy), ioaddr + DMA_RCV_BASE_ADDR); |
---|
48 | 38 | } |
---|
49 | 39 | |
---|
50 | 40 | static void dwmac100_dma_init_tx(void __iomem *ioaddr, |
---|
51 | 41 | struct stmmac_dma_cfg *dma_cfg, |
---|
52 | | - u32 dma_tx_phy, u32 chan) |
---|
| 42 | + dma_addr_t dma_tx_phy, u32 chan) |
---|
53 | 43 | { |
---|
54 | 44 | /* TX descriptor base addr lists must be written into DMA CSR4 */ |
---|
55 | | - writel(dma_tx_phy, ioaddr + DMA_TX_BASE_ADDR); |
---|
| 45 | + writel(lower_32_bits(dma_tx_phy), ioaddr + DMA_TX_BASE_ADDR); |
---|
56 | 46 | } |
---|
57 | 47 | |
---|
58 | 48 | /* Store and Forward capability is not used at all. |
---|