add ax88772_rst

hc

2024-05-10 9999e48639b3cecb08ffb37358bcba3b48161b29

 kernel/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
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@@ -1,3 +1,4 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*******************************************************************************
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   This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
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   DWC Ether MAC 10/100/1000 Universal version 3.41a  has been used for
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@@ -7,17 +8,6 @@
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8
 
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   Copyright (C) 2007-2009  STMicroelectronics Ltd
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-  This program is free software; you can redistribute it and/or modify it
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-  under the terms and conditions of the GNU General Public License,
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-  version 2, as published by the Free Software Foundation.
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-
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-  This program is distributed in the hope it will be useful, but WITHOUT
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-  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
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-  more details.
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-
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-  The full GNU General Public License is included in this distribution in
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-  the file called "COPYING".
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   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
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 *******************************************************************************/
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@@ -122,18 +112,18 @@
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 static void dwmac1000_dma_init_rx(void __iomem *ioaddr,
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 				  struct stmmac_dma_cfg *dma_cfg,
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-				  u32 dma_rx_phy, u32 chan)
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+				  dma_addr_t dma_rx_phy, u32 chan)
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 {
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 	/* RX descriptor base address list must be written into DMA CSR3 */
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-	writel(dma_rx_phy, ioaddr + DMA_RCV_BASE_ADDR);
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+	writel(lower_32_bits(dma_rx_phy), ioaddr + DMA_RCV_BASE_ADDR);
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 }
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 static void dwmac1000_dma_init_tx(void __iomem *ioaddr,
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 				  struct stmmac_dma_cfg *dma_cfg,
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-				  u32 dma_tx_phy, u32 chan)
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+				  dma_addr_t dma_tx_phy, u32 chan)
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 {
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 	/* TX descriptor base address list must be written into DMA CSR4 */
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-	writel(dma_tx_phy, ioaddr + DMA_TX_BASE_ADDR);
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+	writel(lower_32_bits(dma_tx_phy), ioaddr + DMA_TX_BASE_ADDR);
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 }
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 static u32 dwmac1000_configure_fc(u32 csr6, int rxfifosz)
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@@ -228,10 +218,17 @@
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 				readl(ioaddr + DMA_BUS_MODE + i * 4);
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 }
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-static void dwmac1000_get_hw_feature(void __iomem *ioaddr,
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-				     struct dma_features *dma_cap)
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+static int dwmac1000_get_hw_feature(void __iomem *ioaddr,
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+				    struct dma_features *dma_cap)
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 {
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 	u32 hw_cap = readl(ioaddr + DMA_HW_FEATURE);
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+
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+	if (!hw_cap) {
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+		/* 0x00000000 is the value read on old hardware that does not
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+		 * implement this register
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+		 */
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+		return -EOPNOTSUPP;
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+	}
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 	dma_cap->mbps_10_100 = (hw_cap & DMA_HW_FEAT_MIISEL);
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 	dma_cap->mbps_1000 = (hw_cap & DMA_HW_FEAT_GMIISEL) >> 1;
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@@ -262,6 +259,8 @@
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 	dma_cap->number_tx_channel = (hw_cap & DMA_HW_FEAT_TXCHCNT) >> 22;
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 	/* Alternate (enhanced) DESC mode */
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 	dma_cap->enh_desc = (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24;
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+
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+	return 0;
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 }
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 static void dwmac1000_rx_watchdog(void __iomem *ioaddr, u32 riwt,