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2024-05-10 9999e48639b3cecb08ffb37358bcba3b48161b29 
 kernel/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
....@@ -1,19 +1,10 @@
1
+// SPDX-License-Identifier: GPL-2.0-or-later
12 /**
2
- * dwmac-rk.c - Rockchip RK3288 DWMAC specific glue layer
3
+ * DOC: dwmac-rk.c - Rockchip RK3288 DWMAC specific glue layer
34  *
45  * Copyright (C) 2014 Chen-Zhi (Roger Chen)
56  *
67  * Chen-Zhi (Roger Chen)  <roger.chen@rock-chips.com>
7
- *
8
- * This program is free software; you can redistribute it and/or modify
9
- * it under the terms of the GNU General Public License as published by
10
- * the Free Software Foundation; either version 2 of the License, or
11
- * (at your option) any later version.
12
- *
13
- * This program is distributed in the hope that it will be useful,
14
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
15
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16
- * GNU General Public License for more details.
178  */
189 
1910 #include <linux/stmmac.h>
....@@ -24,6 +15,7 @@
2415 #include <linux/of_net.h>
2516 #include <linux/gpio.h>
2617 #include <linux/module.h>
18
+#include <linux/nvmem-consumer.h>
2719 #include <linux/of_gpio.h>
2820 #include <linux/of_device.h>
2921 #include <linux/platform_device.h>
....@@ -47,7 +39,6 @@
4739 	void (*set_to_qsgmii)(struct rk_priv_data *bsp_priv);
4840 	void (*set_rgmii_speed)(struct rk_priv_data *bsp_priv, int speed);
4941 	void (*set_rmii_speed)(struct rk_priv_data *bsp_priv, int speed);
50
-	void (*set_sgmii_speed)(struct rk_priv_data *bsp_priv, int speed);
5142 	void (*set_clock_selection)(struct rk_priv_data *bsp_priv, bool input,
5243 				    bool enable);
5344 	void (*integrated_phy_power)(struct rk_priv_data *bsp_priv, bool up);
....@@ -55,7 +46,7 @@
5546 
5647 struct rk_priv_data {
5748 	struct platform_device *pdev;
58
-	int phy_iface;
49
+	phy_interface_t phy_iface;
5950 	int bus_id;
6051 	struct regulator *regulator;
6152 	bool suspended;
....@@ -64,7 +55,6 @@
6455 	bool clk_enabled;
6556 	bool clock_input;
6657 	bool integrated_phy;
67
-	struct phy *comphy;
6858 
6959 	struct clk *clk_mac;
7060 	struct clk *gmac_clkin;
....@@ -77,6 +67,7 @@
7767 	struct clk *pclk_mac;
7868 	struct clk *clk_phy;
7969 	struct clk *pclk_xpcs;
70
+	struct clk *clk_xpcs_eee;
8071 
8172 	struct reset_control *phy_reset;
8273 
....@@ -84,7 +75,11 @@
8475 	int rx_delay;
8576 
8677 	struct regmap *grf;
78
+	struct regmap *php_grf;
8779 	struct regmap *xpcs;
80
+
81
+	unsigned char otp_data;
82
+	unsigned int bgs_increment;
8883 };
8984 
9085 /* XPCS */
....@@ -169,10 +164,10 @@
169164 	int ret, i, id = bsp_priv->bus_id;
170165 	u32 val;
171166 
172
-	if (mode == PHY_INTERFACE_MODE_QSGMII && !id)
167
+	if (mode == PHY_INTERFACE_MODE_QSGMII && id > 0)
173168 		return 0;
174169 
175
-	ret = xpcs_soft_reset(bsp_priv, 0);
170
+	ret = xpcs_soft_reset(bsp_priv, id);
176171 	if (ret) {
177172 		dev_err(&bsp_priv->pdev->dev, "xpcs_soft_reset fail %d\n", ret);
178173 		return ret;
....@@ -199,10 +194,10 @@
199194 				   SR_MII_CTRL_AN_ENABLE);
200195 		}
201196 	} else {
202
-		val = xpcs_read(bsp_priv, SR_MII_OFFSET(0) + VR_MII_DIG_CTRL1);
203
-		xpcs_write(bsp_priv, SR_MII_OFFSET(0) + VR_MII_DIG_CTRL1,
197
+		val = xpcs_read(bsp_priv, SR_MII_OFFSET(id) + VR_MII_DIG_CTRL1);
198
+		xpcs_write(bsp_priv, SR_MII_OFFSET(id) + VR_MII_DIG_CTRL1,
204199 			   val | MII_MAC_AUTO_SW);
205
-		xpcs_write(bsp_priv, SR_MII_OFFSET(0) + MII_BMCR,
200
+		xpcs_write(bsp_priv, SR_MII_OFFSET(id) + MII_BMCR,
206201 			   SR_MII_CTRL_AN_ENABLE);
207202 	}
208203 
....@@ -219,9 +214,19 @@
219214 	((((tx) >= 0) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \
220215 	 (((rx) >= 0) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE))
221216 
217
+#define DELAY_ENABLE_BY_ID(soc, tx, rx, id) \
218
+	((((tx) >= 0) ? soc##_GMAC_TXCLK_DLY_ENABLE(id) : soc##_GMAC_TXCLK_DLY_DISABLE(id)) | \
219
+	 (((rx) >= 0) ? soc##_GMAC_RXCLK_DLY_ENABLE(id) : soc##_GMAC_RXCLK_DLY_DISABLE(id)))
220
+
222221 #define DELAY_VALUE(soc, tx, rx) \
223222 	((((tx) >= 0) ? soc##_GMAC_CLK_TX_DL_CFG(tx) : 0) | \
224223 	 (((rx) >= 0) ? soc##_GMAC_CLK_RX_DL_CFG(rx) : 0))
224
+
225
+#define GMAC_RGMII_CLK_DIV_BY_ID(soc, id, div) \
226
+		(soc##_GMAC##id##_CLK_RGMII_DIV##div)
227
+
228
+#define GMAC_RMII_CLK_DIV_BY_ID(soc, id, div) \
229
+		(soc##_GMAC##id##_CLK_RMII_DIV##div)
225230 
226231 /* Integrated EPHY */
227232 
....@@ -264,6 +269,60 @@
264269 	regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
265270 	if (priv->phy_reset)
266271 		reset_control_assert(priv->phy_reset);
272
+}
273
+
274
+/* Integrated FEPHY */
275
+#define RK_FEPHY_SHUTDOWN		GRF_BIT(1)
276
+#define RK_FEPHY_POWERUP		GRF_CLR_BIT(1)
277
+#define RK_FEPHY_INTERNAL_RMII_SEL	GRF_BIT(6)
278
+#define RK_FEPHY_24M_CLK_SEL		(GRF_BIT(8) | GRF_BIT(9))
279
+#define RK_FEPHY_PHY_ID			GRF_BIT(11)
280
+
281
+#define RK_FEPHY_BGS			HIWORD_UPDATE(0x0, 0xf, 0)
282
+
283
+#define RK_FEPHY_BGS_MAX		7
284
+
285
+static void rk_gmac_integrated_fephy_power(struct rk_priv_data *priv,
286
+					   unsigned int ctrl_offset,
287
+					   unsigned int bgs_offset,
288
+					   bool up)
289
+{
290
+	struct device *dev = &priv->pdev->dev;
291
+
292
+	if (IS_ERR(priv->grf) || !priv->phy_reset) {
293
+		dev_err(dev, "%s: Missing rockchip,grf or phy_reset property\n",
294
+			__func__);
295
+		return;
296
+	}
297
+
298
+	if (up) {
299
+		unsigned int bgs = priv->otp_data;
300
+
301
+		reset_control_assert(priv->phy_reset);
302
+		udelay(20);
303
+		regmap_write(priv->grf, ctrl_offset,
304
+			     RK_FEPHY_POWERUP |
305
+			     RK_FEPHY_INTERNAL_RMII_SEL |
306
+			     RK_FEPHY_24M_CLK_SEL |
307
+			     RK_FEPHY_PHY_ID);
308
+
309
+		if (bgs > (RK_FEPHY_BGS_MAX - priv->bgs_increment) &&
310
+		    bgs <= RK_FEPHY_BGS_MAX) {
311
+			bgs = HIWORD_UPDATE(RK_FEPHY_BGS_MAX, 0xf, 0);
312
+		} else {
313
+			bgs += priv->bgs_increment;
314
+			bgs &= 0xf;
315
+			bgs = HIWORD_UPDATE(bgs, 0xf, 0);
316
+		}
317
+
318
+		regmap_write(priv->grf, bgs_offset, bgs);
319
+		usleep_range(10 * 1000, 12 * 1000);
320
+		reset_control_deassert(priv->phy_reset);
321
+		usleep_range(50 * 1000, 60 * 1000);
322
+	} else {
323
+		regmap_write(priv->grf, ctrl_offset,
324
+			     RK_FEPHY_SHUTDOWN);
325
+	}
267326 }
268327 
269328 #define PX30_GRF_GMAC_CON1		0x0904
....@@ -684,7 +743,7 @@
684743 	.set_to_rmii = rk3228_set_to_rmii,
685744 	.set_rgmii_speed = rk3228_set_rgmii_speed,
686745 	.set_rmii_speed = rk3228_set_rmii_speed,
687
-	.integrated_phy_power = rk3228_integrated_phy_power,
746
+	.integrated_phy_power =  rk3228_integrated_phy_power,
688747 };
689748 
690749 #define RK3288_GRF_SOC_CON1	0x0248
....@@ -989,7 +1048,7 @@
9891048 	.set_to_rmii = rk3328_set_to_rmii,
9901049 	.set_rgmii_speed = rk3328_set_rgmii_speed,
9911050 	.set_rmii_speed = rk3328_set_rmii_speed,
992
-	.integrated_phy_power = rk3328_integrated_phy_power,
1051
+	.integrated_phy_power =  rk3328_integrated_phy_power,
9931052 };
9941053 
9951054 #define RK3366_GRF_SOC_CON6	0x0418
....@@ -1322,6 +1381,361 @@
13221381 	.set_rmii_speed = rk3399_set_rmii_speed,
13231382 };
13241383 
1384
+#define RK3528_VO_GRF_GMAC_CON		0X60018
1385
+#define RK3528_VPU_GRF_GMAC_CON5	0X40018
1386
+#define RK3528_VPU_GRF_GMAC_CON6	0X4001c
1387
+
1388
+#define RK3528_GMAC_RXCLK_DLY_ENABLE	GRF_BIT(15)
1389
+#define RK3528_GMAC_RXCLK_DLY_DISABLE	GRF_CLR_BIT(15)
1390
+#define RK3528_GMAC_TXCLK_DLY_ENABLE	GRF_BIT(14)
1391
+#define RK3528_GMAC_TXCLK_DLY_DISABLE	GRF_CLR_BIT(14)
1392
+
1393
+#define RK3528_GMAC_CLK_RX_DL_CFG(val)	HIWORD_UPDATE(val, 0xFF, 8)
1394
+#define RK3528_GMAC_CLK_TX_DL_CFG(val)	HIWORD_UPDATE(val, 0xFF, 0)
1395
+
1396
+#define RK3528_GMAC0_PHY_INTF_SEL_RMII	GRF_BIT(1)
1397
+#define RK3528_GMAC1_PHY_INTF_SEL_RGMII	GRF_CLR_BIT(8)
1398
+#define RK3528_GMAC1_PHY_INTF_SEL_RMII	GRF_BIT(8)
1399
+
1400
+#define RK3528_GMAC1_CLK_SELET_CRU	GRF_CLR_BIT(12)
1401
+#define RK3528_GMAC1_CLK_SELET_IO	GRF_BIT(12)
1402
+
1403
+#define RK3528_GMAC0_CLK_RMII_DIV2	GRF_BIT(3)
1404
+#define RK3528_GMAC0_CLK_RMII_DIV20	GRF_CLR_BIT(3)
1405
+#define RK3528_GMAC1_CLK_RMII_DIV2	GRF_BIT(10)
1406
+#define RK3528_GMAC1_CLK_RMII_DIV20	GRF_CLR_BIT(10)
1407
+
1408
+#define RK3528_GMAC1_CLK_RGMII_DIV1		\
1409
+			(GRF_CLR_BIT(11) | GRF_CLR_BIT(10))
1410
+#define RK3528_GMAC1_CLK_RGMII_DIV5		\
1411
+			(GRF_BIT(11) | GRF_BIT(10))
1412
+#define RK3528_GMAC1_CLK_RGMII_DIV50		\
1413
+			(GRF_BIT(11) | GRF_CLR_BIT(10))
1414
+
1415
+#define RK3528_GMAC0_CLK_RMII_GATE	GRF_BIT(2)
1416
+#define RK3528_GMAC0_CLK_RMII_NOGATE	GRF_CLR_BIT(2)
1417
+#define RK3528_GMAC1_CLK_RMII_GATE	GRF_BIT(9)
1418
+#define RK3528_GMAC1_CLK_RMII_NOGATE	GRF_CLR_BIT(9)
1419
+
1420
+#define RK3528_VO_GRF_MACPHY_CON0		0X6001c
1421
+#define RK3528_VO_GRF_MACPHY_CON1		0X60020
1422
+
1423
+static void rk3528_set_to_rgmii(struct rk_priv_data *bsp_priv,
1424
+				int tx_delay, int rx_delay)
1425
+{
1426
+	struct device *dev = &bsp_priv->pdev->dev;
1427
+
1428
+	if (IS_ERR(bsp_priv->grf)) {
1429
+		dev_err(dev, "Missing rockchip,grf property\n");
1430
+		return;
1431
+	}
1432
+
1433
+	regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,
1434
+		     RK3528_GMAC1_PHY_INTF_SEL_RGMII);
1435
+
1436
+	regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,
1437
+		     DELAY_ENABLE(RK3528, tx_delay, rx_delay));
1438
+
1439
+	regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON6,
1440
+		     DELAY_VALUE(RK3528, tx_delay, rx_delay));
1441
+}
1442
+
1443
+static void rk3528_set_to_rmii(struct rk_priv_data *bsp_priv)
1444
+{
1445
+	struct device *dev = &bsp_priv->pdev->dev;
1446
+	unsigned int id = bsp_priv->bus_id;
1447
+
1448
+	if (IS_ERR(bsp_priv->grf)) {
1449
+		dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
1450
+		return;
1451
+	}
1452
+
1453
+	if (id == 1)
1454
+		regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,
1455
+			     RK3528_GMAC1_PHY_INTF_SEL_RMII);
1456
+	else
1457
+		regmap_write(bsp_priv->grf, RK3528_VO_GRF_GMAC_CON,
1458
+			     RK3528_GMAC0_PHY_INTF_SEL_RMII |
1459
+			     RK3528_GMAC0_CLK_RMII_DIV2);
1460
+}
1461
+
1462
+static void rk3528_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
1463
+{
1464
+	struct device *dev = &bsp_priv->pdev->dev;
1465
+	unsigned int val = 0;
1466
+
1467
+	switch (speed) {
1468
+	case 10:
1469
+		val = RK3528_GMAC1_CLK_RGMII_DIV50;
1470
+		break;
1471
+	case 100:
1472
+		val = RK3528_GMAC1_CLK_RGMII_DIV5;
1473
+		break;
1474
+	case 1000:
1475
+		val = RK3528_GMAC1_CLK_RGMII_DIV1;
1476
+		break;
1477
+	default:
1478
+		goto err;
1479
+	}
1480
+
1481
+	regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, val);
1482
+	return;
1483
+err:
1484
+	dev_err(dev, "unknown RGMII speed value for GMAC speed=%d", speed);
1485
+}
1486
+
1487
+static void rk3528_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
1488
+{
1489
+	struct device *dev = &bsp_priv->pdev->dev;
1490
+	unsigned int val, offset, id = bsp_priv->bus_id;
1491
+
1492
+	switch (speed) {
1493
+	case 10:
1494
+		val = (id == 1) ? RK3528_GMAC1_CLK_RMII_DIV20 :
1495
+				  RK3528_GMAC0_CLK_RMII_DIV20;
1496
+		break;
1497
+	case 100:
1498
+		val = (id == 1) ? RK3528_GMAC1_CLK_RMII_DIV2 :
1499
+				  RK3528_GMAC0_CLK_RMII_DIV2;
1500
+		break;
1501
+	default:
1502
+		goto err;
1503
+	}
1504
+
1505
+	offset = (id == 1) ? RK3528_VPU_GRF_GMAC_CON5 : RK3528_VO_GRF_GMAC_CON;
1506
+	regmap_write(bsp_priv->grf, offset, val);
1507
+
1508
+	return;
1509
+err:
1510
+	dev_err(dev, "unknown RMII speed value for GMAC speed=%d", speed);
1511
+}
1512
+
1513
+static void rk3528_set_clock_selection(struct rk_priv_data *bsp_priv,
1514
+				       bool input, bool enable)
1515
+{
1516
+	unsigned int value, id = bsp_priv->bus_id;
1517
+
1518
+	if (id == 1) {
1519
+		value = input ? RK3528_GMAC1_CLK_SELET_IO :
1520
+				RK3528_GMAC1_CLK_SELET_CRU;
1521
+		value |= enable ? RK3528_GMAC1_CLK_RMII_NOGATE :
1522
+				  RK3528_GMAC1_CLK_RMII_GATE;
1523
+		regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, value);
1524
+	} else {
1525
+		value = enable ? RK3528_GMAC0_CLK_RMII_NOGATE :
1526
+				 RK3528_GMAC0_CLK_RMII_GATE;
1527
+		regmap_write(bsp_priv->grf, RK3528_VO_GRF_GMAC_CON, value);
1528
+	}
1529
+}
1530
+
1531
+static void rk3528_integrated_sphy_power(struct rk_priv_data *priv, bool up)
1532
+{
1533
+	rk_gmac_integrated_fephy_power(priv, RK3528_VO_GRF_MACPHY_CON0,
1534
+				       RK3528_VO_GRF_MACPHY_CON1, up);
1535
+}
1536
+
1537
+static const struct rk_gmac_ops rk3528_ops = {
1538
+	.set_to_rgmii = rk3528_set_to_rgmii,
1539
+	.set_to_rmii = rk3528_set_to_rmii,
1540
+	.set_rgmii_speed = rk3528_set_rgmii_speed,
1541
+	.set_rmii_speed = rk3528_set_rmii_speed,
1542
+	.set_clock_selection = rk3528_set_clock_selection,
1543
+	.integrated_phy_power = rk3528_integrated_sphy_power,
1544
+};
1545
+
1546
+/* sys_grf */
1547
+#define RK3562_GRF_SYS_SOC_CON0			0X0400
1548
+#define RK3562_GRF_SYS_SOC_CON1			0X0404
1549
+
1550
+#define RK3562_GMAC0_CLK_RMII_MODE		GRF_BIT(5)
1551
+#define RK3562_GMAC0_CLK_RGMII_MODE		GRF_CLR_BIT(5)
1552
+
1553
+#define RK3562_GMAC0_CLK_RMII_GATE		GRF_BIT(6)
1554
+#define RK3562_GMAC0_CLK_RMII_NOGATE		GRF_CLR_BIT(6)
1555
+
1556
+#define RK3562_GMAC0_CLK_RMII_DIV2		GRF_BIT(7)
1557
+#define RK3562_GMAC0_CLK_RMII_DIV20		GRF_CLR_BIT(7)
1558
+
1559
+#define RK3562_GMAC0_CLK_RGMII_DIV1		\
1560
+				(GRF_CLR_BIT(7) | GRF_CLR_BIT(8))
1561
+#define RK3562_GMAC0_CLK_RGMII_DIV5		\
1562
+				(GRF_BIT(7) | GRF_BIT(8))
1563
+#define RK3562_GMAC0_CLK_RGMII_DIV50		\
1564
+				(GRF_CLR_BIT(7) | GRF_BIT(8))
1565
+
1566
+#define RK3562_GMAC0_CLK_RMII_DIV2		GRF_BIT(7)
1567
+#define RK3562_GMAC0_CLK_RMII_DIV20		GRF_CLR_BIT(7)
1568
+
1569
+#define RK3562_GMAC0_CLK_SELET_CRU		GRF_CLR_BIT(9)
1570
+#define RK3562_GMAC0_CLK_SELET_IO		GRF_BIT(9)
1571
+
1572
+#define RK3562_GMAC1_CLK_RMII_GATE		GRF_BIT(12)
1573
+#define RK3562_GMAC1_CLK_RMII_NOGATE		GRF_CLR_BIT(12)
1574
+
1575
+#define RK3562_GMAC1_CLK_RMII_DIV2		GRF_BIT(13)
1576
+#define RK3562_GMAC1_CLK_RMII_DIV20		GRF_CLR_BIT(13)
1577
+
1578
+#define RK3562_GMAC1_RMII_SPEED100		GRF_BIT(11)
1579
+#define RK3562_GMAC1_RMII_SPEED10		GRF_CLR_BIT(11)
1580
+
1581
+#define RK3562_GMAC1_CLK_SELET_CRU		GRF_CLR_BIT(15)
1582
+#define RK3562_GMAC1_CLK_SELET_IO		GRF_BIT(15)
1583
+
1584
+/* ioc_grf */
1585
+#define RK3562_GRF_IOC_GMAC_IOFUNC0_CON0	0X10400
1586
+#define RK3562_GRF_IOC_GMAC_IOFUNC0_CON1	0X10404
1587
+#define RK3562_GRF_IOC_GMAC_IOFUNC1_CON0	0X00400
1588
+#define RK3562_GRF_IOC_GMAC_IOFUNC1_CON1	0X00404
1589
+
1590
+#define RK3562_GMAC_RXCLK_DLY_ENABLE		GRF_BIT(1)
1591
+#define RK3562_GMAC_RXCLK_DLY_DISABLE		GRF_CLR_BIT(1)
1592
+#define RK3562_GMAC_TXCLK_DLY_ENABLE		GRF_BIT(0)
1593
+#define RK3562_GMAC_TXCLK_DLY_DISABLE		GRF_CLR_BIT(0)
1594
+
1595
+#define RK3562_GMAC_CLK_RX_DL_CFG(val)		HIWORD_UPDATE(val, 0xFF, 8)
1596
+#define RK3562_GMAC_CLK_TX_DL_CFG(val)		HIWORD_UPDATE(val, 0xFF, 0)
1597
+
1598
+#define RK3562_GMAC0_IO_EXTCLK_SELET_CRU	GRF_CLR_BIT(2)
1599
+#define RK3562_GMAC0_IO_EXTCLK_SELET_IO		GRF_BIT(2)
1600
+
1601
+#define RK3562_GMAC1_IO_EXTCLK_SELET_CRU	GRF_CLR_BIT(3)
1602
+#define RK3562_GMAC1_IO_EXTCLK_SELET_IO		GRF_BIT(3)
1603
+
1604
+static void rk3562_set_to_rgmii(struct rk_priv_data *bsp_priv,
1605
+				int tx_delay, int rx_delay)
1606
+{
1607
+	struct device *dev = &bsp_priv->pdev->dev;
1608
+
1609
+	if (IS_ERR(bsp_priv->grf) || IS_ERR(bsp_priv->php_grf)) {
1610
+		dev_err(dev, "Missing rockchip,grf or rockchip,php_grf property\n");
1611
+		return;
1612
+	}
1613
+
1614
+	if (bsp_priv->bus_id > 0)
1615
+		return;
1616
+
1617
+	regmap_write(bsp_priv->grf, RK3562_GRF_SYS_SOC_CON0,
1618
+		     RK3562_GMAC0_CLK_RGMII_MODE);
1619
+
1620
+	regmap_write(bsp_priv->php_grf, RK3562_GRF_IOC_GMAC_IOFUNC0_CON1,
1621
+		     DELAY_ENABLE(RK3562, tx_delay, rx_delay));
1622
+	regmap_write(bsp_priv->php_grf, RK3562_GRF_IOC_GMAC_IOFUNC0_CON0,
1623
+		     DELAY_VALUE(RK3562, tx_delay, rx_delay));
1624
+
1625
+	regmap_write(bsp_priv->php_grf, RK3562_GRF_IOC_GMAC_IOFUNC1_CON1,
1626
+		     DELAY_ENABLE(RK3562, tx_delay, rx_delay));
1627
+	regmap_write(bsp_priv->php_grf, RK3562_GRF_IOC_GMAC_IOFUNC1_CON0,
1628
+		     DELAY_VALUE(RK3562, tx_delay, rx_delay));
1629
+}
1630
+
1631
+static void rk3562_set_to_rmii(struct rk_priv_data *bsp_priv)
1632
+{
1633
+	struct device *dev = &bsp_priv->pdev->dev;
1634
+
1635
+	if (IS_ERR(bsp_priv->grf)) {
1636
+		dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
1637
+		return;
1638
+	}
1639
+
1640
+	if (!bsp_priv->bus_id)
1641
+		regmap_write(bsp_priv->grf, RK3562_GRF_SYS_SOC_CON0,
1642
+			     RK3562_GMAC0_CLK_RMII_MODE);
1643
+}
1644
+
1645
+static void rk3562_set_gmac_speed(struct rk_priv_data *bsp_priv, int speed)
1646
+{
1647
+	struct device *dev = &bsp_priv->pdev->dev;
1648
+	unsigned int val = 0, offset, id = bsp_priv->bus_id;
1649
+
1650
+	switch (speed) {
1651
+	case 10:
1652
+		if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) {
1653
+			if (id > 0) {
1654
+				val = GMAC_RMII_CLK_DIV_BY_ID(RK3562, 1, 20);
1655
+				regmap_write(bsp_priv->grf, RK3562_GRF_SYS_SOC_CON0,
1656
+					     RK3562_GMAC1_RMII_SPEED10);
1657
+			} else {
1658
+				val = GMAC_RMII_CLK_DIV_BY_ID(RK3562, 0, 20);
1659
+			}
1660
+		} else {
1661
+			val = GMAC_RGMII_CLK_DIV_BY_ID(RK3562, 0, 50);
1662
+		}
1663
+		break;
1664
+	case 100:
1665
+		if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) {
1666
+			if (id > 0) {
1667
+				val = GMAC_RMII_CLK_DIV_BY_ID(RK3562, 1, 2);
1668
+				regmap_write(bsp_priv->grf, RK3562_GRF_SYS_SOC_CON0,
1669
+					     RK3562_GMAC1_RMII_SPEED100);
1670
+			} else {
1671
+				val = GMAC_RMII_CLK_DIV_BY_ID(RK3562, 0, 2);
1672
+			}
1673
+		} else {
1674
+			val = GMAC_RGMII_CLK_DIV_BY_ID(RK3562, 0, 5);
1675
+		}
1676
+		break;
1677
+	case 1000:
1678
+		if (bsp_priv->phy_iface != PHY_INTERFACE_MODE_RMII)
1679
+			val = GMAC_RGMII_CLK_DIV_BY_ID(RK3562, 0, 1);
1680
+		else
1681
+			goto err;
1682
+		break;
1683
+	default:
1684
+		goto err;
1685
+	}
1686
+
1687
+	offset = (bsp_priv->bus_id > 0) ? RK3562_GRF_SYS_SOC_CON1 :
1688
+					  RK3562_GRF_SYS_SOC_CON0;
1689
+	regmap_write(bsp_priv->grf, offset, val);
1690
+
1691
+	return;
1692
+err:
1693
+	dev_err(dev, "unknown speed value for GMAC speed=%d", speed);
1694
+}
1695
+
1696
+static void rk3562_set_clock_selection(struct rk_priv_data *bsp_priv, bool input,
1697
+				       bool enable)
1698
+{
1699
+	struct device *dev = &bsp_priv->pdev->dev;
1700
+	unsigned int value;
1701
+
1702
+	if (IS_ERR(bsp_priv->grf) || IS_ERR(bsp_priv->php_grf)) {
1703
+		dev_err(dev, "Missing rockchip,grf or rockchip,php_grf property\n");
1704
+		return;
1705
+	}
1706
+
1707
+	if (!bsp_priv->bus_id) {
1708
+		value = input ? RK3562_GMAC0_CLK_SELET_IO :
1709
+				RK3562_GMAC0_CLK_SELET_CRU;
1710
+		value |= enable ? RK3562_GMAC0_CLK_RMII_NOGATE :
1711
+				  RK3562_GMAC0_CLK_RMII_GATE;
1712
+		regmap_write(bsp_priv->grf, RK3562_GRF_SYS_SOC_CON0, value);
1713
+
1714
+		value = input ? RK3562_GMAC0_IO_EXTCLK_SELET_IO :
1715
+				RK3562_GMAC0_IO_EXTCLK_SELET_CRU;
1716
+		regmap_write(bsp_priv->php_grf, RK3562_GRF_IOC_GMAC_IOFUNC0_CON1, value);
1717
+		regmap_write(bsp_priv->php_grf, RK3562_GRF_IOC_GMAC_IOFUNC1_CON1, value);
1718
+	} else {
1719
+		value = input ? RK3562_GMAC1_CLK_SELET_IO :
1720
+				RK3562_GMAC1_CLK_SELET_CRU;
1721
+		value |= enable ? RK3562_GMAC1_CLK_RMII_NOGATE :
1722
+				 RK3562_GMAC1_CLK_RMII_GATE;
1723
+		regmap_write(bsp_priv->grf, RK3562_GRF_SYS_SOC_CON1, value);
1724
+
1725
+		value = input ? RK3562_GMAC1_IO_EXTCLK_SELET_IO :
1726
+				RK3562_GMAC1_IO_EXTCLK_SELET_CRU;
1727
+		regmap_write(bsp_priv->php_grf, RK3562_GRF_IOC_GMAC_IOFUNC1_CON1, value);
1728
+	}
1729
+}
1730
+
1731
+static const struct rk_gmac_ops rk3562_ops = {
1732
+	.set_to_rgmii = rk3562_set_to_rgmii,
1733
+	.set_to_rmii = rk3562_set_to_rmii,
1734
+	.set_rgmii_speed = rk3562_set_gmac_speed,
1735
+	.set_rmii_speed = rk3562_set_gmac_speed,
1736
+	.set_clock_selection = rk3562_set_clock_selection,
1737
+};
1738
+
13251739 #define RK3568_GRF_GMAC0_CON0		0X0380
13261740 #define RK3568_GRF_GMAC0_CON1		0X0384
13271741 #define RK3568_GRF_GMAC1_CON0		0X0388
....@@ -1451,34 +1865,6 @@
14511865 			__func__, rate, ret);
14521866 }
14531867 
1454
-static void rk3568_set_gmac_sgmii_speed(struct rk_priv_data *bsp_priv, int speed)
1455
-{
1456
-	struct device *dev = &bsp_priv->pdev->dev;
1457
-	unsigned int ctrl;
1458
-
1459
-	/* Only gmac1 set the speed for port1 */
1460
-	if (!bsp_priv->bus_id)
1461
-		return;
1462
-
1463
-	switch (speed) {
1464
-	case 10:
1465
-		ctrl = BMCR_SPEED10;
1466
-		break;
1467
-	case 100:
1468
-		ctrl = BMCR_SPEED100;
1469
-		break;
1470
-	case 1000:
1471
-		ctrl = BMCR_SPEED1000;
1472
-		break;
1473
-	default:
1474
-		dev_err(dev, "unknown speed value for GMAC speed=%d", speed);
1475
-		return;
1476
-	}
1477
-
1478
-	xpcs_write(bsp_priv, SR_MII_OFFSET(bsp_priv->bus_id) + MII_BMCR,
1479
-		   ctrl | BMCR_FULLDPLX);
1480
-}
1481
-
14821868 static const struct rk_gmac_ops rk3568_ops = {
14831869 	.set_to_rgmii = rk3568_set_to_rgmii,
14841870 	.set_to_rmii = rk3568_set_to_rmii,
....@@ -1486,7 +1872,202 @@
14861872 	.set_to_qsgmii = rk3568_set_to_qsgmii,
14871873 	.set_rgmii_speed = rk3568_set_gmac_speed,
14881874 	.set_rmii_speed = rk3568_set_gmac_speed,
1489
-	.set_sgmii_speed = rk3568_set_gmac_sgmii_speed,
1875
+};
1876
+
1877
+/* sys_grf */
1878
+#define RK3588_GRF_GMAC_CON7			0X031c
1879
+#define RK3588_GRF_GMAC_CON8			0X0320
1880
+#define RK3588_GRF_GMAC_CON9			0X0324
1881
+
1882
+#define RK3588_GMAC_RXCLK_DLY_ENABLE(id)	GRF_BIT(2 * (id) + 3)
1883
+#define RK3588_GMAC_RXCLK_DLY_DISABLE(id)	GRF_CLR_BIT(2 * (id) + 3)
1884
+#define RK3588_GMAC_TXCLK_DLY_ENABLE(id)	GRF_BIT(2 * (id) + 2)
1885
+#define RK3588_GMAC_TXCLK_DLY_DISABLE(id)	GRF_CLR_BIT(2 * (id) + 2)
1886
+
1887
+#define RK3588_GMAC_CLK_RX_DL_CFG(val)		HIWORD_UPDATE(val, 0xFF, 8)
1888
+#define RK3588_GMAC_CLK_TX_DL_CFG(val)		HIWORD_UPDATE(val, 0xFF, 0)
1889
+
1890
+/* php_grf */
1891
+#define RK3588_GRF_GMAC_CON0			0X0008
1892
+#define RK3588_GRF_CLK_CON1			0X0070
1893
+
1894
+#define RK3588_GMAC_PHY_INTF_SEL_RGMII(id)	\
1895
+	(GRF_BIT(3 + (id) * 6) | GRF_CLR_BIT(4 + (id) * 6) | GRF_CLR_BIT(5 + (id) * 6))
1896
+#define RK3588_GMAC_PHY_INTF_SEL_RMII(id)	\
1897
+	(GRF_CLR_BIT(3 + (id) * 6) | GRF_CLR_BIT(4 + (id) * 6) | GRF_BIT(5 + (id) * 6))
1898
+
1899
+#define RK3588_GMAC_CLK_RMII_MODE(id)		GRF_BIT(5 * (id))
1900
+#define RK3588_GMAC_CLK_RGMII_MODE(id)		GRF_CLR_BIT(5 * (id))
1901
+
1902
+#define RK3588_GMAC_CLK_SELET_CRU(id)		GRF_BIT(5 * (id) + 4)
1903
+#define RK3588_GMAC_CLK_SELET_IO(id)		GRF_CLR_BIT(5 * (id) + 4)
1904
+
1905
+#define RK3588_GMA_CLK_RMII_DIV2(id)		GRF_BIT(5 * (id) + 2)
1906
+#define RK3588_GMA_CLK_RMII_DIV20(id)		GRF_CLR_BIT(5 * (id) + 2)
1907
+
1908
+#define RK3588_GMAC_CLK_RGMII_DIV1(id)		\
1909
+			(GRF_CLR_BIT(5 * (id) + 2) | GRF_CLR_BIT(5 * (id) + 3))
1910
+#define RK3588_GMAC_CLK_RGMII_DIV5(id)		\
1911
+			(GRF_BIT(5 * (id) + 2) | GRF_BIT(5 * (id) + 3))
1912
+#define RK3588_GMAC_CLK_RGMII_DIV50(id)		\
1913
+			(GRF_CLR_BIT(5 * (id) + 2) | GRF_BIT(5 * (id) + 3))
1914
+
1915
+#define RK3588_GMAC_CLK_RMII_GATE(id)		GRF_BIT(5 * (id) + 1)
1916
+#define RK3588_GMAC_CLK_RMII_NOGATE(id)		GRF_CLR_BIT(5 * (id) + 1)
1917
+
1918
+static void rk3588_set_to_rgmii(struct rk_priv_data *bsp_priv,
1919
+				int tx_delay, int rx_delay)
1920
+{
1921
+	struct device *dev = &bsp_priv->pdev->dev;
1922
+	u32 offset_con, id = bsp_priv->bus_id;
1923
+
1924
+	if (IS_ERR(bsp_priv->grf) || IS_ERR(bsp_priv->php_grf)) {
1925
+		dev_err(dev, "Missing rockchip,grf or rockchip,php_grf property\n");
1926
+		return;
1927
+	}
1928
+
1929
+	offset_con = bsp_priv->bus_id == 1 ? RK3588_GRF_GMAC_CON9 :
1930
+					     RK3588_GRF_GMAC_CON8;
1931
+
1932
+	regmap_write(bsp_priv->php_grf, RK3588_GRF_GMAC_CON0,
1933
+		     RK3588_GMAC_PHY_INTF_SEL_RGMII(id));
1934
+
1935
+	regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1,
1936
+		     RK3588_GMAC_CLK_RGMII_MODE(id));
1937
+
1938
+	regmap_write(bsp_priv->grf, RK3588_GRF_GMAC_CON7,
1939
+		     DELAY_ENABLE_BY_ID(RK3588, tx_delay, rx_delay, id));
1940
+
1941
+	regmap_write(bsp_priv->grf, offset_con,
1942
+		     DELAY_VALUE(RK3588, tx_delay, rx_delay));
1943
+}
1944
+
1945
+static void rk3588_set_to_rmii(struct rk_priv_data *bsp_priv)
1946
+{
1947
+	struct device *dev = &bsp_priv->pdev->dev;
1948
+
1949
+	if (IS_ERR(bsp_priv->php_grf)) {
1950
+		dev_err(dev, "%s: Missing rockchip,php_grf property\n", __func__);
1951
+		return;
1952
+	}
1953
+
1954
+	regmap_write(bsp_priv->php_grf, RK3588_GRF_GMAC_CON0,
1955
+		     RK3588_GMAC_PHY_INTF_SEL_RMII(bsp_priv->bus_id));
1956
+
1957
+	regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1,
1958
+		     RK3588_GMAC_CLK_RMII_MODE(bsp_priv->bus_id));
1959
+}
1960
+
1961
+static void rk3588_set_gmac_speed(struct rk_priv_data *bsp_priv, int speed)
1962
+{
1963
+	struct device *dev = &bsp_priv->pdev->dev;
1964
+	unsigned int val = 0, id = bsp_priv->bus_id;
1965
+
1966
+	switch (speed) {
1967
+	case 10:
1968
+		if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII)
1969
+			val = RK3588_GMA_CLK_RMII_DIV20(id);
1970
+		else
1971
+			val = RK3588_GMAC_CLK_RGMII_DIV50(id);
1972
+		break;
1973
+	case 100:
1974
+		if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII)
1975
+			val = RK3588_GMA_CLK_RMII_DIV2(id);
1976
+		else
1977
+			val = RK3588_GMAC_CLK_RGMII_DIV5(id);
1978
+		break;
1979
+	case 1000:
1980
+		if (bsp_priv->phy_iface != PHY_INTERFACE_MODE_RMII)
1981
+			val = RK3588_GMAC_CLK_RGMII_DIV1(id);
1982
+		else
1983
+			goto err;
1984
+		break;
1985
+	default:
1986
+		goto err;
1987
+	}
1988
+
1989
+	regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1, val);
1990
+
1991
+	return;
1992
+err:
1993
+	dev_err(dev, "unknown speed value for GMAC speed=%d", speed);
1994
+}
1995
+
1996
+static void rk3588_set_clock_selection(struct rk_priv_data *bsp_priv, bool input,
1997
+				       bool enable)
1998
+{
1999
+	unsigned int val = input ? RK3588_GMAC_CLK_SELET_IO(bsp_priv->bus_id) :
2000
+				   RK3588_GMAC_CLK_SELET_CRU(bsp_priv->bus_id);
2001
+
2002
+	val |= enable ? RK3588_GMAC_CLK_RMII_NOGATE(bsp_priv->bus_id) :
2003
+			RK3588_GMAC_CLK_RMII_GATE(bsp_priv->bus_id);
2004
+
2005
+	regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1, val);
2006
+}
2007
+
2008
+static const struct rk_gmac_ops rk3588_ops = {
2009
+	.set_to_rgmii = rk3588_set_to_rgmii,
2010
+	.set_to_rmii = rk3588_set_to_rmii,
2011
+	.set_rgmii_speed = rk3588_set_gmac_speed,
2012
+	.set_rmii_speed = rk3588_set_gmac_speed,
2013
+	.set_clock_selection = rk3588_set_clock_selection,
2014
+};
2015
+
2016
+#define RV1106_VOGRF_GMAC_CLK_CON		0X60004
2017
+
2018
+#define RV1106_VOGRF_MACPHY_RMII_MODE		GRF_BIT(0)
2019
+#define RV1106_VOGRF_GMAC_CLK_RMII_DIV2		GRF_BIT(2)
2020
+#define RV1106_VOGRF_GMAC_CLK_RMII_DIV20	GRF_CLR_BIT(2)
2021
+
2022
+#define RV1106_VOGRF_MACPHY_CON0		0X60028
2023
+#define RV1106_VOGRF_MACPHY_CON1		0X6002C
2024
+
2025
+static void rv1106_set_to_rmii(struct rk_priv_data *bsp_priv)
2026
+{
2027
+	struct device *dev = &bsp_priv->pdev->dev;
2028
+
2029
+	if (IS_ERR(bsp_priv->grf)) {
2030
+		dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
2031
+		return;
2032
+	}
2033
+
2034
+	regmap_write(bsp_priv->grf, RV1106_VOGRF_GMAC_CLK_CON,
2035
+		     RV1106_VOGRF_MACPHY_RMII_MODE |
2036
+		     RV1106_VOGRF_GMAC_CLK_RMII_DIV2);
2037
+}
2038
+
2039
+static void rv1106_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
2040
+{
2041
+	struct device *dev = &bsp_priv->pdev->dev;
2042
+	unsigned int val = 0;
2043
+
2044
+	if (IS_ERR(bsp_priv->grf)) {
2045
+		dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
2046
+		return;
2047
+	}
2048
+
2049
+	if (speed == 10) {
2050
+		val = RV1106_VOGRF_GMAC_CLK_RMII_DIV20;
2051
+	} else if (speed == 100) {
2052
+		val = RV1106_VOGRF_GMAC_CLK_RMII_DIV2;
2053
+	} else {
2054
+		dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
2055
+		return;
2056
+	}
2057
+
2058
+	regmap_write(bsp_priv->grf, RV1106_VOGRF_GMAC_CLK_CON, val);
2059
+}
2060
+
2061
+static void rv1106_integrated_sphy_power(struct rk_priv_data *priv, bool up)
2062
+{
2063
+	rk_gmac_integrated_fephy_power(priv, RV1106_VOGRF_MACPHY_CON0,
2064
+				       RV1106_VOGRF_MACPHY_CON1, up);
2065
+}
2066
+
2067
+static const struct rk_gmac_ops rv1106_ops = {
2068
+	.set_to_rmii = rv1106_set_to_rmii,
2069
+	.set_rmii_speed = rv1106_set_rmii_speed,
2070
+	.integrated_phy_power = rv1106_integrated_sphy_power,
14902071 };
14912072 
14922073 #define RV1108_GRF_GMAC_CON0		0X0900
....@@ -1708,8 +2289,10 @@
17082289 		   bsp_priv->phy_iface == PHY_INTERFACE_MODE_QSGMII) {
17092290 		bsp_priv->pclk_xpcs = devm_clk_get(dev, "pclk_xpcs");
17102291 		if (IS_ERR(bsp_priv->pclk_xpcs))
1711
-			dev_err(dev, "cannot get clock %s\n",
1712
-				"pclk_xpcs");
2292
+			dev_err(dev, "cannot get clock %s\n", "pclk_xpcs");
2293
+		bsp_priv->clk_xpcs_eee = devm_clk_get(dev, "clk_xpcs_eee");
2294
+		if (IS_ERR(bsp_priv->clk_xpcs_eee))
2295
+			dev_err(dev, "cannot get clock %s\n", "clk_xpcs_eee");
17132296 	}
17142297 
17152298 	bsp_priv->clk_mac_speed = devm_clk_get(dev, "clk_mac_speed");
....@@ -1777,9 +2360,12 @@
17772360 			if (!IS_ERR(bsp_priv->pclk_xpcs))
17782361 				clk_prepare_enable(bsp_priv->pclk_xpcs);
17792362 
2363
+			if (!IS_ERR(bsp_priv->clk_xpcs_eee))
2364
+				clk_prepare_enable(bsp_priv->clk_xpcs_eee);
2365
+
17802366 			if (bsp_priv->ops && bsp_priv->ops->set_clock_selection)
1781
-				bsp_priv->ops->set_clock_selection(bsp_priv, bsp_priv->clock_input,
1782
-								   true);
2367
+				bsp_priv->ops->set_clock_selection(bsp_priv,
2368
+					       bsp_priv->clock_input, true);
17832369 
17842370 			/**
17852371 			 * if (!IS_ERR(bsp_priv->clk_mac))
....@@ -1791,8 +2377,8 @@
17912377 	} else {
17922378 		if (bsp_priv->clk_enabled) {
17932379 			if (bsp_priv->ops && bsp_priv->ops->set_clock_selection)
1794
-				bsp_priv->ops->set_clock_selection(bsp_priv, bsp_priv->clock_input,
1795
-								   false);
2380
+				bsp_priv->ops->set_clock_selection(bsp_priv,
2381
+					      bsp_priv->clock_input, false);
17962382 
17972383 			if (phy_iface == PHY_INTERFACE_MODE_RMII) {
17982384 				clk_disable_unprepare(bsp_priv->mac_clk_rx);
....@@ -1813,6 +2399,8 @@
18132399 			clk_disable_unprepare(bsp_priv->clk_mac_speed);
18142400 
18152401 			clk_disable_unprepare(bsp_priv->pclk_xpcs);
2402
+
2403
+			clk_disable_unprepare(bsp_priv->clk_xpcs_eee);
18162404 
18172405 			/**
18182406 			 * if (!IS_ERR(bsp_priv->clk_mac))
....@@ -1861,7 +2449,7 @@
18612449 	if (!bsp_priv)
18622450 		return ERR_PTR(-ENOMEM);
18632451 
1864
-	bsp_priv->phy_iface = of_get_phy_mode(dev->of_node);
2452
+	of_get_phy_mode(dev->of_node, &bsp_priv->phy_iface);
18652453 	bsp_priv->ops = ops;
18662454 	bsp_priv->bus_id = plat->bus_id;
18672455 
....@@ -1912,24 +2500,64 @@
19122500 
19132501 	bsp_priv->grf = syscon_regmap_lookup_by_phandle(dev->of_node,
19142502 							"rockchip,grf");
2503
+	bsp_priv->php_grf = syscon_regmap_lookup_by_phandle(dev->of_node,
2504
+							    "rockchip,php_grf");
19152505 	bsp_priv->xpcs = syscon_regmap_lookup_by_phandle(dev->of_node,
19162506 							 "rockchip,xpcs");
19172507 	if (!IS_ERR(bsp_priv->xpcs)) {
1918
-		bsp_priv->comphy = devm_of_phy_get(&pdev->dev, dev->of_node, NULL);
1919
-		if (IS_ERR(bsp_priv->comphy)) {
1920
-			bsp_priv->comphy = NULL;
2508
+		struct phy *comphy;
2509
+
2510
+		comphy = devm_of_phy_get(&pdev->dev, dev->of_node, NULL);
2511
+		if (IS_ERR(comphy))
19212512 			dev_err(dev, "devm_of_phy_get error\n");
1922
-		}
2513
+		ret = phy_init(comphy);
2514
+		if (ret)
2515
+			dev_err(dev, "phy_init error\n");
19232516 	}
19242517 
19252518 	if (plat->phy_node) {
19262519 		bsp_priv->integrated_phy = of_property_read_bool(plat->phy_node,
19272520 								 "phy-is-integrated");
19282521 		if (bsp_priv->integrated_phy) {
2522
+			unsigned char *efuse_buf;
2523
+			struct nvmem_cell *cell;
2524
+			size_t len;
2525
+
19292526 			bsp_priv->phy_reset = of_reset_control_get(plat->phy_node, NULL);
19302527 			if (IS_ERR(bsp_priv->phy_reset)) {
19312528 				dev_err(&pdev->dev, "No PHY reset control found.\n");
19322529 				bsp_priv->phy_reset = NULL;
2530
+			}
2531
+
2532
+			if (of_property_read_u32(plat->phy_node, "bgs,increment",
2533
+						 &bsp_priv->bgs_increment)) {
2534
+				bsp_priv->bgs_increment = 0;
2535
+			} else {
2536
+				if (bsp_priv->bgs_increment > RK_FEPHY_BGS_MAX) {
2537
+					dev_err(dev, "%s: error bgs increment: %d\n",
2538
+						__func__, bsp_priv->bgs_increment);
2539
+					bsp_priv->bgs_increment = RK_FEPHY_BGS_MAX;
2540
+				}
2541
+			}
2542
+
2543
+			/* Read bgs from OTP if it exists */
2544
+			cell = nvmem_cell_get(dev, "bgs");
2545
+			if (IS_ERR(cell)) {
2546
+				if (PTR_ERR(cell) != -EPROBE_DEFER)
2547
+					dev_info(dev, "failed to get bgs cell: %ld, use default\n",
2548
+						 PTR_ERR(cell));
2549
+				else
2550
+					return ERR_CAST(cell);
2551
+			} else {
2552
+				efuse_buf = nvmem_cell_read(cell, &len);
2553
+				nvmem_cell_put(cell);
2554
+				if (!IS_ERR(efuse_buf)) {
2555
+					if (len == 1)
2556
+						bsp_priv->otp_data = efuse_buf[0];
2557
+					kfree(efuse_buf);
2558
+				} else {
2559
+					dev_err(dev, "failed to get efuse buf, use default\n");
2560
+				}
19332561 			}
19342562 		}
19352563 	}
....@@ -1980,23 +2608,11 @@
19802608 		break;
19812609 	case PHY_INTERFACE_MODE_SGMII:
19822610 		dev_info(dev, "init for SGMII\n");
1983
-		ret = phy_init(bsp_priv->comphy);
1984
-		if (ret) {
1985
-			dev_err(dev, "phy_init error: %d\n", ret);
1986
-			return ret;
1987
-		}
1988
-
19892611 		if (bsp_priv->ops && bsp_priv->ops->set_to_sgmii)
19902612 			bsp_priv->ops->set_to_sgmii(bsp_priv);
19912613 		break;
19922614 	case PHY_INTERFACE_MODE_QSGMII:
19932615 		dev_info(dev, "init for QSGMII\n");
1994
-		ret = phy_init(bsp_priv->comphy);
1995
-		if (ret) {
1996
-			dev_err(dev, "phy_init error: %d\n", ret);
1997
-			return ret;
1998
-		}
1999
-
20002616 		if (bsp_priv->ops && bsp_priv->ops->set_to_qsgmii)
20012617 			bsp_priv->ops->set_to_qsgmii(bsp_priv);
20022618 		break;
....@@ -2010,7 +2626,6 @@
20102626 		return ret;
20112627 	}
20122628 
2013
-	pm_runtime_enable(dev);
20142629 	pm_runtime_get_sync(dev);
20152630 
20162631 	return 0;
....@@ -2018,14 +2633,7 @@
20182633 
20192634 static void rk_gmac_powerdown(struct rk_priv_data *gmac)
20202635 {
2021
-	struct device *dev = &gmac->pdev->dev;
2022
-
2023
-	if (gmac->phy_iface == PHY_INTERFACE_MODE_SGMII ||
2024
-	    gmac->phy_iface == PHY_INTERFACE_MODE_QSGMII)
2025
-		phy_exit(gmac->comphy);
2026
-
2027
-	pm_runtime_put_sync(dev);
2028
-	pm_runtime_disable(dev);
2636
+	pm_runtime_put_sync(&gmac->pdev->dev);
20292637 
20302638 	rk_gmac_phy_power_on(gmac, false);
20312639 	gmac_clk_enable(gmac, false);
....@@ -2049,8 +2657,6 @@
20492657 			bsp_priv->ops->set_rmii_speed(bsp_priv, speed);
20502658 		break;
20512659 	case PHY_INTERFACE_MODE_SGMII:
2052
-		if (bsp_priv->ops && bsp_priv->ops->set_sgmii_speed)
2053
-			bsp_priv->ops->set_sgmii_speed(bsp_priv, speed);
20542660 	case PHY_INTERFACE_MODE_QSGMII:
20552661 		break;
20562662 	default:
....@@ -2105,18 +2711,18 @@
21052711 }
21062712 EXPORT_SYMBOL(dwmac_rk_get_phy_interface);
21072713 
2108
-void __weak rk_devinfo_get_eth_mac(u8 *mac)
2109
-{
2110
-}
2111
-
2112
-void rk_get_eth_addr(void *priv, unsigned char *addr)
2714
+static unsigned char macaddr[6];
2715
+extern ssize_t at24_mac_read(unsigned char* addr);
2716
+static void rk_get_eth_addr(void *priv, unsigned char *addr)
21132717 {
21142718 	struct rk_priv_data *bsp_priv = priv;
21152719 	struct device *dev = &bsp_priv->pdev->dev;
2116
-	unsigned char ethaddr[ETH_ALEN * MAX_ETH] = {0};
2720
+	//unsigned char ethaddr[ETH_ALEN * MAX_ETH] = {0};
21172721 	int ret, id = bsp_priv->bus_id;
2722
+	//int i;
21182723 
2119
-	rk_devinfo_get_eth_mac(addr);
2724
+	printk("hw-debug:enter rk_get_eth_addr.. \n");
2725
+#if 0
21202726 	if (is_valid_ether_addr(addr))
21212727 		goto out;
21222728 
....@@ -2146,7 +2752,32 @@
21462752 	} else {
21472753 		memcpy(addr, &ethaddr[id * ETH_ALEN], ETH_ALEN);
21482754 	}
2755
+#endif
2756
+	
21492757 
2758
+	//eeprom
2759
+        	ret = at24_mac_read(macaddr);
2760
+        	if (ret > 0)
2761
+        	{
2762
+                	printk("ben %s: at24_mac_read Success!! \n", __func__);
2763
+                	memcpy(addr, macaddr, 6);
2764
+
2765
+                	if ((addr[0] == 0x68) && (addr[1] == 0xed))
2766
+                	{
2767
+                        	printk("at24_eeprom mac is valid \n", __func__);
2768
+                        	goto out;
2769
+        		}
2770
+                	else
2771
+                	{
2772
+                        	printk("at24_eeprom mac is invalid \n", __func__);
2773
+                        	addr[0] = 0x68;
2774
+                        	addr[1] = 0xed;
2775
+                        	addr[2] = 0x01;
2776
+                        	addr[3] = 0x02;
2777
+                        	addr[4] = 0x03;
2778
+                        	addr[5] = 0x04;
2779
+                	}
2780
+    		}
21502781 out:
21512782 	dev_err(dev, "%s: mac address: %pM\n", __func__, addr);
21522783 }
....@@ -2175,6 +2806,7 @@
21752806 	if (!of_device_is_compatible(pdev->dev.of_node, "snps,dwmac-4.20a"))
21762807 		plat_dat->has_gmac = true;
21772808 
2809
+	plat_dat->sph_disable = true;
21782810 	plat_dat->fix_mac_speed = rk_fix_speed;
21792811 	plat_dat->get_eth_addr = rk_get_eth_addr;
21802812 	plat_dat->integrated_phy_power = rk_integrated_phy_power;
....@@ -2284,10 +2916,22 @@
22842916 #ifdef CONFIG_CPU_RK3399
22852917 	{ .compatible = "rockchip,rk3399-gmac", .data = &rk3399_ops },
22862918 #endif
2919
+#ifdef CONFIG_CPU_RK3528
2920
+	{ .compatible = "rockchip,rk3528-gmac", .data = &rk3528_ops },
2921
+#endif
2922
+#ifdef CONFIG_CPU_RK3562
2923
+	{ .compatible = "rockchip,rk3562-gmac", .data = &rk3562_ops },
2924
+#endif
22872925 #ifdef CONFIG_CPU_RK3568
22882926 	{ .compatible = "rockchip,rk3568-gmac", .data = &rk3568_ops },
22892927 #endif
2290
-#ifdef CONFIG_CPU_RV110X
2928
+#ifdef CONFIG_CPU_RK3588
2929
+	{ .compatible = "rockchip,rk3588-gmac", .data = &rk3588_ops },
2930
+#endif
2931
+#ifdef CONFIG_CPU_RV1106
2932
+	{ .compatible = "rockchip,rv1106-gmac", .data = &rv1106_ops },
2933
+#endif
2934
+#ifdef CONFIG_CPU_RV1108
22912935 	{ .compatible = "rockchip,rv1108-gmac", .data = &rv1108_ops },
22922936 #endif
22932937 #ifdef CONFIG_CPU_RV1126
....@@ -2306,7 +2950,8 @@
23062950 		.of_match_table = rk_gmac_dwmac_match,
23072951 	},
23082952 };
2309
-module_platform_driver(rk_gmac_dwmac_driver);
2953
+//module_platform_driver(rk_gmac_dwmac_driver);
2954
+module_platform_driver1(rk_gmac_dwmac_driver);
23102955 
23112956 MODULE_AUTHOR("Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com>");
23122957 MODULE_DESCRIPTION("Rockchip RK3288 DWMAC specific glue layer");