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2024-05-10 9999e48639b3cecb08ffb37358bcba3b48161b29 
 kernel/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
....@@ -1,19 +1,10 @@
1
+// SPDX-License-Identifier: GPL-2.0-or-later
12 /**
2
- * dwmac-rk.c - Rockchip RK3288 DWMAC specific glue layer
3
+ * DOC: dwmac-rk.c - Rockchip RK3288 DWMAC specific glue layer
34  *
45  * Copyright (C) 2014 Chen-Zhi (Roger Chen)
56  *
67  * Chen-Zhi (Roger Chen)  <roger.chen@rock-chips.com>
7
- *
8
- * This program is free software; you can redistribute it and/or modify
9
- * it under the terms of the GNU General Public License as published by
10
- * the Free Software Foundation; either version 2 of the License, or
11
- * (at your option) any later version.
12
- *
13
- * This program is distributed in the hope that it will be useful,
14
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
15
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16
- * GNU General Public License for more details.
178  */
189 
1910 #include <linux/stmmac.h>
....@@ -24,6 +15,7 @@
2415 #include <linux/of_net.h>
2516 #include <linux/gpio.h>
2617 #include <linux/module.h>
18
+#include <linux/nvmem-consumer.h>
2719 #include <linux/of_gpio.h>
2820 #include <linux/of_device.h>
2921 #include <linux/platform_device.h>
....@@ -47,12 +39,14 @@
4739 	void (*set_to_qsgmii)(struct rk_priv_data *bsp_priv);
4840 	void (*set_rgmii_speed)(struct rk_priv_data *bsp_priv, int speed);
4941 	void (*set_rmii_speed)(struct rk_priv_data *bsp_priv, int speed);
50
-	void (*integrated_phy_powerup)(struct rk_priv_data *bsp_priv);
42
+	void (*set_clock_selection)(struct rk_priv_data *bsp_priv, bool input,
43
+				    bool enable);
44
+	void (*integrated_phy_power)(struct rk_priv_data *bsp_priv, bool up);
5145 };
5246 
5347 struct rk_priv_data {
5448 	struct platform_device *pdev;
55
-	int phy_iface;
49
+	phy_interface_t phy_iface;
5650 	int bus_id;
5751 	struct regulator *regulator;
5852 	bool suspended;
....@@ -73,6 +67,7 @@
7367 	struct clk *pclk_mac;
7468 	struct clk *clk_phy;
7569 	struct clk *pclk_xpcs;
70
+	struct clk *clk_xpcs_eee;
7671 
7772 	struct reset_control *phy_reset;
7873 
....@@ -80,7 +75,11 @@
8075 	int rx_delay;
8176 
8277 	struct regmap *grf;
78
+	struct regmap *php_grf;
8379 	struct regmap *xpcs;
80
+
81
+	unsigned char otp_data;
82
+	unsigned int bgs_increment;
8483 };
8584 
8685 /* XPCS */
....@@ -212,8 +211,119 @@
212211 #define GRF_CLR_BIT(nr)	(BIT(nr+16))
213212 
214213 #define DELAY_ENABLE(soc, tx, rx) \
215
-	(((tx) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \
216
-	 ((rx) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE))
214
+	((((tx) >= 0) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \
215
+	 (((rx) >= 0) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE))
216
+
217
+#define DELAY_ENABLE_BY_ID(soc, tx, rx, id) \
218
+	((((tx) >= 0) ? soc##_GMAC_TXCLK_DLY_ENABLE(id) : soc##_GMAC_TXCLK_DLY_DISABLE(id)) | \
219
+	 (((rx) >= 0) ? soc##_GMAC_RXCLK_DLY_ENABLE(id) : soc##_GMAC_RXCLK_DLY_DISABLE(id)))
220
+
221
+#define DELAY_VALUE(soc, tx, rx) \
222
+	((((tx) >= 0) ? soc##_GMAC_CLK_TX_DL_CFG(tx) : 0) | \
223
+	 (((rx) >= 0) ? soc##_GMAC_CLK_RX_DL_CFG(rx) : 0))
224
+
225
+#define GMAC_RGMII_CLK_DIV_BY_ID(soc, id, div) \
226
+		(soc##_GMAC##id##_CLK_RGMII_DIV##div)
227
+
228
+#define GMAC_RMII_CLK_DIV_BY_ID(soc, id, div) \
229
+		(soc##_GMAC##id##_CLK_RMII_DIV##div)
230
+
231
+/* Integrated EPHY */
232
+
233
+#define RK_GRF_MACPHY_CON0		0xb00
234
+#define RK_GRF_MACPHY_CON1		0xb04
235
+#define RK_GRF_MACPHY_CON2		0xb08
236
+#define RK_GRF_MACPHY_CON3		0xb0c
237
+
238
+#define RK_MACPHY_ENABLE		GRF_BIT(0)
239
+#define RK_MACPHY_DISABLE		GRF_CLR_BIT(0)
240
+#define RK_MACPHY_CFG_CLK_50M		GRF_BIT(14)
241
+#define RK_GMAC2PHY_RMII_MODE		(GRF_BIT(6) | GRF_CLR_BIT(7))
242
+#define RK_GRF_CON2_MACPHY_ID		HIWORD_UPDATE(0x1234, 0xffff, 0)
243
+#define RK_GRF_CON3_MACPHY_ID		HIWORD_UPDATE(0x35, 0x3f, 0)
244
+
245
+static void rk_gmac_integrated_ephy_powerup(struct rk_priv_data *priv)
246
+{
247
+	regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_CFG_CLK_50M);
248
+	regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_GMAC2PHY_RMII_MODE);
249
+
250
+	regmap_write(priv->grf, RK_GRF_MACPHY_CON2, RK_GRF_CON2_MACPHY_ID);
251
+	regmap_write(priv->grf, RK_GRF_MACPHY_CON3, RK_GRF_CON3_MACPHY_ID);
252
+
253
+	if (priv->phy_reset) {
254
+		/* PHY needs to be disabled before trying to reset it */
255
+		regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
256
+		if (priv->phy_reset)
257
+			reset_control_assert(priv->phy_reset);
258
+		usleep_range(10, 20);
259
+		if (priv->phy_reset)
260
+			reset_control_deassert(priv->phy_reset);
261
+		usleep_range(10, 20);
262
+		regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_ENABLE);
263
+		msleep(30);
264
+	}
265
+}
266
+
267
+static void rk_gmac_integrated_ephy_powerdown(struct rk_priv_data *priv)
268
+{
269
+	regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
270
+	if (priv->phy_reset)
271
+		reset_control_assert(priv->phy_reset);
272
+}
273
+
274
+/* Integrated FEPHY */
275
+#define RK_FEPHY_SHUTDOWN		GRF_BIT(1)
276
+#define RK_FEPHY_POWERUP		GRF_CLR_BIT(1)
277
+#define RK_FEPHY_INTERNAL_RMII_SEL	GRF_BIT(6)
278
+#define RK_FEPHY_24M_CLK_SEL		(GRF_BIT(8) | GRF_BIT(9))
279
+#define RK_FEPHY_PHY_ID			GRF_BIT(11)
280
+
281
+#define RK_FEPHY_BGS			HIWORD_UPDATE(0x0, 0xf, 0)
282
+
283
+#define RK_FEPHY_BGS_MAX		7
284
+
285
+static void rk_gmac_integrated_fephy_power(struct rk_priv_data *priv,
286
+					   unsigned int ctrl_offset,
287
+					   unsigned int bgs_offset,
288
+					   bool up)
289
+{
290
+	struct device *dev = &priv->pdev->dev;
291
+
292
+	if (IS_ERR(priv->grf) || !priv->phy_reset) {
293
+		dev_err(dev, "%s: Missing rockchip,grf or phy_reset property\n",
294
+			__func__);
295
+		return;
296
+	}
297
+
298
+	if (up) {
299
+		unsigned int bgs = priv->otp_data;
300
+
301
+		reset_control_assert(priv->phy_reset);
302
+		udelay(20);
303
+		regmap_write(priv->grf, ctrl_offset,
304
+			     RK_FEPHY_POWERUP |
305
+			     RK_FEPHY_INTERNAL_RMII_SEL |
306
+			     RK_FEPHY_24M_CLK_SEL |
307
+			     RK_FEPHY_PHY_ID);
308
+
309
+		if (bgs > (RK_FEPHY_BGS_MAX - priv->bgs_increment) &&
310
+		    bgs <= RK_FEPHY_BGS_MAX) {
311
+			bgs = HIWORD_UPDATE(RK_FEPHY_BGS_MAX, 0xf, 0);
312
+		} else {
313
+			bgs += priv->bgs_increment;
314
+			bgs &= 0xf;
315
+			bgs = HIWORD_UPDATE(bgs, 0xf, 0);
316
+		}
317
+
318
+		regmap_write(priv->grf, bgs_offset, bgs);
319
+		usleep_range(10 * 1000, 12 * 1000);
320
+		reset_control_deassert(priv->phy_reset);
321
+		usleep_range(50 * 1000, 60 * 1000);
322
+	} else {
323
+		regmap_write(priv->grf, ctrl_offset,
324
+			     RK_FEPHY_SHUTDOWN);
325
+	}
326
+}
217327 
218328 #define PX30_GRF_GMAC_CON1		0x0904
219329 
....@@ -306,12 +416,10 @@
306416 
307417 	regmap_write(bsp_priv->grf, RK1808_GRF_GMAC_CON1,
308418 		     RK1808_GMAC_PHY_INTF_SEL_RGMII |
309
-		     RK1808_GMAC_RXCLK_DLY_ENABLE |
310
-		     RK1808_GMAC_TXCLK_DLY_ENABLE);
419
+		     DELAY_ENABLE(RK1808, tx_delay, rx_delay));
311420 
312421 	regmap_write(bsp_priv->grf, RK1808_GRF_GMAC_CON0,
313
-		     RK1808_GMAC_CLK_RX_DL_CFG(rx_delay) |
314
-		     RK1808_GMAC_CLK_TX_DL_CFG(tx_delay));
422
+		     DELAY_VALUE(RK1808, tx_delay, rx_delay));
315423 }
316424 
317425 static void rk1808_set_to_rmii(struct rk_priv_data *bsp_priv)
....@@ -439,8 +547,7 @@
439547 		     RK3128_GMAC_RMII_MODE_CLR);
440548 	regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON0,
441549 		     DELAY_ENABLE(RK3128, tx_delay, rx_delay) |
442
-		     RK3128_GMAC_CLK_RX_DL_CFG(rx_delay) |
443
-		     RK3128_GMAC_CLK_TX_DL_CFG(tx_delay));
550
+		     DELAY_VALUE(RK3128, tx_delay, rx_delay));
444551 }
445552 
446553 static void rk3128_set_to_rmii(struct rk_priv_data *bsp_priv)
....@@ -556,8 +663,7 @@
556663 		     DELAY_ENABLE(RK3228, tx_delay, rx_delay));
557664 
558665 	regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON0,
559
-		     RK3228_GMAC_CLK_RX_DL_CFG(rx_delay) |
560
-		     RK3228_GMAC_CLK_TX_DL_CFG(tx_delay));
666
+		     DELAY_VALUE(RK3128, tx_delay, rx_delay));
561667 }
562668 
563669 static void rk3228_set_to_rmii(struct rk_priv_data *bsp_priv)
....@@ -620,10 +726,16 @@
620726 		dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
621727 }
622728 
623
-static void rk3228_integrated_phy_powerup(struct rk_priv_data *priv)
729
+static void rk3228_integrated_phy_power(struct rk_priv_data *priv, bool up)
624730 {
625
-	regmap_write(priv->grf, RK3228_GRF_CON_MUX,
626
-		     RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY);
731
+	if (up) {
732
+		regmap_write(priv->grf, RK3228_GRF_CON_MUX,
733
+			     RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY);
734
+
735
+		rk_gmac_integrated_ephy_powerup(priv);
736
+	} else {
737
+		rk_gmac_integrated_ephy_powerdown(priv);
738
+	}
627739 }
628740 
629741 static const struct rk_gmac_ops rk3228_ops = {
....@@ -631,7 +743,7 @@
631743 	.set_to_rmii = rk3228_set_to_rmii,
632744 	.set_rgmii_speed = rk3228_set_rgmii_speed,
633745 	.set_rmii_speed = rk3228_set_rmii_speed,
634
-	.integrated_phy_powerup =  rk3228_integrated_phy_powerup,
746
+	.integrated_phy_power =  rk3228_integrated_phy_power,
635747 };
636748 
637749 #define RK3288_GRF_SOC_CON1	0x0248
....@@ -677,8 +789,7 @@
677789 		     RK3288_GMAC_RMII_MODE_CLR);
678790 	regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON3,
679791 		     DELAY_ENABLE(RK3288, tx_delay, rx_delay) |
680
-		     RK3288_GMAC_CLK_RX_DL_CFG(rx_delay) |
681
-		     RK3288_GMAC_CLK_TX_DL_CFG(tx_delay));
792
+		     DELAY_VALUE(RK3288, tx_delay, rx_delay));
682793 }
683794 
684795 static void rk3288_set_to_rmii(struct rk_priv_data *bsp_priv)
....@@ -849,12 +960,10 @@
849960 	regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
850961 		     RK3328_GMAC_PHY_INTF_SEL_RGMII |
851962 		     RK3328_GMAC_RMII_MODE_CLR |
852
-		     RK3328_GMAC_RXCLK_DLY_ENABLE |
853
-		     RK3328_GMAC_TXCLK_DLY_ENABLE);
963
+		     DELAY_ENABLE(RK3328, tx_delay, rx_delay));
854964 
855965 	regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON0,
856
-		     RK3328_GMAC_CLK_RX_DL_CFG(rx_delay) |
857
-		     RK3328_GMAC_CLK_TX_DL_CFG(tx_delay));
966
+		     DELAY_VALUE(RK3328, tx_delay, rx_delay));
858967 }
859968 
860969 static void rk3328_set_to_rmii(struct rk_priv_data *bsp_priv)
....@@ -922,10 +1031,16 @@
9221031 		dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
9231032 }
9241033 
925
-static void rk3328_integrated_phy_powerup(struct rk_priv_data *priv)
1034
+static void rk3328_integrated_phy_power(struct rk_priv_data *priv, bool up)
9261035 {
927
-	regmap_write(priv->grf, RK3328_GRF_MACPHY_CON1,
928
-		     RK3328_MACPHY_RMII_MODE);
1036
+	if (up) {
1037
+		regmap_write(priv->grf, RK3328_GRF_MACPHY_CON1,
1038
+			     RK3328_MACPHY_RMII_MODE);
1039
+
1040
+		rk_gmac_integrated_ephy_powerup(priv);
1041
+	} else {
1042
+		rk_gmac_integrated_ephy_powerdown(priv);
1043
+	}
9291044 }
9301045 
9311046 static const struct rk_gmac_ops rk3328_ops = {
....@@ -933,7 +1048,7 @@
9331048 	.set_to_rmii = rk3328_set_to_rmii,
9341049 	.set_rgmii_speed = rk3328_set_rgmii_speed,
9351050 	.set_rmii_speed = rk3328_set_rmii_speed,
936
-	.integrated_phy_powerup =  rk3328_integrated_phy_powerup,
1051
+	.integrated_phy_power =  rk3328_integrated_phy_power,
9371052 };
9381053 
9391054 #define RK3366_GRF_SOC_CON6	0x0418
....@@ -979,8 +1094,7 @@
9791094 		     RK3366_GMAC_RMII_MODE_CLR);
9801095 	regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON7,
9811096 		     DELAY_ENABLE(RK3366, tx_delay, rx_delay) |
982
-		     RK3366_GMAC_CLK_RX_DL_CFG(rx_delay) |
983
-		     RK3366_GMAC_CLK_TX_DL_CFG(tx_delay));
1097
+		     DELAY_VALUE(RK3366, tx_delay, rx_delay));
9841098 }
9851099 
9861100 static void rk3366_set_to_rmii(struct rk_priv_data *bsp_priv)
....@@ -1090,8 +1204,7 @@
10901204 		     RK3368_GMAC_RMII_MODE_CLR);
10911205 	regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON16,
10921206 		     DELAY_ENABLE(RK3368, tx_delay, rx_delay) |
1093
-		     RK3368_GMAC_CLK_RX_DL_CFG(rx_delay) |
1094
-		     RK3368_GMAC_CLK_TX_DL_CFG(tx_delay));
1207
+		     DELAY_VALUE(RK3368, tx_delay, rx_delay));
10951208 }
10961209 
10971210 static void rk3368_set_to_rmii(struct rk_priv_data *bsp_priv)
....@@ -1201,8 +1314,7 @@
12011314 		     RK3399_GMAC_RMII_MODE_CLR);
12021315 	regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON6,
12031316 		     DELAY_ENABLE(RK3399, tx_delay, rx_delay) |
1204
-		     RK3399_GMAC_CLK_RX_DL_CFG(rx_delay) |
1205
-		     RK3399_GMAC_CLK_TX_DL_CFG(tx_delay));
1317
+		     DELAY_VALUE(RK3399, tx_delay, rx_delay));
12061318 }
12071319 
12081320 static void rk3399_set_to_rmii(struct rk_priv_data *bsp_priv)
....@@ -1267,6 +1379,361 @@
12671379 	.set_to_rmii = rk3399_set_to_rmii,
12681380 	.set_rgmii_speed = rk3399_set_rgmii_speed,
12691381 	.set_rmii_speed = rk3399_set_rmii_speed,
1382
+};
1383
+
1384
+#define RK3528_VO_GRF_GMAC_CON		0X60018
1385
+#define RK3528_VPU_GRF_GMAC_CON5	0X40018
1386
+#define RK3528_VPU_GRF_GMAC_CON6	0X4001c
1387
+
1388
+#define RK3528_GMAC_RXCLK_DLY_ENABLE	GRF_BIT(15)
1389
+#define RK3528_GMAC_RXCLK_DLY_DISABLE	GRF_CLR_BIT(15)
1390
+#define RK3528_GMAC_TXCLK_DLY_ENABLE	GRF_BIT(14)
1391
+#define RK3528_GMAC_TXCLK_DLY_DISABLE	GRF_CLR_BIT(14)
1392
+
1393
+#define RK3528_GMAC_CLK_RX_DL_CFG(val)	HIWORD_UPDATE(val, 0xFF, 8)
1394
+#define RK3528_GMAC_CLK_TX_DL_CFG(val)	HIWORD_UPDATE(val, 0xFF, 0)
1395
+
1396
+#define RK3528_GMAC0_PHY_INTF_SEL_RMII	GRF_BIT(1)
1397
+#define RK3528_GMAC1_PHY_INTF_SEL_RGMII	GRF_CLR_BIT(8)
1398
+#define RK3528_GMAC1_PHY_INTF_SEL_RMII	GRF_BIT(8)
1399
+
1400
+#define RK3528_GMAC1_CLK_SELET_CRU	GRF_CLR_BIT(12)
1401
+#define RK3528_GMAC1_CLK_SELET_IO	GRF_BIT(12)
1402
+
1403
+#define RK3528_GMAC0_CLK_RMII_DIV2	GRF_BIT(3)
1404
+#define RK3528_GMAC0_CLK_RMII_DIV20	GRF_CLR_BIT(3)
1405
+#define RK3528_GMAC1_CLK_RMII_DIV2	GRF_BIT(10)
1406
+#define RK3528_GMAC1_CLK_RMII_DIV20	GRF_CLR_BIT(10)
1407
+
1408
+#define RK3528_GMAC1_CLK_RGMII_DIV1		\
1409
+			(GRF_CLR_BIT(11) | GRF_CLR_BIT(10))
1410
+#define RK3528_GMAC1_CLK_RGMII_DIV5		\
1411
+			(GRF_BIT(11) | GRF_BIT(10))
1412
+#define RK3528_GMAC1_CLK_RGMII_DIV50		\
1413
+			(GRF_BIT(11) | GRF_CLR_BIT(10))
1414
+
1415
+#define RK3528_GMAC0_CLK_RMII_GATE	GRF_BIT(2)
1416
+#define RK3528_GMAC0_CLK_RMII_NOGATE	GRF_CLR_BIT(2)
1417
+#define RK3528_GMAC1_CLK_RMII_GATE	GRF_BIT(9)
1418
+#define RK3528_GMAC1_CLK_RMII_NOGATE	GRF_CLR_BIT(9)
1419
+
1420
+#define RK3528_VO_GRF_MACPHY_CON0		0X6001c
1421
+#define RK3528_VO_GRF_MACPHY_CON1		0X60020
1422
+
1423
+static void rk3528_set_to_rgmii(struct rk_priv_data *bsp_priv,
1424
+				int tx_delay, int rx_delay)
1425
+{
1426
+	struct device *dev = &bsp_priv->pdev->dev;
1427
+
1428
+	if (IS_ERR(bsp_priv->grf)) {
1429
+		dev_err(dev, "Missing rockchip,grf property\n");
1430
+		return;
1431
+	}
1432
+
1433
+	regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,
1434
+		     RK3528_GMAC1_PHY_INTF_SEL_RGMII);
1435
+
1436
+	regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,
1437
+		     DELAY_ENABLE(RK3528, tx_delay, rx_delay));
1438
+
1439
+	regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON6,
1440
+		     DELAY_VALUE(RK3528, tx_delay, rx_delay));
1441
+}
1442
+
1443
+static void rk3528_set_to_rmii(struct rk_priv_data *bsp_priv)
1444
+{
1445
+	struct device *dev = &bsp_priv->pdev->dev;
1446
+	unsigned int id = bsp_priv->bus_id;
1447
+
1448
+	if (IS_ERR(bsp_priv->grf)) {
1449
+		dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
1450
+		return;
1451
+	}
1452
+
1453
+	if (id == 1)
1454
+		regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,
1455
+			     RK3528_GMAC1_PHY_INTF_SEL_RMII);
1456
+	else
1457
+		regmap_write(bsp_priv->grf, RK3528_VO_GRF_GMAC_CON,
1458
+			     RK3528_GMAC0_PHY_INTF_SEL_RMII |
1459
+			     RK3528_GMAC0_CLK_RMII_DIV2);
1460
+}
1461
+
1462
+static void rk3528_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
1463
+{
1464
+	struct device *dev = &bsp_priv->pdev->dev;
1465
+	unsigned int val = 0;
1466
+
1467
+	switch (speed) {
1468
+	case 10:
1469
+		val = RK3528_GMAC1_CLK_RGMII_DIV50;
1470
+		break;
1471
+	case 100:
1472
+		val = RK3528_GMAC1_CLK_RGMII_DIV5;
1473
+		break;
1474
+	case 1000:
1475
+		val = RK3528_GMAC1_CLK_RGMII_DIV1;
1476
+		break;
1477
+	default:
1478
+		goto err;
1479
+	}
1480
+
1481
+	regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, val);
1482
+	return;
1483
+err:
1484
+	dev_err(dev, "unknown RGMII speed value for GMAC speed=%d", speed);
1485
+}
1486
+
1487
+static void rk3528_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
1488
+{
1489
+	struct device *dev = &bsp_priv->pdev->dev;
1490
+	unsigned int val, offset, id = bsp_priv->bus_id;
1491
+
1492
+	switch (speed) {
1493
+	case 10:
1494
+		val = (id == 1) ? RK3528_GMAC1_CLK_RMII_DIV20 :
1495
+				  RK3528_GMAC0_CLK_RMII_DIV20;
1496
+		break;
1497
+	case 100:
1498
+		val = (id == 1) ? RK3528_GMAC1_CLK_RMII_DIV2 :
1499
+				  RK3528_GMAC0_CLK_RMII_DIV2;
1500
+		break;
1501
+	default:
1502
+		goto err;
1503
+	}
1504
+
1505
+	offset = (id == 1) ? RK3528_VPU_GRF_GMAC_CON5 : RK3528_VO_GRF_GMAC_CON;
1506
+	regmap_write(bsp_priv->grf, offset, val);
1507
+
1508
+	return;
1509
+err:
1510
+	dev_err(dev, "unknown RMII speed value for GMAC speed=%d", speed);
1511
+}
1512
+
1513
+static void rk3528_set_clock_selection(struct rk_priv_data *bsp_priv,
1514
+				       bool input, bool enable)
1515
+{
1516
+	unsigned int value, id = bsp_priv->bus_id;
1517
+
1518
+	if (id == 1) {
1519
+		value = input ? RK3528_GMAC1_CLK_SELET_IO :
1520
+				RK3528_GMAC1_CLK_SELET_CRU;
1521
+		value |= enable ? RK3528_GMAC1_CLK_RMII_NOGATE :
1522
+				  RK3528_GMAC1_CLK_RMII_GATE;
1523
+		regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, value);
1524
+	} else {
1525
+		value = enable ? RK3528_GMAC0_CLK_RMII_NOGATE :
1526
+				 RK3528_GMAC0_CLK_RMII_GATE;
1527
+		regmap_write(bsp_priv->grf, RK3528_VO_GRF_GMAC_CON, value);
1528
+	}
1529
+}
1530
+
1531
+static void rk3528_integrated_sphy_power(struct rk_priv_data *priv, bool up)
1532
+{
1533
+	rk_gmac_integrated_fephy_power(priv, RK3528_VO_GRF_MACPHY_CON0,
1534
+				       RK3528_VO_GRF_MACPHY_CON1, up);
1535
+}
1536
+
1537
+static const struct rk_gmac_ops rk3528_ops = {
1538
+	.set_to_rgmii = rk3528_set_to_rgmii,
1539
+	.set_to_rmii = rk3528_set_to_rmii,
1540
+	.set_rgmii_speed = rk3528_set_rgmii_speed,
1541
+	.set_rmii_speed = rk3528_set_rmii_speed,
1542
+	.set_clock_selection = rk3528_set_clock_selection,
1543
+	.integrated_phy_power = rk3528_integrated_sphy_power,
1544
+};
1545
+
1546
+/* sys_grf */
1547
+#define RK3562_GRF_SYS_SOC_CON0			0X0400
1548
+#define RK3562_GRF_SYS_SOC_CON1			0X0404
1549
+
1550
+#define RK3562_GMAC0_CLK_RMII_MODE		GRF_BIT(5)
1551
+#define RK3562_GMAC0_CLK_RGMII_MODE		GRF_CLR_BIT(5)
1552
+
1553
+#define RK3562_GMAC0_CLK_RMII_GATE		GRF_BIT(6)
1554
+#define RK3562_GMAC0_CLK_RMII_NOGATE		GRF_CLR_BIT(6)
1555
+
1556
+#define RK3562_GMAC0_CLK_RMII_DIV2		GRF_BIT(7)
1557
+#define RK3562_GMAC0_CLK_RMII_DIV20		GRF_CLR_BIT(7)
1558
+
1559
+#define RK3562_GMAC0_CLK_RGMII_DIV1		\
1560
+				(GRF_CLR_BIT(7) | GRF_CLR_BIT(8))
1561
+#define RK3562_GMAC0_CLK_RGMII_DIV5		\
1562
+				(GRF_BIT(7) | GRF_BIT(8))
1563
+#define RK3562_GMAC0_CLK_RGMII_DIV50		\
1564
+				(GRF_CLR_BIT(7) | GRF_BIT(8))
1565
+
1566
+#define RK3562_GMAC0_CLK_RMII_DIV2		GRF_BIT(7)
1567
+#define RK3562_GMAC0_CLK_RMII_DIV20		GRF_CLR_BIT(7)
1568
+
1569
+#define RK3562_GMAC0_CLK_SELET_CRU		GRF_CLR_BIT(9)
1570
+#define RK3562_GMAC0_CLK_SELET_IO		GRF_BIT(9)
1571
+
1572
+#define RK3562_GMAC1_CLK_RMII_GATE		GRF_BIT(12)
1573
+#define RK3562_GMAC1_CLK_RMII_NOGATE		GRF_CLR_BIT(12)
1574
+
1575
+#define RK3562_GMAC1_CLK_RMII_DIV2		GRF_BIT(13)
1576
+#define RK3562_GMAC1_CLK_RMII_DIV20		GRF_CLR_BIT(13)
1577
+
1578
+#define RK3562_GMAC1_RMII_SPEED100		GRF_BIT(11)
1579
+#define RK3562_GMAC1_RMII_SPEED10		GRF_CLR_BIT(11)
1580
+
1581
+#define RK3562_GMAC1_CLK_SELET_CRU		GRF_CLR_BIT(15)
1582
+#define RK3562_GMAC1_CLK_SELET_IO		GRF_BIT(15)
1583
+
1584
+/* ioc_grf */
1585
+#define RK3562_GRF_IOC_GMAC_IOFUNC0_CON0	0X10400
1586
+#define RK3562_GRF_IOC_GMAC_IOFUNC0_CON1	0X10404
1587
+#define RK3562_GRF_IOC_GMAC_IOFUNC1_CON0	0X00400
1588
+#define RK3562_GRF_IOC_GMAC_IOFUNC1_CON1	0X00404
1589
+
1590
+#define RK3562_GMAC_RXCLK_DLY_ENABLE		GRF_BIT(1)
1591
+#define RK3562_GMAC_RXCLK_DLY_DISABLE		GRF_CLR_BIT(1)
1592
+#define RK3562_GMAC_TXCLK_DLY_ENABLE		GRF_BIT(0)
1593
+#define RK3562_GMAC_TXCLK_DLY_DISABLE		GRF_CLR_BIT(0)
1594
+
1595
+#define RK3562_GMAC_CLK_RX_DL_CFG(val)		HIWORD_UPDATE(val, 0xFF, 8)
1596
+#define RK3562_GMAC_CLK_TX_DL_CFG(val)		HIWORD_UPDATE(val, 0xFF, 0)
1597
+
1598
+#define RK3562_GMAC0_IO_EXTCLK_SELET_CRU	GRF_CLR_BIT(2)
1599
+#define RK3562_GMAC0_IO_EXTCLK_SELET_IO		GRF_BIT(2)
1600
+
1601
+#define RK3562_GMAC1_IO_EXTCLK_SELET_CRU	GRF_CLR_BIT(3)
1602
+#define RK3562_GMAC1_IO_EXTCLK_SELET_IO		GRF_BIT(3)
1603
+
1604
+static void rk3562_set_to_rgmii(struct rk_priv_data *bsp_priv,
1605
+				int tx_delay, int rx_delay)
1606
+{
1607
+	struct device *dev = &bsp_priv->pdev->dev;
1608
+
1609
+	if (IS_ERR(bsp_priv->grf) || IS_ERR(bsp_priv->php_grf)) {
1610
+		dev_err(dev, "Missing rockchip,grf or rockchip,php_grf property\n");
1611
+		return;
1612
+	}
1613
+
1614
+	if (bsp_priv->bus_id > 0)
1615
+		return;
1616
+
1617
+	regmap_write(bsp_priv->grf, RK3562_GRF_SYS_SOC_CON0,
1618
+		     RK3562_GMAC0_CLK_RGMII_MODE);
1619
+
1620
+	regmap_write(bsp_priv->php_grf, RK3562_GRF_IOC_GMAC_IOFUNC0_CON1,
1621
+		     DELAY_ENABLE(RK3562, tx_delay, rx_delay));
1622
+	regmap_write(bsp_priv->php_grf, RK3562_GRF_IOC_GMAC_IOFUNC0_CON0,
1623
+		     DELAY_VALUE(RK3562, tx_delay, rx_delay));
1624
+
1625
+	regmap_write(bsp_priv->php_grf, RK3562_GRF_IOC_GMAC_IOFUNC1_CON1,
1626
+		     DELAY_ENABLE(RK3562, tx_delay, rx_delay));
1627
+	regmap_write(bsp_priv->php_grf, RK3562_GRF_IOC_GMAC_IOFUNC1_CON0,
1628
+		     DELAY_VALUE(RK3562, tx_delay, rx_delay));
1629
+}
1630
+
1631
+static void rk3562_set_to_rmii(struct rk_priv_data *bsp_priv)
1632
+{
1633
+	struct device *dev = &bsp_priv->pdev->dev;
1634
+
1635
+	if (IS_ERR(bsp_priv->grf)) {
1636
+		dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
1637
+		return;
1638
+	}
1639
+
1640
+	if (!bsp_priv->bus_id)
1641
+		regmap_write(bsp_priv->grf, RK3562_GRF_SYS_SOC_CON0,
1642
+			     RK3562_GMAC0_CLK_RMII_MODE);
1643
+}
1644
+
1645
+static void rk3562_set_gmac_speed(struct rk_priv_data *bsp_priv, int speed)
1646
+{
1647
+	struct device *dev = &bsp_priv->pdev->dev;
1648
+	unsigned int val = 0, offset, id = bsp_priv->bus_id;
1649
+
1650
+	switch (speed) {
1651
+	case 10:
1652
+		if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) {
1653
+			if (id > 0) {
1654
+				val = GMAC_RMII_CLK_DIV_BY_ID(RK3562, 1, 20);
1655
+				regmap_write(bsp_priv->grf, RK3562_GRF_SYS_SOC_CON0,
1656
+					     RK3562_GMAC1_RMII_SPEED10);
1657
+			} else {
1658
+				val = GMAC_RMII_CLK_DIV_BY_ID(RK3562, 0, 20);
1659
+			}
1660
+		} else {
1661
+			val = GMAC_RGMII_CLK_DIV_BY_ID(RK3562, 0, 50);
1662
+		}
1663
+		break;
1664
+	case 100:
1665
+		if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) {
1666
+			if (id > 0) {
1667
+				val = GMAC_RMII_CLK_DIV_BY_ID(RK3562, 1, 2);
1668
+				regmap_write(bsp_priv->grf, RK3562_GRF_SYS_SOC_CON0,
1669
+					     RK3562_GMAC1_RMII_SPEED100);
1670
+			} else {
1671
+				val = GMAC_RMII_CLK_DIV_BY_ID(RK3562, 0, 2);
1672
+			}
1673
+		} else {
1674
+			val = GMAC_RGMII_CLK_DIV_BY_ID(RK3562, 0, 5);
1675
+		}
1676
+		break;
1677
+	case 1000:
1678
+		if (bsp_priv->phy_iface != PHY_INTERFACE_MODE_RMII)
1679
+			val = GMAC_RGMII_CLK_DIV_BY_ID(RK3562, 0, 1);
1680
+		else
1681
+			goto err;
1682
+		break;
1683
+	default:
1684
+		goto err;
1685
+	}
1686
+
1687
+	offset = (bsp_priv->bus_id > 0) ? RK3562_GRF_SYS_SOC_CON1 :
1688
+					  RK3562_GRF_SYS_SOC_CON0;
1689
+	regmap_write(bsp_priv->grf, offset, val);
1690
+
1691
+	return;
1692
+err:
1693
+	dev_err(dev, "unknown speed value for GMAC speed=%d", speed);
1694
+}
1695
+
1696
+static void rk3562_set_clock_selection(struct rk_priv_data *bsp_priv, bool input,
1697
+				       bool enable)
1698
+{
1699
+	struct device *dev = &bsp_priv->pdev->dev;
1700
+	unsigned int value;
1701
+
1702
+	if (IS_ERR(bsp_priv->grf) || IS_ERR(bsp_priv->php_grf)) {
1703
+		dev_err(dev, "Missing rockchip,grf or rockchip,php_grf property\n");
1704
+		return;
1705
+	}
1706
+
1707
+	if (!bsp_priv->bus_id) {
1708
+		value = input ? RK3562_GMAC0_CLK_SELET_IO :
1709
+				RK3562_GMAC0_CLK_SELET_CRU;
1710
+		value |= enable ? RK3562_GMAC0_CLK_RMII_NOGATE :
1711
+				  RK3562_GMAC0_CLK_RMII_GATE;
1712
+		regmap_write(bsp_priv->grf, RK3562_GRF_SYS_SOC_CON0, value);
1713
+
1714
+		value = input ? RK3562_GMAC0_IO_EXTCLK_SELET_IO :
1715
+				RK3562_GMAC0_IO_EXTCLK_SELET_CRU;
1716
+		regmap_write(bsp_priv->php_grf, RK3562_GRF_IOC_GMAC_IOFUNC0_CON1, value);
1717
+		regmap_write(bsp_priv->php_grf, RK3562_GRF_IOC_GMAC_IOFUNC1_CON1, value);
1718
+	} else {
1719
+		value = input ? RK3562_GMAC1_CLK_SELET_IO :
1720
+				RK3562_GMAC1_CLK_SELET_CRU;
1721
+		value |= enable ? RK3562_GMAC1_CLK_RMII_NOGATE :
1722
+				 RK3562_GMAC1_CLK_RMII_GATE;
1723
+		regmap_write(bsp_priv->grf, RK3562_GRF_SYS_SOC_CON1, value);
1724
+
1725
+		value = input ? RK3562_GMAC1_IO_EXTCLK_SELET_IO :
1726
+				RK3562_GMAC1_IO_EXTCLK_SELET_CRU;
1727
+		regmap_write(bsp_priv->php_grf, RK3562_GRF_IOC_GMAC_IOFUNC1_CON1, value);
1728
+	}
1729
+}
1730
+
1731
+static const struct rk_gmac_ops rk3562_ops = {
1732
+	.set_to_rgmii = rk3562_set_to_rgmii,
1733
+	.set_to_rmii = rk3562_set_to_rmii,
1734
+	.set_rgmii_speed = rk3562_set_gmac_speed,
1735
+	.set_rmii_speed = rk3562_set_gmac_speed,
1736
+	.set_clock_selection = rk3562_set_clock_selection,
12701737 };
12711738 
12721739 #define RK3568_GRF_GMAC0_CON0		0X0380
....@@ -1349,12 +1816,10 @@
13491816 
13501817 	regmap_write(bsp_priv->grf, offset_con1,
13511818 		     RK3568_GMAC_PHY_INTF_SEL_RGMII |
1352
-		     RK3568_GMAC_RXCLK_DLY_ENABLE |
1353
-		     RK3568_GMAC_TXCLK_DLY_ENABLE);
1819
+		     DELAY_ENABLE(RK3568, tx_delay, rx_delay));
13541820 
13551821 	regmap_write(bsp_priv->grf, offset_con0,
1356
-		     RK3568_GMAC_CLK_RX_DL_CFG(rx_delay) |
1357
-		     RK3568_GMAC_CLK_TX_DL_CFG(tx_delay));
1822
+		     DELAY_VALUE(RK3568, tx_delay, rx_delay));
13581823 }
13591824 
13601825 static void rk3568_set_to_rmii(struct rk_priv_data *bsp_priv)
....@@ -1407,6 +1872,202 @@
14071872 	.set_to_qsgmii = rk3568_set_to_qsgmii,
14081873 	.set_rgmii_speed = rk3568_set_gmac_speed,
14091874 	.set_rmii_speed = rk3568_set_gmac_speed,
1875
+};
1876
+
1877
+/* sys_grf */
1878
+#define RK3588_GRF_GMAC_CON7			0X031c
1879
+#define RK3588_GRF_GMAC_CON8			0X0320
1880
+#define RK3588_GRF_GMAC_CON9			0X0324
1881
+
1882
+#define RK3588_GMAC_RXCLK_DLY_ENABLE(id)	GRF_BIT(2 * (id) + 3)
1883
+#define RK3588_GMAC_RXCLK_DLY_DISABLE(id)	GRF_CLR_BIT(2 * (id) + 3)
1884
+#define RK3588_GMAC_TXCLK_DLY_ENABLE(id)	GRF_BIT(2 * (id) + 2)
1885
+#define RK3588_GMAC_TXCLK_DLY_DISABLE(id)	GRF_CLR_BIT(2 * (id) + 2)
1886
+
1887
+#define RK3588_GMAC_CLK_RX_DL_CFG(val)		HIWORD_UPDATE(val, 0xFF, 8)
1888
+#define RK3588_GMAC_CLK_TX_DL_CFG(val)		HIWORD_UPDATE(val, 0xFF, 0)
1889
+
1890
+/* php_grf */
1891
+#define RK3588_GRF_GMAC_CON0			0X0008
1892
+#define RK3588_GRF_CLK_CON1			0X0070
1893
+
1894
+#define RK3588_GMAC_PHY_INTF_SEL_RGMII(id)	\
1895
+	(GRF_BIT(3 + (id) * 6) | GRF_CLR_BIT(4 + (id) * 6) | GRF_CLR_BIT(5 + (id) * 6))
1896
+#define RK3588_GMAC_PHY_INTF_SEL_RMII(id)	\
1897
+	(GRF_CLR_BIT(3 + (id) * 6) | GRF_CLR_BIT(4 + (id) * 6) | GRF_BIT(5 + (id) * 6))
1898
+
1899
+#define RK3588_GMAC_CLK_RMII_MODE(id)		GRF_BIT(5 * (id))
1900
+#define RK3588_GMAC_CLK_RGMII_MODE(id)		GRF_CLR_BIT(5 * (id))
1901
+
1902
+#define RK3588_GMAC_CLK_SELET_CRU(id)		GRF_BIT(5 * (id) + 4)
1903
+#define RK3588_GMAC_CLK_SELET_IO(id)		GRF_CLR_BIT(5 * (id) + 4)
1904
+
1905
+#define RK3588_GMA_CLK_RMII_DIV2(id)		GRF_BIT(5 * (id) + 2)
1906
+#define RK3588_GMA_CLK_RMII_DIV20(id)		GRF_CLR_BIT(5 * (id) + 2)
1907
+
1908
+#define RK3588_GMAC_CLK_RGMII_DIV1(id)		\
1909
+			(GRF_CLR_BIT(5 * (id) + 2) | GRF_CLR_BIT(5 * (id) + 3))
1910
+#define RK3588_GMAC_CLK_RGMII_DIV5(id)		\
1911
+			(GRF_BIT(5 * (id) + 2) | GRF_BIT(5 * (id) + 3))
1912
+#define RK3588_GMAC_CLK_RGMII_DIV50(id)		\
1913
+			(GRF_CLR_BIT(5 * (id) + 2) | GRF_BIT(5 * (id) + 3))
1914
+
1915
+#define RK3588_GMAC_CLK_RMII_GATE(id)		GRF_BIT(5 * (id) + 1)
1916
+#define RK3588_GMAC_CLK_RMII_NOGATE(id)		GRF_CLR_BIT(5 * (id) + 1)
1917
+
1918
+static void rk3588_set_to_rgmii(struct rk_priv_data *bsp_priv,
1919
+				int tx_delay, int rx_delay)
1920
+{
1921
+	struct device *dev = &bsp_priv->pdev->dev;
1922
+	u32 offset_con, id = bsp_priv->bus_id;
1923
+
1924
+	if (IS_ERR(bsp_priv->grf) || IS_ERR(bsp_priv->php_grf)) {
1925
+		dev_err(dev, "Missing rockchip,grf or rockchip,php_grf property\n");
1926
+		return;
1927
+	}
1928
+
1929
+	offset_con = bsp_priv->bus_id == 1 ? RK3588_GRF_GMAC_CON9 :
1930
+					     RK3588_GRF_GMAC_CON8;
1931
+
1932
+	regmap_write(bsp_priv->php_grf, RK3588_GRF_GMAC_CON0,
1933
+		     RK3588_GMAC_PHY_INTF_SEL_RGMII(id));
1934
+
1935
+	regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1,
1936
+		     RK3588_GMAC_CLK_RGMII_MODE(id));
1937
+
1938
+	regmap_write(bsp_priv->grf, RK3588_GRF_GMAC_CON7,
1939
+		     DELAY_ENABLE_BY_ID(RK3588, tx_delay, rx_delay, id));
1940
+
1941
+	regmap_write(bsp_priv->grf, offset_con,
1942
+		     DELAY_VALUE(RK3588, tx_delay, rx_delay));
1943
+}
1944
+
1945
+static void rk3588_set_to_rmii(struct rk_priv_data *bsp_priv)
1946
+{
1947
+	struct device *dev = &bsp_priv->pdev->dev;
1948
+
1949
+	if (IS_ERR(bsp_priv->php_grf)) {
1950
+		dev_err(dev, "%s: Missing rockchip,php_grf property\n", __func__);
1951
+		return;
1952
+	}
1953
+
1954
+	regmap_write(bsp_priv->php_grf, RK3588_GRF_GMAC_CON0,
1955
+		     RK3588_GMAC_PHY_INTF_SEL_RMII(bsp_priv->bus_id));
1956
+
1957
+	regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1,
1958
+		     RK3588_GMAC_CLK_RMII_MODE(bsp_priv->bus_id));
1959
+}
1960
+
1961
+static void rk3588_set_gmac_speed(struct rk_priv_data *bsp_priv, int speed)
1962
+{
1963
+	struct device *dev = &bsp_priv->pdev->dev;
1964
+	unsigned int val = 0, id = bsp_priv->bus_id;
1965
+
1966
+	switch (speed) {
1967
+	case 10:
1968
+		if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII)
1969
+			val = RK3588_GMA_CLK_RMII_DIV20(id);
1970
+		else
1971
+			val = RK3588_GMAC_CLK_RGMII_DIV50(id);
1972
+		break;
1973
+	case 100:
1974
+		if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII)
1975
+			val = RK3588_GMA_CLK_RMII_DIV2(id);
1976
+		else
1977
+			val = RK3588_GMAC_CLK_RGMII_DIV5(id);
1978
+		break;
1979
+	case 1000:
1980
+		if (bsp_priv->phy_iface != PHY_INTERFACE_MODE_RMII)
1981
+			val = RK3588_GMAC_CLK_RGMII_DIV1(id);
1982
+		else
1983
+			goto err;
1984
+		break;
1985
+	default:
1986
+		goto err;
1987
+	}
1988
+
1989
+	regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1, val);
1990
+
1991
+	return;
1992
+err:
1993
+	dev_err(dev, "unknown speed value for GMAC speed=%d", speed);
1994
+}
1995
+
1996
+static void rk3588_set_clock_selection(struct rk_priv_data *bsp_priv, bool input,
1997
+				       bool enable)
1998
+{
1999
+	unsigned int val = input ? RK3588_GMAC_CLK_SELET_IO(bsp_priv->bus_id) :
2000
+				   RK3588_GMAC_CLK_SELET_CRU(bsp_priv->bus_id);
2001
+
2002
+	val |= enable ? RK3588_GMAC_CLK_RMII_NOGATE(bsp_priv->bus_id) :
2003
+			RK3588_GMAC_CLK_RMII_GATE(bsp_priv->bus_id);
2004
+
2005
+	regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1, val);
2006
+}
2007
+
2008
+static const struct rk_gmac_ops rk3588_ops = {
2009
+	.set_to_rgmii = rk3588_set_to_rgmii,
2010
+	.set_to_rmii = rk3588_set_to_rmii,
2011
+	.set_rgmii_speed = rk3588_set_gmac_speed,
2012
+	.set_rmii_speed = rk3588_set_gmac_speed,
2013
+	.set_clock_selection = rk3588_set_clock_selection,
2014
+};
2015
+
2016
+#define RV1106_VOGRF_GMAC_CLK_CON		0X60004
2017
+
2018
+#define RV1106_VOGRF_MACPHY_RMII_MODE		GRF_BIT(0)
2019
+#define RV1106_VOGRF_GMAC_CLK_RMII_DIV2		GRF_BIT(2)
2020
+#define RV1106_VOGRF_GMAC_CLK_RMII_DIV20	GRF_CLR_BIT(2)
2021
+
2022
+#define RV1106_VOGRF_MACPHY_CON0		0X60028
2023
+#define RV1106_VOGRF_MACPHY_CON1		0X6002C
2024
+
2025
+static void rv1106_set_to_rmii(struct rk_priv_data *bsp_priv)
2026
+{
2027
+	struct device *dev = &bsp_priv->pdev->dev;
2028
+
2029
+	if (IS_ERR(bsp_priv->grf)) {
2030
+		dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
2031
+		return;
2032
+	}
2033
+
2034
+	regmap_write(bsp_priv->grf, RV1106_VOGRF_GMAC_CLK_CON,
2035
+		     RV1106_VOGRF_MACPHY_RMII_MODE |
2036
+		     RV1106_VOGRF_GMAC_CLK_RMII_DIV2);
2037
+}
2038
+
2039
+static void rv1106_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
2040
+{
2041
+	struct device *dev = &bsp_priv->pdev->dev;
2042
+	unsigned int val = 0;
2043
+
2044
+	if (IS_ERR(bsp_priv->grf)) {
2045
+		dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
2046
+		return;
2047
+	}
2048
+
2049
+	if (speed == 10) {
2050
+		val = RV1106_VOGRF_GMAC_CLK_RMII_DIV20;
2051
+	} else if (speed == 100) {
2052
+		val = RV1106_VOGRF_GMAC_CLK_RMII_DIV2;
2053
+	} else {
2054
+		dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
2055
+		return;
2056
+	}
2057
+
2058
+	regmap_write(bsp_priv->grf, RV1106_VOGRF_GMAC_CLK_CON, val);
2059
+}
2060
+
2061
+static void rv1106_integrated_sphy_power(struct rk_priv_data *priv, bool up)
2062
+{
2063
+	rk_gmac_integrated_fephy_power(priv, RV1106_VOGRF_MACPHY_CON0,
2064
+				       RV1106_VOGRF_MACPHY_CON1, up);
2065
+}
2066
+
2067
+static const struct rk_gmac_ops rv1106_ops = {
2068
+	.set_to_rmii = rv1106_set_to_rmii,
2069
+	.set_rmii_speed = rv1106_set_rmii_speed,
2070
+	.integrated_phy_power = rv1106_integrated_sphy_power,
14102071 };
14112072 
14122073 #define RV1108_GRF_GMAC_CON0		0X0900
....@@ -1472,21 +2133,18 @@
14722133 		(GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
14732134 #define RV1126_GMAC_FLOW_CTRL			GRF_BIT(7)
14742135 #define RV1126_GMAC_FLOW_CTRL_CLR		GRF_CLR_BIT(7)
1475
-#define RV1126_GMAC_M0_RXCLK_DLY_ENABLE		GRF_BIT(1)
1476
-#define RV1126_GMAC_M0_RXCLK_DLY_DISABLE	GRF_CLR_BIT(1)
1477
-#define RV1126_GMAC_M0_TXCLK_DLY_ENABLE		GRF_BIT(0)
1478
-#define RV1126_GMAC_M0_TXCLK_DLY_DISABLE	GRF_CLR_BIT(0)
1479
-#define RV1126_GMAC_M1_RXCLK_DLY_ENABLE		GRF_BIT(3)
1480
-#define RV1126_GMAC_M1_RXCLK_DLY_DISABLE	GRF_CLR_BIT(3)
1481
-#define RV1126_GMAC_M1_TXCLK_DLY_ENABLE		GRF_BIT(2)
1482
-#define RV1126_GMAC_M1_TXCLK_DLY_DISABLE	GRF_CLR_BIT(2)
2136
+#define RV1126_M0_GMAC_RXCLK_DLY_ENABLE		GRF_BIT(1)
2137
+#define RV1126_M0_GMAC_RXCLK_DLY_DISABLE	GRF_CLR_BIT(1)
2138
+#define RV1126_M0_GMAC_TXCLK_DLY_ENABLE		GRF_BIT(0)
2139
+#define RV1126_M0_GMAC_TXCLK_DLY_DISABLE	GRF_CLR_BIT(0)
2140
+#define RV1126_M1_GMAC_RXCLK_DLY_ENABLE		GRF_BIT(3)
2141
+#define RV1126_M1_GMAC_RXCLK_DLY_DISABLE	GRF_CLR_BIT(3)
2142
+#define RV1126_M1_GMAC_TXCLK_DLY_ENABLE		GRF_BIT(2)
2143
+#define RV1126_M1_GMAC_TXCLK_DLY_DISABLE	GRF_CLR_BIT(2)
14832144 
1484
-/* RV1126_GRF_GMAC_CON1 */
1485
-#define RV1126_GMAC_M0_CLK_RX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 8)
1486
-#define RV1126_GMAC_M0_CLK_TX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 0)
1487
-/* RV1126_GRF_GMAC_CON2 */
1488
-#define RV1126_GMAC_M1_CLK_RX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 8)
1489
-#define RV1126_GMAC_M1_CLK_TX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 0)
2145
+/* RV1126_GRF_GMAC_CON1 && RV1126_GRF_GMAC_CON2 */
2146
+#define RV1126_GMAC_CLK_RX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 8)
2147
+#define RV1126_GMAC_CLK_TX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 0)
14902148 
14912149 static void rv1126_set_to_rgmii(struct rk_priv_data *bsp_priv,
14922150 				int tx_delay, int rx_delay)
....@@ -1500,18 +2158,14 @@
15002158 
15012159 	regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON0,
15022160 		     RV1126_GMAC_PHY_INTF_SEL_RGMII |
1503
-		     RV1126_GMAC_M0_RXCLK_DLY_ENABLE |
1504
-		     RV1126_GMAC_M0_TXCLK_DLY_ENABLE |
1505
-		     RV1126_GMAC_M1_RXCLK_DLY_ENABLE |
1506
-		     RV1126_GMAC_M1_TXCLK_DLY_ENABLE);
2161
+		     DELAY_ENABLE(RV1126_M0, tx_delay, rx_delay) |
2162
+		     DELAY_ENABLE(RV1126_M1, tx_delay, rx_delay));
15072163 
15082164 	regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON1,
1509
-		     RV1126_GMAC_M0_CLK_RX_DL_CFG(rx_delay) |
1510
-		     RV1126_GMAC_M0_CLK_TX_DL_CFG(tx_delay));
2165
+		     DELAY_VALUE(RV1126, tx_delay, rx_delay));
15112166 
15122167 	regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON2,
1513
-		     RV1126_GMAC_M1_CLK_RX_DL_CFG(rx_delay) |
1514
-		     RV1126_GMAC_M1_CLK_TX_DL_CFG(tx_delay));
2168
+		     DELAY_VALUE(RV1126, tx_delay, rx_delay));
15152169 }
15162170 
15172171 static void rv1126_set_to_rmii(struct rk_priv_data *bsp_priv)
....@@ -1585,50 +2239,6 @@
15852239 	.set_rmii_speed = rv1126_set_rmii_speed,
15862240 };
15872241 
1588
-#define RK_GRF_MACPHY_CON0		0xb00
1589
-#define RK_GRF_MACPHY_CON1		0xb04
1590
-#define RK_GRF_MACPHY_CON2		0xb08
1591
-#define RK_GRF_MACPHY_CON3		0xb0c
1592
-
1593
-#define RK_MACPHY_ENABLE		GRF_BIT(0)
1594
-#define RK_MACPHY_DISABLE		GRF_CLR_BIT(0)
1595
-#define RK_MACPHY_CFG_CLK_50M		GRF_BIT(14)
1596
-#define RK_GMAC2PHY_RMII_MODE		(GRF_BIT(6) | GRF_CLR_BIT(7))
1597
-#define RK_GRF_CON2_MACPHY_ID		HIWORD_UPDATE(0x1234, 0xffff, 0)
1598
-#define RK_GRF_CON3_MACPHY_ID		HIWORD_UPDATE(0x35, 0x3f, 0)
1599
-
1600
-static void rk_gmac_integrated_phy_powerup(struct rk_priv_data *priv)
1601
-{
1602
-	if (priv->ops->integrated_phy_powerup)
1603
-		priv->ops->integrated_phy_powerup(priv);
1604
-
1605
-	regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_CFG_CLK_50M);
1606
-	regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_GMAC2PHY_RMII_MODE);
1607
-
1608
-	regmap_write(priv->grf, RK_GRF_MACPHY_CON2, RK_GRF_CON2_MACPHY_ID);
1609
-	regmap_write(priv->grf, RK_GRF_MACPHY_CON3, RK_GRF_CON3_MACPHY_ID);
1610
-
1611
-	if (priv->phy_reset) {
1612
-		/* PHY needs to be disabled before trying to reset it */
1613
-		regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
1614
-		if (priv->phy_reset)
1615
-			reset_control_assert(priv->phy_reset);
1616
-		usleep_range(10, 20);
1617
-		if (priv->phy_reset)
1618
-			reset_control_deassert(priv->phy_reset);
1619
-		usleep_range(10, 20);
1620
-		regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_ENABLE);
1621
-		msleep(30);
1622
-	}
1623
-}
1624
-
1625
-static void rk_gmac_integrated_phy_powerdown(struct rk_priv_data *priv)
1626
-{
1627
-	regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
1628
-	if (priv->phy_reset)
1629
-		reset_control_assert(priv->phy_reset);
1630
-}
1631
-
16322242 static int rk_gmac_clk_init(struct plat_stmmacenet_data *plat)
16332243 {
16342244 	struct rk_priv_data *bsp_priv = plat->bsp_priv;
....@@ -1679,8 +2289,10 @@
16792289 		   bsp_priv->phy_iface == PHY_INTERFACE_MODE_QSGMII) {
16802290 		bsp_priv->pclk_xpcs = devm_clk_get(dev, "pclk_xpcs");
16812291 		if (IS_ERR(bsp_priv->pclk_xpcs))
1682
-			dev_err(dev, "cannot get clock %s\n",
1683
-				"pclk_xpcs");
2292
+			dev_err(dev, "cannot get clock %s\n", "pclk_xpcs");
2293
+		bsp_priv->clk_xpcs_eee = devm_clk_get(dev, "clk_xpcs_eee");
2294
+		if (IS_ERR(bsp_priv->clk_xpcs_eee))
2295
+			dev_err(dev, "cannot get clock %s\n", "clk_xpcs_eee");
16842296 	}
16852297 
16862298 	bsp_priv->clk_mac_speed = devm_clk_get(dev, "clk_mac_speed");
....@@ -1748,15 +2360,26 @@
17482360 			if (!IS_ERR(bsp_priv->pclk_xpcs))
17492361 				clk_prepare_enable(bsp_priv->pclk_xpcs);
17502362 
2363
+			if (!IS_ERR(bsp_priv->clk_xpcs_eee))
2364
+				clk_prepare_enable(bsp_priv->clk_xpcs_eee);
2365
+
2366
+			if (bsp_priv->ops && bsp_priv->ops->set_clock_selection)
2367
+				bsp_priv->ops->set_clock_selection(bsp_priv,
2368
+					       bsp_priv->clock_input, true);
2369
+
17512370 			/**
17522371 			 * if (!IS_ERR(bsp_priv->clk_mac))
17532372 			 *	clk_prepare_enable(bsp_priv->clk_mac);
17542373 			 */
1755
-			mdelay(5);
2374
+			usleep_range(100, 200);
17562375 			bsp_priv->clk_enabled = true;
17572376 		}
17582377 	} else {
17592378 		if (bsp_priv->clk_enabled) {
2379
+			if (bsp_priv->ops && bsp_priv->ops->set_clock_selection)
2380
+				bsp_priv->ops->set_clock_selection(bsp_priv,
2381
+					      bsp_priv->clock_input, false);
2382
+
17602383 			if (phy_iface == PHY_INTERFACE_MODE_RMII) {
17612384 				clk_disable_unprepare(bsp_priv->mac_clk_rx);
17622385 
....@@ -1776,6 +2399,8 @@
17762399 			clk_disable_unprepare(bsp_priv->clk_mac_speed);
17772400 
17782401 			clk_disable_unprepare(bsp_priv->pclk_xpcs);
2402
+
2403
+			clk_disable_unprepare(bsp_priv->clk_xpcs_eee);
17792404 
17802405 			/**
17812406 			 * if (!IS_ERR(bsp_priv->clk_mac))
....@@ -1824,7 +2449,7 @@
18242449 	if (!bsp_priv)
18252450 		return ERR_PTR(-ENOMEM);
18262451 
1827
-	bsp_priv->phy_iface = of_get_phy_mode(dev->of_node);
2452
+	of_get_phy_mode(dev->of_node, &bsp_priv->phy_iface);
18282453 	bsp_priv->ops = ops;
18292454 	bsp_priv->bus_id = plat->bus_id;
18302455 
....@@ -1853,7 +2478,7 @@
18532478 
18542479 	ret = of_property_read_u32(dev->of_node, "tx_delay", &value);
18552480 	if (ret) {
1856
-		bsp_priv->tx_delay = 0x30;
2481
+		bsp_priv->tx_delay = -1;
18572482 		dev_err(dev, "Can not read property: tx_delay.");
18582483 		dev_err(dev, "set tx_delay to 0x%x\n",
18592484 			bsp_priv->tx_delay);
....@@ -1864,7 +2489,7 @@
18642489 
18652490 	ret = of_property_read_u32(dev->of_node, "rx_delay", &value);
18662491 	if (ret) {
1867
-		bsp_priv->rx_delay = 0x10;
2492
+		bsp_priv->rx_delay = -1;
18682493 		dev_err(dev, "Can not read property: rx_delay.");
18692494 		dev_err(dev, "set rx_delay to 0x%x\n",
18702495 			bsp_priv->rx_delay);
....@@ -1875,6 +2500,8 @@
18752500 
18762501 	bsp_priv->grf = syscon_regmap_lookup_by_phandle(dev->of_node,
18772502 							"rockchip,grf");
2503
+	bsp_priv->php_grf = syscon_regmap_lookup_by_phandle(dev->of_node,
2504
+							    "rockchip,php_grf");
18782505 	bsp_priv->xpcs = syscon_regmap_lookup_by_phandle(dev->of_node,
18792506 							 "rockchip,xpcs");
18802507 	if (!IS_ERR(bsp_priv->xpcs)) {
....@@ -1892,10 +2519,45 @@
18922519 		bsp_priv->integrated_phy = of_property_read_bool(plat->phy_node,
18932520 								 "phy-is-integrated");
18942521 		if (bsp_priv->integrated_phy) {
2522
+			unsigned char *efuse_buf;
2523
+			struct nvmem_cell *cell;
2524
+			size_t len;
2525
+
18952526 			bsp_priv->phy_reset = of_reset_control_get(plat->phy_node, NULL);
18962527 			if (IS_ERR(bsp_priv->phy_reset)) {
18972528 				dev_err(&pdev->dev, "No PHY reset control found.\n");
18982529 				bsp_priv->phy_reset = NULL;
2530
+			}
2531
+
2532
+			if (of_property_read_u32(plat->phy_node, "bgs,increment",
2533
+						 &bsp_priv->bgs_increment)) {
2534
+				bsp_priv->bgs_increment = 0;
2535
+			} else {
2536
+				if (bsp_priv->bgs_increment > RK_FEPHY_BGS_MAX) {
2537
+					dev_err(dev, "%s: error bgs increment: %d\n",
2538
+						__func__, bsp_priv->bgs_increment);
2539
+					bsp_priv->bgs_increment = RK_FEPHY_BGS_MAX;
2540
+				}
2541
+			}
2542
+
2543
+			/* Read bgs from OTP if it exists */
2544
+			cell = nvmem_cell_get(dev, "bgs");
2545
+			if (IS_ERR(cell)) {
2546
+				if (PTR_ERR(cell) != -EPROBE_DEFER)
2547
+					dev_info(dev, "failed to get bgs cell: %ld, use default\n",
2548
+						 PTR_ERR(cell));
2549
+				else
2550
+					return ERR_CAST(cell);
2551
+			} else {
2552
+				efuse_buf = nvmem_cell_read(cell, &len);
2553
+				nvmem_cell_put(cell);
2554
+				if (!IS_ERR(efuse_buf)) {
2555
+					if (len == 1)
2556
+						bsp_priv->otp_data = efuse_buf[0];
2557
+					kfree(efuse_buf);
2558
+				} else {
2559
+					dev_err(dev, "failed to get efuse buf, use default\n");
2560
+				}
18992561 			}
19002562 		}
19012563 	}
....@@ -1927,17 +2589,17 @@
19272589 	case PHY_INTERFACE_MODE_RGMII_ID:
19282590 		dev_info(dev, "init for RGMII_ID\n");
19292591 		if (bsp_priv->ops && bsp_priv->ops->set_to_rgmii)
1930
-			bsp_priv->ops->set_to_rgmii(bsp_priv, 0, 0);
2592
+			bsp_priv->ops->set_to_rgmii(bsp_priv, -1, -1);
19312593 		break;
19322594 	case PHY_INTERFACE_MODE_RGMII_RXID:
19332595 		dev_info(dev, "init for RGMII_RXID\n");
19342596 		if (bsp_priv->ops && bsp_priv->ops->set_to_rgmii)
1935
-			bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay, 0);
2597
+			bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay, -1);
19362598 		break;
19372599 	case PHY_INTERFACE_MODE_RGMII_TXID:
19382600 		dev_info(dev, "init for RGMII_TXID\n");
19392601 		if (bsp_priv->ops && bsp_priv->ops->set_to_rgmii)
1940
-			bsp_priv->ops->set_to_rgmii(bsp_priv, 0, bsp_priv->rx_delay);
2602
+			bsp_priv->ops->set_to_rgmii(bsp_priv, -1, bsp_priv->rx_delay);
19412603 		break;
19422604 	case PHY_INTERFACE_MODE_RMII:
19432605 		dev_info(dev, "init for RMII\n");
....@@ -1964,24 +2626,14 @@
19642626 		return ret;
19652627 	}
19662628 
1967
-	pm_runtime_enable(dev);
19682629 	pm_runtime_get_sync(dev);
1969
-
1970
-	if (bsp_priv->integrated_phy)
1971
-		rk_gmac_integrated_phy_powerup(bsp_priv);
19722630 
19732631 	return 0;
19742632 }
19752633 
19762634 static void rk_gmac_powerdown(struct rk_priv_data *gmac)
19772635 {
1978
-	struct device *dev = &gmac->pdev->dev;
1979
-
1980
-	if (gmac->integrated_phy)
1981
-		rk_gmac_integrated_phy_powerdown(gmac);
1982
-
1983
-	pm_runtime_put_sync(dev);
1984
-	pm_runtime_disable(dev);
2636
+	pm_runtime_put_sync(&gmac->pdev->dev);
19852637 
19862638 	rk_gmac_phy_power_on(gmac, false);
19872639 	gmac_clk_enable(gmac, false);
....@@ -2010,6 +2662,19 @@
20102662 	default:
20112663 		dev_err(dev, "unsupported interface %d", bsp_priv->phy_iface);
20122664 	}
2665
+}
2666
+
2667
+static int rk_integrated_phy_power(void *priv, bool up)
2668
+{
2669
+	struct rk_priv_data *bsp_priv = priv;
2670
+
2671
+	if (!bsp_priv->integrated_phy || !bsp_priv->ops ||
2672
+	    !bsp_priv->ops->integrated_phy_power)
2673
+		return 0;
2674
+
2675
+	bsp_priv->ops->integrated_phy_power(bsp_priv, up);
2676
+
2677
+	return 0;
20132678 }
20142679 
20152680 void dwmac_rk_set_rgmii_delayline(struct stmmac_priv *priv,
....@@ -2046,28 +2711,21 @@
20462711 }
20472712 EXPORT_SYMBOL(dwmac_rk_get_phy_interface);
20482713 
2049
-void __weak rk_devinfo_get_eth_mac(u8 *mac)
2050
-{
2051
-}
2052
-
20532714 static unsigned char macaddr[6];
20542715 extern ssize_t at24_mac_read(unsigned char* addr);
2055
-void rk_get_eth_addr(void *priv, unsigned char *addr)
2716
+static void rk_get_eth_addr(void *priv, unsigned char *addr)
20562717 {
20572718 	struct rk_priv_data *bsp_priv = priv;
20582719 	struct device *dev = &bsp_priv->pdev->dev;
2059
-	int i;
20602720 	//unsigned char ethaddr[ETH_ALEN * MAX_ETH] = {0};
2061
-	//int ret, id = bsp_priv->bus_id;
2721
+	int ret, id = bsp_priv->bus_id;
2722
+	//int i;
20622723 
2063
-	//ben
2064
-	printk("nk-debug:enter rk_get_eth_addr.. \n");
2065
-
2066
-	#if 0
2067
-	rk_devinfo_get_eth_mac(addr);
2724
+	printk("hw-debug:enter rk_get_eth_addr.. \n");
2725
+#if 0
20682726 	if (is_valid_ether_addr(addr))
20692727 		goto out;
2070
-		
2728
+
20712729 	if (id < 0 || id >= MAX_ETH) {
20722730 		dev_err(dev, "%s: Invalid ethernet bus id %d\n", __func__, id);
20732731 		return;
....@@ -2094,35 +2752,32 @@
20942752 	} else {
20952753 		memcpy(addr, &ethaddr[id * ETH_ALEN], ETH_ALEN);
20962754 	}
2097
-	#endif
2755
+#endif
20982756 	
2099
-	#if 0
2100
-	macaddr[0] = 0xee;
2101
-	macaddr[1] = 0x31;
2102
-	macaddr[2] = 0x32;
2103
-	macaddr[3] = 0x33;
2104
-	macaddr[4] = 0x34;
2105
-	macaddr[5] = 0x35;
2106
-	
2107
-	memcpy(addr, macaddr, 6);
2108
-	#endif
2109
-	
2110
-	#if 1
2111
-	if (at24_mac_read(macaddr) > 0) {
2112
-		printk("ben %s: at24_mac_read Success!! \n", __func__);
2113
-		memcpy(addr, macaddr, 6);
21142757 
2115
-		printk("Read the Ethernet MAC address from :");
2116
-		for (i = 0; i < 5; i++)
2117
-			printk("%2.2x:", addr[i]);
2118
- 
2119
-		printk("%2.2x\n", addr[i]);	
2120
-	} else {
2121
-		printk("ben %s: at24_mac_read Failed!! \n", __func__);
2122
-		goto out;
2123
-	}
2124
-	#endif
2125
-	
2758
+	//eeprom
2759
+        	ret = at24_mac_read(macaddr);
2760
+        	if (ret > 0)
2761
+        	{
2762
+                	printk("ben %s: at24_mac_read Success!! \n", __func__);
2763
+                	memcpy(addr, macaddr, 6);
2764
+
2765
+                	if ((addr[0] == 0x68) && (addr[1] == 0xed))
2766
+                	{
2767
+                        	printk("at24_eeprom mac is valid \n", __func__);
2768
+                        	goto out;
2769
+        		}
2770
+                	else
2771
+                	{
2772
+                        	printk("at24_eeprom mac is invalid \n", __func__);
2773
+                        	addr[0] = 0x68;
2774
+                        	addr[1] = 0xed;
2775
+                        	addr[2] = 0x01;
2776
+                        	addr[3] = 0x02;
2777
+                        	addr[4] = 0x03;
2778
+                        	addr[5] = 0x04;
2779
+                	}
2780
+    		}
21262781 out:
21272782 	dev_err(dev, "%s: mac address: %pM\n", __func__, addr);
21282783 }
....@@ -2134,7 +2789,6 @@
21342789 	const struct rk_gmac_ops *data;
21352790 	int ret;
21362791 
2137
-	printk("nk-debug:enter rk_gmac_probe 1.. \n");
21382792 	data = of_device_get_match_data(&pdev->dev);
21392793 	if (!data) {
21402794 		dev_err(&pdev->dev, "no of match data provided\n");
....@@ -2152,8 +2806,10 @@
21522806 	if (!of_device_is_compatible(pdev->dev.of_node, "snps,dwmac-4.20a"))
21532807 		plat_dat->has_gmac = true;
21542808 
2809
+	plat_dat->sph_disable = true;
21552810 	plat_dat->fix_mac_speed = rk_fix_speed;
21562811 	plat_dat->get_eth_addr = rk_get_eth_addr;
2812
+	plat_dat->integrated_phy_power = rk_integrated_phy_power;
21572813 
21582814 	plat_dat->bsp_priv = rk_gmac_setup(pdev, plat_dat, data);
21592815 	if (IS_ERR(plat_dat->bsp_priv)) {
....@@ -2161,7 +2817,6 @@
21612817 		goto err_remove_config_dt;
21622818 	}
21632819 
2164
-	printk("nk-debug:enter rk_gmac_probe 2.. \n");
21652820 	ret = rk_gmac_clk_init(plat_dat);
21662821 	if (ret)
21672822 		goto err_remove_config_dt;
....@@ -2231,19 +2886,57 @@
22312886 static SIMPLE_DEV_PM_OPS(rk_gmac_pm_ops, rk_gmac_suspend, rk_gmac_resume);
22322887 
22332888 static const struct of_device_id rk_gmac_dwmac_match[] = {
2889
+#ifdef CONFIG_CPU_PX30
22342890 	{ .compatible = "rockchip,px30-gmac",	.data = &px30_ops   },
2891
+#endif
2892
+#ifdef CONFIG_CPU_RK1808
22352893 	{ .compatible = "rockchip,rk1808-gmac", .data = &rk1808_ops },
2894
+#endif
2895
+#ifdef CONFIG_CPU_RK312X
22362896 	{ .compatible = "rockchip,rk3128-gmac", .data = &rk3128_ops },
2897
+#endif
2898
+#ifdef CONFIG_CPU_RK322X
22372899 	{ .compatible = "rockchip,rk3228-gmac", .data = &rk3228_ops },
2900
+#endif
2901
+#ifdef CONFIG_CPU_RK3288
22382902 	{ .compatible = "rockchip,rk3288-gmac", .data = &rk3288_ops },
2903
+#endif
2904
+#ifdef CONFIG_CPU_RK3308
22392905 	{ .compatible = "rockchip,rk3308-mac",  .data = &rk3308_ops },
2906
+#endif
2907
+#ifdef CONFIG_CPU_RK3328
22402908 	{ .compatible = "rockchip,rk3328-gmac", .data = &rk3328_ops },
2909
+#endif
2910
+#ifdef CONFIG_CPU_RK3366
22412911 	{ .compatible = "rockchip,rk3366-gmac", .data = &rk3366_ops },
2912
+#endif
2913
+#ifdef CONFIG_CPU_RK3368
22422914 	{ .compatible = "rockchip,rk3368-gmac", .data = &rk3368_ops },
2915
+#endif
2916
+#ifdef CONFIG_CPU_RK3399
22432917 	{ .compatible = "rockchip,rk3399-gmac", .data = &rk3399_ops },
2918
+#endif
2919
+#ifdef CONFIG_CPU_RK3528
2920
+	{ .compatible = "rockchip,rk3528-gmac", .data = &rk3528_ops },
2921
+#endif
2922
+#ifdef CONFIG_CPU_RK3562
2923
+	{ .compatible = "rockchip,rk3562-gmac", .data = &rk3562_ops },
2924
+#endif
2925
+#ifdef CONFIG_CPU_RK3568
22442926 	{ .compatible = "rockchip,rk3568-gmac", .data = &rk3568_ops },
2927
+#endif
2928
+#ifdef CONFIG_CPU_RK3588
2929
+	{ .compatible = "rockchip,rk3588-gmac", .data = &rk3588_ops },
2930
+#endif
2931
+#ifdef CONFIG_CPU_RV1106
2932
+	{ .compatible = "rockchip,rv1106-gmac", .data = &rv1106_ops },
2933
+#endif
2934
+#ifdef CONFIG_CPU_RV1108
22452935 	{ .compatible = "rockchip,rv1108-gmac", .data = &rv1108_ops },
2936
+#endif
2937
+#ifdef CONFIG_CPU_RV1126
22462938 	{ .compatible = "rockchip,rv1126-gmac", .data = &rv1126_ops },
2939
+#endif
22472940 	{ }
22482941 };
22492942 MODULE_DEVICE_TABLE(of, rk_gmac_dwmac_match);
....@@ -2258,7 +2951,7 @@
22582951 	},
22592952 };
22602953 //module_platform_driver(rk_gmac_dwmac_driver);
2261
- module_platform_driver1(rk_gmac_dwmac_driver);
2954
+module_platform_driver1(rk_gmac_dwmac_driver);
22622955 
22632956 MODULE_AUTHOR("Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com>");
22642957 MODULE_DESCRIPTION("Rockchip RK3288 DWMAC specific glue layer");