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| 1 | +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ |
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1 | 2 | /* QLogic qed NIC Driver |
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2 | 3 | * Copyright (c) 2015-2017 QLogic Corporation |
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3 | | - * |
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4 | | - * This software is available to you under a choice of one of two |
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5 | | - * licenses. You may choose to be licensed under the terms of the GNU |
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6 | | - * General Public License (GPL) Version 2, available from the file |
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7 | | - * COPYING in the main directory of this source tree, or the |
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8 | | - * OpenIB.org BSD license below: |
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9 | | - * |
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10 | | - * Redistribution and use in source and binary forms, with or |
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11 | | - * without modification, are permitted provided that the following |
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12 | | - * conditions are met: |
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13 | | - * |
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14 | | - * - Redistributions of source code must retain the above |
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15 | | - * copyright notice, this list of conditions and the following |
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16 | | - * disclaimer. |
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17 | | - * |
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18 | | - * - Redistributions in binary form must reproduce the above |
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19 | | - * copyright notice, this list of conditions and the following |
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20 | | - * disclaimer in the documentation and /or other materials |
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21 | | - * provided with the distribution. |
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22 | | - * |
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23 | | - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
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24 | | - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
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25 | | - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
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26 | | - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS |
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27 | | - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN |
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28 | | - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
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29 | | - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
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30 | | - * SOFTWARE. |
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| 4 | + * Copyright (c) 2019-2020 Marvell International Ltd. |
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31 | 5 | */ |
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32 | 6 | |
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33 | 7 | #ifndef _QED_INT_H |
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.. | .. |
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37 | 11 | #include <linux/slab.h> |
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38 | 12 | #include "qed.h" |
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39 | 13 | |
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40 | | -/* Fields of IGU PF CONFIGRATION REGISTER */ |
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| 14 | +/* Fields of IGU PF CONFIGURATION REGISTER */ |
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41 | 15 | #define IGU_PF_CONF_FUNC_EN (0x1 << 0) /* function enable */ |
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42 | 16 | #define IGU_PF_CONF_MSI_MSIX_EN (0x1 << 1) /* MSI/MSIX enable */ |
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43 | 17 | #define IGU_PF_CONF_INT_LINE_EN (0x1 << 2) /* INT enable */ |
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44 | 18 | #define IGU_PF_CONF_ATTN_BIT_EN (0x1 << 3) /* attention enable */ |
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45 | 19 | #define IGU_PF_CONF_SINGLE_ISR_EN (0x1 << 4) /* single ISR mode enable */ |
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46 | 20 | #define IGU_PF_CONF_SIMD_MODE (0x1 << 5) /* simd all ones mode */ |
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47 | | -/* Fields of IGU VF CONFIGRATION REGISTER */ |
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| 21 | +/* Fields of IGU VF CONFIGURATION REGISTER */ |
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48 | 22 | #define IGU_VF_CONF_FUNC_EN (0x1 << 0) /* function enable */ |
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49 | 23 | #define IGU_VF_CONF_MSI_MSIX_EN (0x1 << 1) /* MSI/MSIX enable */ |
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50 | 24 | #define IGU_VF_CONF_SINGLE_ISR_EN (0x1 << 4) /* single ISR mode enable */ |
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.. | .. |
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166 | 140 | * @param p_hwfn - pointer to hwfn |
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167 | 141 | * |
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168 | 142 | */ |
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169 | | -void qed_int_sp_dpc(unsigned long hwfn_cookie); |
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| 143 | +void qed_int_sp_dpc(struct tasklet_struct *t); |
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170 | 144 | |
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171 | 145 | /** |
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172 | 146 | * @brief qed_int_get_num_sbs - get the number of status |
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.. | .. |
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189 | 163 | * |
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190 | 164 | */ |
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191 | 165 | void qed_int_disable_post_isr_release(struct qed_dev *cdev); |
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| 166 | + |
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| 167 | +/** |
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| 168 | + * @brief qed_int_attn_clr_enable - sets whether the general behavior is |
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| 169 | + * preventing attentions from being reasserted, or following the |
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| 170 | + * attributes of the specific attention. |
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| 171 | + * |
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| 172 | + * @param cdev |
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| 173 | + * @param clr_enable |
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| 174 | + * |
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| 175 | + */ |
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| 176 | +void qed_int_attn_clr_enable(struct qed_dev *cdev, bool clr_enable); |
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| 177 | + |
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| 178 | +/** |
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| 179 | + * @brief - Doorbell Recovery handler. |
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| 180 | + * Run doorbell recovery in case of PF overflow (and flush DORQ if |
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| 181 | + * needed). |
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| 182 | + * |
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| 183 | + * @param p_hwfn |
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| 184 | + * @param p_ptt |
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| 185 | + */ |
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| 186 | +int qed_db_rec_handler(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); |
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192 | 187 | |
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193 | 188 | #define QED_CAU_DEF_RX_TIMER_RES 0 |
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194 | 189 | #define QED_CAU_DEF_TX_TIMER_RES 0 |
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.. | .. |
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421 | 416 | |
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422 | 417 | #define QED_MAPPING_MEMORY_SIZE(dev) (NUM_OF_SBS(dev)) |
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423 | 418 | |
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| 419 | +int qed_pglueb_rbc_attn_handler(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, |
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| 420 | + bool hw_init); |
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| 421 | + |
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424 | 422 | #endif |
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