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2024-05-10 9999e48639b3cecb08ffb37358bcba3b48161b29 
 kernel/drivers/net/ethernet/qlogic/qed/qed_init_ops.c
....@@ -1,33 +1,7 @@
1
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
12 /* QLogic qed NIC Driver
23  * Copyright (c) 2015-2017  QLogic Corporation
3
- *
4
- * This software is available to you under a choice of one of two
5
- * licenses.  You may choose to be licensed under the terms of the GNU
6
- * General Public License (GPL) Version 2, available from the file
7
- * COPYING in the main directory of this source tree, or the
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- * OpenIB.org BSD license below:
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- *
10
- *     Redistribution and use in source and binary forms, with or
11
- *     without modification, are permitted provided that the following
12
- *     conditions are met:
13
- *
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- *      - Redistributions of source code must retain the above
15
- *        copyright notice, this list of conditions and the following
16
- *        disclaimer.
17
- *
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- *      - Redistributions in binary form must reproduce the above
19
- *        copyright notice, this list of conditions and the following
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- *        disclaimer in the documentation and /or other materials
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- *        provided with the distribution.
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- *
23
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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- * SOFTWARE.
4
+ * Copyright (c) 2019-2020 Marvell International Ltd.
315  */
326 
337 #include <linux/types.h>
....@@ -54,33 +28,97 @@
5428 	0x1c80, /* win 3: addr=0x1c80000, size=4096 bytes */
5529 	0x1d00, /* win 4: addr=0x1d00000, size=4096 bytes */
5630 	0x1d01, /* win 5: addr=0x1d01000, size=4096 bytes */
57
-	0x1d80, /* win 6: addr=0x1d80000, size=4096 bytes */
58
-	0x1d81, /* win 7: addr=0x1d81000, size=4096 bytes */
59
-	0x1d82, /* win 8: addr=0x1d82000, size=4096 bytes */
60
-	0x1e00, /* win 9: addr=0x1e00000, size=4096 bytes */
61
-	0x1e80, /* win 10: addr=0x1e80000, size=4096 bytes */
62
-	0x1f00, /* win 11: addr=0x1f00000, size=4096 bytes */
63
-	0,
64
-	0,
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-	0,
31
+	0x1d02, /* win 6: addr=0x1d02000, size=4096 bytes */
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+	0x1d80, /* win 7: addr=0x1d80000, size=4096 bytes */
33
+	0x1d81, /* win 8: addr=0x1d81000, size=4096 bytes */
34
+	0x1d82, /* win 9: addr=0x1d82000, size=4096 bytes */
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+	0x1e00, /* win 10: addr=0x1e00000, size=4096 bytes */
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+	0x1e01, /* win 11: addr=0x1e01000, size=4096 bytes */
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+	0x1e80, /* win 12: addr=0x1e80000, size=4096 bytes */
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+	0x1f00, /* win 13: addr=0x1f00000, size=4096 bytes */
39
+	0x1c08, /* win 14: addr=0x1c08000, size=4096 bytes */
6640 	0,
6741 	0,
6842 	0,
6943 	0,
7044 };
7145 
46
+/* IRO Array */
47
+static const u32 iro_arr[] = {
48
+	0x00000000, 0x00000000, 0x00080000,
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+	0x00003288, 0x00000088, 0x00880000,
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+	0x000058e8, 0x00000020, 0x00200000,
51
+	0x00000b00, 0x00000008, 0x00040000,
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+	0x00000a80, 0x00000008, 0x00040000,
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+	0x00000000, 0x00000008, 0x00020000,
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+	0x00000080, 0x00000008, 0x00040000,
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+	0x00000084, 0x00000008, 0x00020000,
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+	0x00005718, 0x00000004, 0x00040000,
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+	0x00004dd0, 0x00000000, 0x00780000,
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+	0x00003e40, 0x00000000, 0x00780000,
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+	0x00004480, 0x00000000, 0x00780000,
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+	0x00003210, 0x00000000, 0x00780000,
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+	0x00003b50, 0x00000000, 0x00780000,
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+	0x00007f58, 0x00000000, 0x00780000,
63
+	0x00005f58, 0x00000000, 0x00080000,
64
+	0x00007100, 0x00000000, 0x00080000,
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+	0x0000aea0, 0x00000000, 0x00080000,
66
+	0x00004398, 0x00000000, 0x00080000,
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+	0x0000a5a0, 0x00000000, 0x00080000,
68
+	0x0000bde8, 0x00000000, 0x00080000,
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+	0x00000020, 0x00000004, 0x00040000,
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+	0x000056c8, 0x00000010, 0x00100000,
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+	0x0000c210, 0x00000030, 0x00300000,
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+	0x0000b088, 0x00000038, 0x00380000,
73
+	0x00003d20, 0x00000080, 0x00400000,
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+	0x0000bf60, 0x00000000, 0x00040000,
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+	0x00004560, 0x00040080, 0x00040000,
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+	0x000001f8, 0x00000004, 0x00040000,
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+	0x00003d60, 0x00000080, 0x00200000,
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+	0x00008960, 0x00000040, 0x00300000,
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+	0x0000e840, 0x00000060, 0x00600000,
80
+	0x00004618, 0x00000080, 0x00380000,
81
+	0x00010738, 0x000000c0, 0x00c00000,
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+	0x000001f8, 0x00000002, 0x00020000,
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+	0x0000a2a0, 0x00000000, 0x01080000,
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+	0x0000a3a8, 0x00000008, 0x00080000,
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+	0x000001c0, 0x00000008, 0x00080000,
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+	0x000001f8, 0x00000008, 0x00080000,
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+	0x00000ac0, 0x00000008, 0x00080000,
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+	0x00002578, 0x00000008, 0x00080000,
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+	0x000024f8, 0x00000008, 0x00080000,
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+	0x00000280, 0x00000008, 0x00080000,
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+	0x00000680, 0x00080018, 0x00080000,
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+	0x00000b78, 0x00080018, 0x00020000,
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+	0x0000c640, 0x00000050, 0x003c0000,
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+	0x00012038, 0x00000018, 0x00100000,
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+	0x00011b00, 0x00000040, 0x00180000,
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+	0x000095d0, 0x00000050, 0x00200000,
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+	0x00008b10, 0x00000040, 0x00280000,
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+	0x00011640, 0x00000018, 0x00100000,
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+	0x0000c828, 0x00000048, 0x00380000,
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+	0x00011710, 0x00000020, 0x00200000,
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+	0x00004650, 0x00000080, 0x00100000,
102
+	0x00003618, 0x00000010, 0x00100000,
103
+	0x0000a968, 0x00000008, 0x00010000,
104
+	0x000097a0, 0x00000008, 0x00010000,
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+	0x00011990, 0x00000008, 0x00010000,
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+	0x0000f018, 0x00000008, 0x00010000,
107
+	0x00012628, 0x00000008, 0x00010000,
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+	0x00011da8, 0x00000008, 0x00010000,
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+	0x0000aa78, 0x00000030, 0x00100000,
110
+	0x0000d768, 0x00000028, 0x00280000,
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+	0x00009a58, 0x00000018, 0x00180000,
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+	0x00009bd8, 0x00000008, 0x00080000,
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+	0x00013a18, 0x00000008, 0x00080000,
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+	0x000126e8, 0x00000018, 0x00180000,
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+	0x0000e608, 0x00500288, 0x00100000,
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+	0x00012970, 0x00000138, 0x00280000,
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+};
118
+
72119 void qed_init_iro_array(struct qed_dev *cdev)
73120 {
74121 	cdev->iro_arr = iro_arr;
75
-}
76
-
77
-/* Runtime configuration helpers */
78
-void qed_init_clear_rt_data(struct qed_hwfn *p_hwfn)
79
-{
80
-	int i;
81
-
82
-	for (i = 0; i < RUNTIME_ARRAY_SIZE; i++)
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-		p_hwfn->rt_data.b_valid[i] = false;
84122 }
85123 
86124 void qed_init_store_rt_reg(struct qed_hwfn *p_hwfn, u32 rt_offset, u32 val)
....@@ -106,7 +144,7 @@
106144 {
107145 	u32 *p_init_val = &p_hwfn->rt_data.init_val[rt_offset];
108146 	bool *p_valid = &p_hwfn->rt_data.b_valid[rt_offset];
109
-	u16 i, segment;
147
+	u16 i, j, segment;
110148 	int rc = 0;
111149 
112150 	/* Since not all RT entries are initialized, go over the RT and
....@@ -121,6 +159,7 @@
121159 		 */
122160 		if (!b_must_dmae) {
123161 			qed_wr(p_hwfn, p_ptt, addr + (i << 2), p_init_val[i]);
162
+			p_valid[i] = false;
124163 			continue;
125164 		}
126165 
....@@ -131,9 +170,13 @@
131170 
132171 		rc = qed_dmae_host2grc(p_hwfn, p_ptt,
133172 				       (uintptr_t)(p_init_val + i),
134
-				       addr + (i << 2), segment, 0);
173
+				       addr + (i << 2), segment, NULL);
135174 		if (rc)
136175 			return rc;
176
+
177
+		/* invalidate after writing */
178
+		for (j = i; j < i + segment; j++)
179
+			p_valid[j] = false;
137180 
138181 		/* Jump over the entire segment, including invalid entry */
139182 		i += segment;
....@@ -194,7 +237,7 @@
194237 	} else {
195238 		rc = qed_dmae_host2grc(p_hwfn, p_ptt,
196239 				       (uintptr_t)(buf + dmae_data_offset),
197
-				       addr, size, 0);
240
+				       addr, size, NULL);
198241 	}
199242 
200243 	return rc;
....@@ -205,6 +248,7 @@
205248 			      u32 addr, u32 fill, u32 fill_count)
206249 {
207250 	static u32 zero_buffer[DMAE_MAX_RW_SIZE];
251
+	struct qed_dmae_params params = {};
208252 
209253 	memset(zero_buffer, 0, sizeof(u32) * DMAE_MAX_RW_SIZE);
210254 
....@@ -214,10 +258,10 @@
214258 	 * 3. p_hwfb->temp_data,
215259 	 * 4. fill_count
216260 	 */
217
-
261
+	SET_FIELD(params.flags, QED_DMAE_PARAMS_RW_REPL_SRC, 0x1);
218262 	return qed_dmae_host2grc(p_hwfn, p_ptt,
219263 				 (uintptr_t)(&zero_buffer[0]),
220
-				 addr, fill_count, QED_DMAE_FLAG_RW_REPL_SRC);
264
+				 addr, fill_count, &params);
221265 }
222266 
223267 static void qed_init_fill(struct qed_hwfn *p_hwfn,
....@@ -489,10 +533,10 @@
489533 int qed_init_run(struct qed_hwfn *p_hwfn,
490534 		 struct qed_ptt *p_ptt, int phase, int phase_id, int modes)
491535 {
536
+	bool b_dmae = (phase != PHASE_ENGINE);
492537 	struct qed_dev *cdev = p_hwfn->cdev;
493538 	u32 cmd_num, num_init_ops;
494539 	union init_op *init_ops;
495
-	bool b_dmae = false;
496540 	int rc = 0;
497541 
498542 	num_init_ops = cdev->fw_data->init_ops_size;
....@@ -521,7 +565,6 @@
521565 		case INIT_OP_IF_PHASE:
522566 			cmd_num += qed_init_cmd_phase(p_hwfn, &cmd->if_phase,
523567 						      phase, phase_id);
524
-			b_dmae = GET_FIELD(data, INIT_IF_PHASE_OP_DMAE_ENABLE);
525568 			break;
526569 		case INIT_OP_DELAY:
527570 			/* qed_init_run is always invoked from
....@@ -532,6 +575,9 @@
532575 
533576 		case INIT_OP_CALLBACK:
534577 			rc = qed_init_cmd_cb(p_hwfn, p_ptt, &cmd->callback);
578
+			if (phase == PHASE_ENGINE &&
579
+			    cmd->callback.callback_id == DMAE_READY_CB)
580
+				b_dmae = true;
535581 			break;
536582 		}
537583 
....@@ -586,5 +632,10 @@
586632 	len = buf_hdr[BIN_BUF_INIT_CMD].length;
587633 	fw->init_ops_size = len / sizeof(struct init_raw_op);
588634 
635
+	offset = buf_hdr[BIN_BUF_INIT_OVERLAYS].offset;
636
+	fw->fw_overlays = (u32 *)(data + offset);
637
+	len = buf_hdr[BIN_BUF_INIT_OVERLAYS].length;
638
+	fw->fw_overlays_len = len;
639
+
589640 	return 0;
590641 }