forked from ~ljy/RK356X_SDK_RELEASE
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hc
2024-05-10 9999e48639b3cecb08ffb37358bcba3b48161b29 
 kernel/drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h
....@@ -87,6 +87,7 @@
8787 	FW_ULPTX_WR                    = 0x04,
8888 	FW_TP_WR                       = 0x05,
8989 	FW_ETH_TX_PKT_WR               = 0x08,
90
+	FW_ETH_TX_EO_WR                = 0x1c,
9091 	FW_OFLD_CONNECTION_WR          = 0x2f,
9192 	FW_FLOWC_WR                    = 0x0a,
9293 	FW_OFLD_TX_DATA_WR             = 0x0b,
....@@ -534,6 +535,47 @@
534535 	__be64 r3;
535536 };
536537 
538
+enum fw_eth_tx_eo_type {
539
+	FW_ETH_TX_EO_TYPE_UDPSEG = 0,
540
+	FW_ETH_TX_EO_TYPE_TCPSEG,
541
+};
542
+
543
+struct fw_eth_tx_eo_wr {
544
+	__be32 op_immdlen;
545
+	__be32 equiq_to_len16;
546
+	__be64 r3;
547
+	union fw_eth_tx_eo {
548
+		struct fw_eth_tx_eo_udpseg {
549
+			__u8   type;
550
+			__u8   ethlen;
551
+			__be16 iplen;
552
+			__u8   udplen;
553
+			__u8   rtplen;
554
+			__be16 r4;
555
+			__be16 mss;
556
+			__be16 schedpktsize;
557
+			__be32 plen;
558
+		} udpseg;
559
+		struct fw_eth_tx_eo_tcpseg {
560
+			__u8   type;
561
+			__u8   ethlen;
562
+			__be16 iplen;
563
+			__u8   tcplen;
564
+			__u8   tsclk_tsoff;
565
+			__be16 r4;
566
+			__be16 mss;
567
+			__be16 r5;
568
+			__be32 plen;
569
+		} tcpseg;
570
+	} u;
571
+};
572
+
573
+#define FW_ETH_TX_EO_WR_IMMDLEN_S	0
574
+#define FW_ETH_TX_EO_WR_IMMDLEN_M	0x1ff
575
+#define FW_ETH_TX_EO_WR_IMMDLEN_V(x)	((x) << FW_ETH_TX_EO_WR_IMMDLEN_S)
576
+#define FW_ETH_TX_EO_WR_IMMDLEN_G(x)	\
577
+	(((x) >> FW_ETH_TX_EO_WR_IMMDLEN_S) & FW_ETH_TX_EO_WR_IMMDLEN_M)
578
+
537579 struct fw_ofld_connection_wr {
538580 	__be32 op_compl;
539581 	__be32 len16_pkd;
....@@ -660,6 +702,12 @@
660702 	FW_FLOWC_MNEM_TCPSTATE_TIMEWAIT = 10, /* not expected */
661703 };
662704 
705
+enum fw_flowc_mnem_eostate {
706
+	FW_FLOWC_MNEM_EOSTATE_ESTABLISHED = 1, /* default */
707
+	/* graceful close, after sending outstanding payload */
708
+	FW_FLOWC_MNEM_EOSTATE_CLOSING = 2,
709
+};
710
+
663711 enum fw_flowc_mnem {
664712 	FW_FLOWC_MNEM_PFNVFN,		/* PFN [15:8] VFN [7:0] */
665713 	FW_FLOWC_MNEM_CH,
....@@ -689,7 +737,7 @@
689737 struct fw_flowc_wr {
690738 	__be32 op_to_nparams;
691739 	__be32 flowid_len16;
692
-	struct fw_flowc_mnemval mnemval[0];
740
+	struct fw_flowc_mnemval mnemval[];
693741 };
694742 
695743 #define FW_FLOWC_WR_NPARAMS_S           0
....@@ -1134,6 +1182,7 @@
11341182 	FW_CAPS_CONFIG_NIC		= 0x00000001,
11351183 	FW_CAPS_CONFIG_NIC_VM		= 0x00000002,
11361184 	FW_CAPS_CONFIG_NIC_HASHFILTER	= 0x00000020,
1185
+	FW_CAPS_CONFIG_NIC_ETHOFLD	= 0x00000040,
11371186 };
11381187 
11391188 enum fw_caps_config_ofld {
....@@ -1156,6 +1205,7 @@
11561205 	FW_CAPS_CONFIG_CRYPTO_LOOKASIDE = 0x00000001,
11571206 	FW_CAPS_CONFIG_TLS_INLINE = 0x00000002,
11581207 	FW_CAPS_CONFIG_IPSEC_INLINE = 0x00000004,
1208
+	FW_CAPS_CONFIG_TLS_HW = 0x00000008,
11591209 };
11601210 
11611211 enum fw_caps_config_fcoe {
....@@ -1221,6 +1271,23 @@
12211271 /*
12221272  * device parameters
12231273  */
1274
+
1275
+#define FW_PARAMS_PARAM_FILTER_MODE_S 16
1276
+#define FW_PARAMS_PARAM_FILTER_MODE_M 0xffff
1277
+#define FW_PARAMS_PARAM_FILTER_MODE_V(x)          \
1278
+	((x) << FW_PARAMS_PARAM_FILTER_MODE_S)
1279
+#define FW_PARAMS_PARAM_FILTER_MODE_G(x)          \
1280
+	(((x) >> FW_PARAMS_PARAM_FILTER_MODE_S) & \
1281
+	FW_PARAMS_PARAM_FILTER_MODE_M)
1282
+
1283
+#define FW_PARAMS_PARAM_FILTER_MASK_S 0
1284
+#define FW_PARAMS_PARAM_FILTER_MASK_M 0xffff
1285
+#define FW_PARAMS_PARAM_FILTER_MASK_V(x)          \
1286
+	((x) << FW_PARAMS_PARAM_FILTER_MASK_S)
1287
+#define FW_PARAMS_PARAM_FILTER_MASK_G(x)          \
1288
+	(((x) >> FW_PARAMS_PARAM_FILTER_MASK_S) & \
1289
+	FW_PARAMS_PARAM_FILTER_MASK_M)
1290
+
12241291 enum fw_params_param_dev {
12251292 	FW_PARAMS_PARAM_DEV_CCLK	= 0x00, /* chip core clock in khz */
12261293 	FW_PARAMS_PARAM_DEV_PORTVEC	= 0x01, /* the port vector */
....@@ -1250,9 +1317,19 @@
12501317 	FW_PARAMS_PARAM_DEV_RI_FR_NSMR_TPTE_WR	= 0x1C,
12511318 	FW_PARAMS_PARAM_DEV_FILTER2_WR  = 0x1D,
12521319 	FW_PARAMS_PARAM_DEV_MPSBGMAP	= 0x1E,
1320
+	FW_PARAMS_PARAM_DEV_TPCHMAP     = 0x1F,
12531321 	FW_PARAMS_PARAM_DEV_HMA_SIZE	= 0x20,
12541322 	FW_PARAMS_PARAM_DEV_RDMA_WRITE_WITH_IMM = 0x21,
1323
+	FW_PARAMS_PARAM_DEV_PPOD_EDRAM  = 0x23,
12551324 	FW_PARAMS_PARAM_DEV_RI_WRITE_CMPL_WR    = 0x24,
1325
+	FW_PARAMS_PARAM_DEV_HPFILTER_REGION_SUPPORT = 0x26,
1326
+	FW_PARAMS_PARAM_DEV_OPAQUE_VIID_SMT_EXTN = 0x27,
1327
+	FW_PARAMS_PARAM_DEV_HASHFILTER_WITH_OFLD = 0x28,
1328
+	FW_PARAMS_PARAM_DEV_DBQ_TIMER	= 0x29,
1329
+	FW_PARAMS_PARAM_DEV_DBQ_TIMERTICK = 0x2A,
1330
+	FW_PARAMS_PARAM_DEV_NUM_TM_CLASS = 0x2B,
1331
+	FW_PARAMS_PARAM_DEV_FILTER = 0x2E,
1332
+	FW_PARAMS_PARAM_DEV_KTLS_HW = 0x31,
12561333 };
12571334 
12581335 /*
....@@ -1309,6 +1386,16 @@
13091386 	FW_PARAMS_PARAM_PFVF_RAWF_END = 0x37,
13101387 	FW_PARAMS_PARAM_PFVF_NCRYPTO_LOOKASIDE = 0x39,
13111388 	FW_PARAMS_PARAM_PFVF_PORT_CAPS32 = 0x3A,
1389
+	FW_PARAMS_PARAM_PFVF_PPOD_EDRAM_START = 0x3B,
1390
+	FW_PARAMS_PARAM_PFVF_PPOD_EDRAM_END = 0x3C,
1391
+	FW_PARAMS_PARAM_PFVF_LINK_STATE = 0x40,
1392
+};
1393
+
1394
+/* Virtual link state as seen by the specified VF */
1395
+enum vf_link_states {
1396
+	FW_VF_LINK_STATE_AUTO		= 0x00,
1397
+	FW_VF_LINK_STATE_ENABLE		= 0x01,
1398
+	FW_VF_LINK_STATE_DISABLE	= 0x02,
13121399 };
13131400 
13141401 /*
....@@ -1321,7 +1408,14 @@
13211408 	FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11,
13221409 	FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12,
13231410 	FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH = 0x13,
1411
+	FW_PARAMS_PARAM_DMAQ_EQ_TIMERIX	= 0x15,
13241412 	FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20,
1413
+};
1414
+
1415
+enum fw_params_param_dev_ktls_hw {
1416
+	FW_PARAMS_PARAM_DEV_KTLS_HW_DISABLE      = 0x00,
1417
+	FW_PARAMS_PARAM_DEV_KTLS_HW_ENABLE       = 0x01,
1418
+	FW_PARAMS_PARAM_DEV_KTLS_HW_USER_ENABLE  = 0x01,
13251419 };
13261420 
13271421 enum fw_params_param_dev_phyfw {
....@@ -1332,6 +1426,12 @@
13321426 enum fw_params_param_dev_diag {
13331427 	FW_PARAM_DEV_DIAG_TMP		= 0x00,
13341428 	FW_PARAM_DEV_DIAG_VDD		= 0x01,
1429
+	FW_PARAM_DEV_DIAG_MAXTMPTHRESH	= 0x02,
1430
+};
1431
+
1432
+enum fw_params_param_dev_filter {
1433
+	FW_PARAM_DEV_FILTER_VNIC_MODE   = 0x00,
1434
+	FW_PARAM_DEV_FILTER_MODE_MASK   = 0x01,
13351435 };
13361436 
13371437 enum fw_params_param_dev_fwcache {
....@@ -1749,8 +1849,8 @@
17491849 	__be32 fetchszm_to_iqid;
17501850 	__be32 dcaen_to_eqsize;
17511851 	__be64 eqaddr;
1752
-	__be32 viid_pkd;
1753
-	__be32 r8_lo;
1852
+	__be32 autoequiqe_to_viid;
1853
+	__be32 timeren_timerix;
17541854 	__be64 r9;
17551855 };
17561856 
....@@ -1845,12 +1945,29 @@
18451945 #define FW_EQ_ETH_CMD_EQSIZE_S		0
18461946 #define FW_EQ_ETH_CMD_EQSIZE_V(x)	((x) << FW_EQ_ETH_CMD_EQSIZE_S)
18471947 
1948
+#define FW_EQ_ETH_CMD_AUTOEQUIQE_S	31
1949
+#define FW_EQ_ETH_CMD_AUTOEQUIQE_V(x)	((x) << FW_EQ_ETH_CMD_AUTOEQUIQE_S)
1950
+#define FW_EQ_ETH_CMD_AUTOEQUIQE_F	FW_EQ_ETH_CMD_AUTOEQUIQE_V(1U)
1951
+
18481952 #define FW_EQ_ETH_CMD_AUTOEQUEQE_S	30
18491953 #define FW_EQ_ETH_CMD_AUTOEQUEQE_V(x)	((x) << FW_EQ_ETH_CMD_AUTOEQUEQE_S)
18501954 #define FW_EQ_ETH_CMD_AUTOEQUEQE_F	FW_EQ_ETH_CMD_AUTOEQUEQE_V(1U)
18511955 
18521956 #define FW_EQ_ETH_CMD_VIID_S	16
18531957 #define FW_EQ_ETH_CMD_VIID_V(x)	((x) << FW_EQ_ETH_CMD_VIID_S)
1958
+
1959
+#define FW_EQ_ETH_CMD_TIMEREN_S		3
1960
+#define FW_EQ_ETH_CMD_TIMEREN_M		0x1
1961
+#define FW_EQ_ETH_CMD_TIMEREN_V(x)	((x) << FW_EQ_ETH_CMD_TIMEREN_S)
1962
+#define FW_EQ_ETH_CMD_TIMEREN_G(x)	\
1963
+    (((x) >> FW_EQ_ETH_CMD_TIMEREN_S) & FW_EQ_ETH_CMD_TIMEREN_M)
1964
+#define FW_EQ_ETH_CMD_TIMEREN_F	FW_EQ_ETH_CMD_TIMEREN_V(1U)
1965
+
1966
+#define FW_EQ_ETH_CMD_TIMERIX_S		0
1967
+#define FW_EQ_ETH_CMD_TIMERIX_M		0x7
1968
+#define FW_EQ_ETH_CMD_TIMERIX_V(x)	((x) << FW_EQ_ETH_CMD_TIMERIX_S)
1969
+#define FW_EQ_ETH_CMD_TIMERIX_G(x)	\
1970
+    (((x) >> FW_EQ_ETH_CMD_TIMERIX_S) & FW_EQ_ETH_CMD_TIMERIX_M)
18541971 
18551972 struct fw_eq_ctrl_cmd {
18561973 	__be32 op_to_vfn;
....@@ -2108,6 +2225,19 @@
21082225 #define FW_VI_CMD_FREE_V(x)	((x) << FW_VI_CMD_FREE_S)
21092226 #define FW_VI_CMD_FREE_F	FW_VI_CMD_FREE_V(1U)
21102227 
2228
+#define FW_VI_CMD_VFVLD_S	24
2229
+#define FW_VI_CMD_VFVLD_M	0x1
2230
+#define FW_VI_CMD_VFVLD_V(x)	((x) << FW_VI_CMD_VFVLD_S)
2231
+#define FW_VI_CMD_VFVLD_G(x)	\
2232
+	(((x) >> FW_VI_CMD_VFVLD_S) & FW_VI_CMD_VFVLD_M)
2233
+#define FW_VI_CMD_VFVLD_F	FW_VI_CMD_VFVLD_V(1U)
2234
+
2235
+#define FW_VI_CMD_VIN_S		16
2236
+#define FW_VI_CMD_VIN_M		0xff
2237
+#define FW_VI_CMD_VIN_V(x)	((x) << FW_VI_CMD_VIN_S)
2238
+#define FW_VI_CMD_VIN_G(x)	\
2239
+	(((x) >> FW_VI_CMD_VIN_S) & FW_VI_CMD_VIN_M)
2240
+
21112241 #define FW_VI_CMD_VIID_S	0
21122242 #define FW_VI_CMD_VIID_M	0xfff
21132243 #define FW_VI_CMD_VIID_V(x)	((x) << FW_VI_CMD_VIID_S)
....@@ -2180,6 +2310,12 @@
21802310 		} exact_vni[2];
21812311 	} u;
21822312 };
2313
+
2314
+#define FW_VI_MAC_CMD_SMTID_S		12
2315
+#define FW_VI_MAC_CMD_SMTID_M		0xff
2316
+#define FW_VI_MAC_CMD_SMTID_V(x)	((x) << FW_VI_MAC_CMD_SMTID_S)
2317
+#define FW_VI_MAC_CMD_SMTID_G(x)	\
2318
+	(((x) >> FW_VI_MAC_CMD_SMTID_S) & FW_VI_MAC_CMD_SMTID_M)
21832319 
21842320 #define FW_VI_MAC_CMD_VIID_S	0
21852321 #define FW_VI_MAC_CMD_VIID_V(x)	((x) << FW_VI_MAC_CMD_VIID_S)
....@@ -2464,6 +2600,7 @@
24642600 
24652601 #define FW_ACL_VLAN_CMD_DROPNOVLAN_S	7
24662602 #define FW_ACL_VLAN_CMD_DROPNOVLAN_V(x)	((x) << FW_ACL_VLAN_CMD_DROPNOVLAN_S)
2603
+#define FW_ACL_VLAN_CMD_DROPNOVLAN_F    FW_ACL_VLAN_CMD_DROPNOVLAN_V(1U)
24672604 
24682605 #define FW_ACL_VLAN_CMD_FM_S		6
24692606 #define FW_ACL_VLAN_CMD_FM_M		0x1