forked from ~ljy/RK356X_SDK_RELEASE
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hc
2024-05-10 9999e48639b3cecb08ffb37358bcba3b48161b29 
 kernel/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c
....@@ -837,49 +837,45 @@
837837 
838838 	switch (cos_entry) {
839839 	case 0:
840
-	    nig_reg_adress_crd_weight =
841
-		 (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
842
-		     NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0;
843
-	     pbf_reg_adress_crd_weight = (port) ?
844
-		 PBF_REG_COS0_WEIGHT_P1 : PBF_REG_COS0_WEIGHT_P0;
845
-	     break;
840
+		nig_reg_adress_crd_weight =
841
+			(port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
842
+			NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0;
843
+		pbf_reg_adress_crd_weight = (port) ?
844
+		    PBF_REG_COS0_WEIGHT_P1 : PBF_REG_COS0_WEIGHT_P0;
845
+		break;
846846 	case 1:
847
-	     nig_reg_adress_crd_weight = (port) ?
848
-		 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
849
-		 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1;
850
-	     pbf_reg_adress_crd_weight = (port) ?
851
-		 PBF_REG_COS1_WEIGHT_P1 : PBF_REG_COS1_WEIGHT_P0;
852
-	     break;
847
+		nig_reg_adress_crd_weight = (port) ?
848
+			NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
849
+			NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1;
850
+		pbf_reg_adress_crd_weight = (port) ?
851
+			PBF_REG_COS1_WEIGHT_P1 : PBF_REG_COS1_WEIGHT_P0;
852
+		break;
853853 	case 2:
854
-	     nig_reg_adress_crd_weight = (port) ?
855
-		 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
856
-		 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2;
854
+		nig_reg_adress_crd_weight = (port) ?
855
+			NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
856
+			NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2;
857857 
858
-		 pbf_reg_adress_crd_weight = (port) ?
859
-		     PBF_REG_COS2_WEIGHT_P1 : PBF_REG_COS2_WEIGHT_P0;
860
-	     break;
858
+		pbf_reg_adress_crd_weight = (port) ?
859
+			PBF_REG_COS2_WEIGHT_P1 : PBF_REG_COS2_WEIGHT_P0;
860
+		break;
861861 	case 3:
862
-	    if (port)
862
+		if (port)
863863 			return -EINVAL;
864
-	     nig_reg_adress_crd_weight =
865
-		 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3;
866
-	     pbf_reg_adress_crd_weight =
867
-		 PBF_REG_COS3_WEIGHT_P0;
868
-	     break;
864
+		nig_reg_adress_crd_weight = NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3;
865
+		pbf_reg_adress_crd_weight = PBF_REG_COS3_WEIGHT_P0;
866
+		break;
869867 	case 4:
870
-	    if (port)
871
-		return -EINVAL;
872
-	     nig_reg_adress_crd_weight =
873
-		 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4;
874
-	     pbf_reg_adress_crd_weight = PBF_REG_COS4_WEIGHT_P0;
875
-	     break;
868
+		if (port)
869
+			return -EINVAL;
870
+		nig_reg_adress_crd_weight = NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4;
871
+		pbf_reg_adress_crd_weight = PBF_REG_COS4_WEIGHT_P0;
872
+		break;
876873 	case 5:
877
-	    if (port)
878
-		return -EINVAL;
879
-	     nig_reg_adress_crd_weight =
880
-		 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5;
881
-	     pbf_reg_adress_crd_weight = PBF_REG_COS5_WEIGHT_P0;
882
-	     break;
874
+		if (port)
875
+			return -EINVAL;
876
+		nig_reg_adress_crd_weight = NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5;
877
+		pbf_reg_adress_crd_weight = PBF_REG_COS5_WEIGHT_P0;
878
+		break;
883879 	}
884880 
885881 	REG_WR(bp, nig_reg_adress_crd_weight, cos_bw_nig);
....@@ -966,7 +962,7 @@
966962 	if (pri >= max_num_of_cos) {
967963 		DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid "
968964 		   "parameter Illegal strict priority\n");
969
-	    return -EINVAL;
965
+		return -EINVAL;
970966 	}
971967 
972968 	if (sp_pri_to_cos[pri] != DCBX_INVALID_COS) {
....@@ -1845,28 +1841,28 @@
18451841 	bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
18461842 		      EMAC_TX_MODE_RESET);
18471843 
1848
-		/* pause enable/disable */
1849
-		bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
1850
-			       EMAC_RX_MODE_FLOW_EN);
1844
+	/* pause enable/disable */
1845
+	bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
1846
+		       EMAC_RX_MODE_FLOW_EN);
18511847 
1852
-		bnx2x_bits_dis(bp,  emac_base + EMAC_REG_EMAC_TX_MODE,
1853
-			       (EMAC_TX_MODE_EXT_PAUSE_EN |
1854
-				EMAC_TX_MODE_FLOW_EN));
1855
-		if (!(params->feature_config_flags &
1856
-		      FEATURE_CONFIG_PFC_ENABLED)) {
1857
-			if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1858
-				bnx2x_bits_en(bp, emac_base +
1859
-					      EMAC_REG_EMAC_RX_MODE,
1860
-					      EMAC_RX_MODE_FLOW_EN);
1848
+	bnx2x_bits_dis(bp,  emac_base + EMAC_REG_EMAC_TX_MODE,
1849
+		       (EMAC_TX_MODE_EXT_PAUSE_EN |
1850
+			EMAC_TX_MODE_FLOW_EN));
1851
+	if (!(params->feature_config_flags &
1852
+	      FEATURE_CONFIG_PFC_ENABLED)) {
1853
+		if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1854
+			bnx2x_bits_en(bp, emac_base +
1855
+				      EMAC_REG_EMAC_RX_MODE,
1856
+				      EMAC_RX_MODE_FLOW_EN);
18611857 
1862
-			if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1863
-				bnx2x_bits_en(bp, emac_base +
1864
-					      EMAC_REG_EMAC_TX_MODE,
1865
-					      (EMAC_TX_MODE_EXT_PAUSE_EN |
1866
-					       EMAC_TX_MODE_FLOW_EN));
1867
-		} else
1868
-			bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1869
-				      EMAC_TX_MODE_FLOW_EN);
1858
+		if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1859
+			bnx2x_bits_en(bp, emac_base +
1860
+				      EMAC_REG_EMAC_TX_MODE,
1861
+				      (EMAC_TX_MODE_EXT_PAUSE_EN |
1862
+				       EMAC_TX_MODE_FLOW_EN));
1863
+	} else
1864
+		bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1865
+			      EMAC_TX_MODE_FLOW_EN);
18701866 
18711867 	/* KEEP_VLAN_TAG, promiscuous */
18721868 	val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);
....@@ -3089,6 +3085,7 @@
30893085 			  u8 xfer_cnt,
30903086 			  u32 *data_array)
30913087 {
3088
+	u64 t0, delta;
30923089 	u32 val, i;
30933090 	int rc = 0;
30943091 
....@@ -3118,17 +3115,18 @@
31183115 	REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
31193116 
31203117 	/* Poll for completion */
3121
-	i = 0;
3118
+	t0 = ktime_get_ns();
31223119 	val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
31233120 	while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3124
-		udelay(10);
3125
-		val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3126
-		if (i++ > 1000) {
3127
-			DP(NETIF_MSG_LINK, "wr 0 byte timed out after %d try\n",
3128
-								i);
3121
+		delta = ktime_get_ns() - t0;
3122
+		if (delta > 10 * NSEC_PER_MSEC) {
3123
+			DP(NETIF_MSG_LINK, "wr 0 byte timed out after %Lu ns\n",
3124
+					   delta);
31293125 			rc = -EFAULT;
31303126 			break;
31313127 		}
3128
+		usleep_range(10, 20);
3129
+		val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
31323130 	}
31333131 	if (rc == -EFAULT)
31343132 		return rc;
....@@ -3142,16 +3140,18 @@
31423140 	REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
31433141 
31443142 	/* Poll for completion */
3145
-	i = 0;
3143
+	t0 = ktime_get_ns();
31463144 	val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
31473145 	while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3148
-		udelay(10);
3149
-		val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3150
-		if (i++ > 1000) {
3151
-			DP(NETIF_MSG_LINK, "rd op timed out after %d try\n", i);
3146
+		delta = ktime_get_ns() - t0;
3147
+		if (delta > 10 * NSEC_PER_MSEC) {
3148
+			DP(NETIF_MSG_LINK, "rd op timed out after %Lu ns\n",
3149
+					   delta);
31523150 			rc = -EFAULT;
31533151 			break;
31543152 		}
3153
+		usleep_range(10, 20);
3154
+		val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
31553155 	}
31563156 	if (rc == -EFAULT)
31573157 		return rc;
....@@ -4712,14 +4712,14 @@
47124712 			LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
47134713 		case LINK_10THD:
47144714 			vars->duplex = DUPLEX_HALF;
4715
-			/* Fall thru */
4715
+			fallthrough;
47164716 		case LINK_10TFD:
47174717 			vars->line_speed = SPEED_10;
47184718 			break;
47194719 
47204720 		case LINK_100TXHD:
47214721 			vars->duplex = DUPLEX_HALF;
4722
-			/* Fall thru */
4722
+			fallthrough;
47234723 		case LINK_100T4:
47244724 		case LINK_100TXFD:
47254725 			vars->line_speed = SPEED_100;
....@@ -4727,14 +4727,14 @@
47274727 
47284728 		case LINK_1000THD:
47294729 			vars->duplex = DUPLEX_HALF;
4730
-			/* Fall thru */
4730
+			fallthrough;
47314731 		case LINK_1000TFD:
47324732 			vars->line_speed = SPEED_1000;
47334733 			break;
47344734 
47354735 		case LINK_2500THD:
47364736 			vars->duplex = DUPLEX_HALF;
4737
-			/* Fall thru */
4737
+			fallthrough;
47384738 		case LINK_2500TFD:
47394739 			vars->line_speed = SPEED_2500;
47404740 			break;
....@@ -5615,9 +5615,9 @@
56155615 	return 0;
56165616 }
56175617 
5618
-static int bnx2x_link_settings_status(struct bnx2x_phy *phy,
5619
-				      struct link_params *params,
5620
-				      struct link_vars *vars)
5618
+static u8 bnx2x_link_settings_status(struct bnx2x_phy *phy,
5619
+				     struct link_params *params,
5620
+				     struct link_vars *vars)
56215621 {
56225622 	struct bnx2x *bp = params->bp;
56235623 
....@@ -5689,7 +5689,7 @@
56895689 	return rc;
56905690 }
56915691 
5692
-static int bnx2x_warpcore_read_status(struct bnx2x_phy *phy,
5692
+static u8 bnx2x_warpcore_read_status(struct bnx2x_phy *phy,
56935693 				     struct link_params *params,
56945694 				     struct link_vars *vars)
56955695 {
....@@ -6339,7 +6339,7 @@
63396339 		 */
63406340 		if (!vars->link_up)
63416341 			break;
6342
-		/* else: fall through */
6342
+		fallthrough;
63436343 	case LED_MODE_ON:
63446344 		if (((params->phy[EXT_PHY1].type ==
63456345 			  PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) ||
....@@ -6478,9 +6478,9 @@
64786478 			  MDIO_REG_BANK_GP_STATUS,
64796479 			  MDIO_GP_STATUS_TOP_AN_STATUS1,
64806480 			  &gp_status);
6481
-	/* Link is up only if both local phy and external phy are up */
6482
-	if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS))
6483
-		return -ESRCH;
6481
+		/* Link is up only if both local phy and external phy are up */
6482
+		if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS))
6483
+			return -ESRCH;
64846484 	}
64856485 	/* In XGXS loopback mode, do not check external PHY */
64866486 	if (params->loopback_mode == LOOPBACK_XGXS)
....@@ -6878,7 +6878,8 @@
68786878 			case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
68796879 			/* In this option, the first PHY makes sure to pass the
68806880 			 * traffic through itself only.
6881
-			 * Its not clear how to reset the link on the second phy
6881
+			 * It's not clear how to reset the link on the second
6882
+			 * phy.
68826883 			 */
68836884 				active_external_phy = EXT_PHY1;
68846885 				break;
....@@ -7293,8 +7294,8 @@
72937294 					DP(NETIF_MSG_LINK,
72947295 					  "XAUI workaround has completed\n");
72957296 					return 0;
7296
-				 }
7297
-				 usleep_range(3000, 6000);
7297
+				}
7298
+				usleep_range(3000, 6000);
72987299 			}
72997300 			break;
73007301 		}
....@@ -7368,9 +7369,9 @@
73687369 	}
73697370 }
73707371 
7371
-static int bnx2x_8073_config_init(struct bnx2x_phy *phy,
7372
-				  struct link_params *params,
7373
-				  struct link_vars *vars)
7372
+static void bnx2x_8073_config_init(struct bnx2x_phy *phy,
7373
+				   struct link_params *params,
7374
+				   struct link_vars *vars)
73747375 {
73757376 	struct bnx2x *bp = params->bp;
73767377 	u16 val = 0, tmp1;
....@@ -7431,7 +7432,7 @@
74317432 	if (params->loopback_mode == LOOPBACK_EXT) {
74327433 		bnx2x_807x_force_10G(bp, phy);
74337434 		DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n");
7434
-		return 0;
7435
+		return;
74357436 	} else {
74367437 		bnx2x_cl45_write(bp, phy,
74377438 				 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002);
....@@ -7513,7 +7514,6 @@
75137514 	bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
75147515 	DP(NETIF_MSG_LINK, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n",
75157516 		   ((val & (1<<5)) > 0), ((val & (1<<7)) > 0));
7516
-	return 0;
75177517 }
75187518 
75197519 static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy,
....@@ -7680,9 +7680,9 @@
76807680 /******************************************************************/
76817681 /*			BCM8705 PHY SECTION			  */
76827682 /******************************************************************/
7683
-static int bnx2x_8705_config_init(struct bnx2x_phy *phy,
7684
-				  struct link_params *params,
7685
-				  struct link_vars *vars)
7683
+static void bnx2x_8705_config_init(struct bnx2x_phy *phy,
7684
+				   struct link_params *params,
7685
+				   struct link_vars *vars)
76867686 {
76877687 	struct bnx2x *bp = params->bp;
76887688 	DP(NETIF_MSG_LINK, "init 8705\n");
....@@ -7704,7 +7704,6 @@
77047704 			 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1);
77057705 	/* BCM8705 doesn't have microcode, hence the 0 */
77067706 	bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0);
7707
-	return 0;
77087707 }
77097708 
77107709 static u8 bnx2x_8705_read_status(struct bnx2x_phy *phy,
....@@ -8891,9 +8890,9 @@
88918890 /******************************************************************/
88928891 /*			BCM8706 PHY SECTION			  */
88938892 /******************************************************************/
8894
-static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy,
8895
-				 struct link_params *params,
8896
-				 struct link_vars *vars)
8893
+static void bnx2x_8706_config_init(struct bnx2x_phy *phy,
8894
+				   struct link_params *params,
8895
+				   struct link_vars *vars)
88978896 {
88988897 	u32 tx_en_mode;
88998898 	u16 cnt, val, tmp1;
....@@ -8993,13 +8992,11 @@
89938992 		bnx2x_cl45_write(bp, phy,
89948993 			MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, tmp1);
89958994 	}
8996
-
8997
-	return 0;
89988995 }
89998996 
9000
-static int bnx2x_8706_read_status(struct bnx2x_phy *phy,
9001
-				  struct link_params *params,
9002
-				  struct link_vars *vars)
8997
+static u8 bnx2x_8706_read_status(struct bnx2x_phy *phy,
8998
+				 struct link_params *params,
8999
+				 struct link_vars *vars)
90039000 {
90049001 	return bnx2x_8706_8726_read_status(phy, params, vars);
90059002 }
....@@ -9074,9 +9071,9 @@
90749071 }
90759072 
90769073 
9077
-static int bnx2x_8726_config_init(struct bnx2x_phy *phy,
9078
-				  struct link_params *params,
9079
-				  struct link_vars *vars)
9074
+static void bnx2x_8726_config_init(struct bnx2x_phy *phy,
9075
+				   struct link_params *params,
9076
+				   struct link_vars *vars)
90809077 {
90819078 	struct bnx2x *bp = params->bp;
90829079 	DP(NETIF_MSG_LINK, "Initializing BCM8726\n");
....@@ -9154,9 +9151,6 @@
91549151 				 MDIO_PMA_REG_8726_TX_CTRL2,
91559152 				 phy->tx_preemphasis[1]);
91569153 	}
9157
-
9158
-	return 0;
9159
-
91609154 }
91619155 
91629156 static void bnx2x_8726_link_reset(struct bnx2x_phy *phy,
....@@ -9292,9 +9286,9 @@
92929286 	}
92939287 }
92949288 
9295
-static int bnx2x_8727_config_init(struct bnx2x_phy *phy,
9296
-				  struct link_params *params,
9297
-				  struct link_vars *vars)
9289
+static void bnx2x_8727_config_init(struct bnx2x_phy *phy,
9290
+				   struct link_params *params,
9291
+				   struct link_vars *vars)
92989292 {
92999293 	u32 tx_en_mode;
93009294 	u16 tmp1, mod_abs, tmp2;
....@@ -9374,8 +9368,6 @@
93749368 				 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
93759369 				 (tmp2 & 0x7fff));
93769370 	}
9377
-
9378
-	return 0;
93799371 }
93809372 
93819373 static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy,
....@@ -9950,9 +9942,9 @@
99509942 	return 0;
99519943 }
99529944 
9953
-static int bnx2x_8481_config_init(struct bnx2x_phy *phy,
9954
-				  struct link_params *params,
9955
-				  struct link_vars *vars)
9945
+static void bnx2x_8481_config_init(struct bnx2x_phy *phy,
9946
+				   struct link_params *params,
9947
+				   struct link_vars *vars)
99569948 {
99579949 	struct bnx2x *bp = params->bp;
99589950 	/* Restore normal power mode*/
....@@ -9964,7 +9956,7 @@
99649956 	bnx2x_wait_reset_complete(bp, phy, params);
99659957 
99669958 	bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
9967
-	return bnx2x_848xx_cmn_config_init(phy, params, vars);
9959
+	bnx2x_848xx_cmn_config_init(phy, params, vars);
99689960 }
99699961 
99709962 #define PHY848xx_CMDHDLR_WAIT 300
....@@ -10214,8 +10206,8 @@
1021410206 	return reset_gpios;
1021510207 }
1021610208 
10217
-static int bnx2x_84833_hw_reset_phy(struct bnx2x_phy *phy,
10218
-				struct link_params *params)
10209
+static void bnx2x_84833_hw_reset_phy(struct bnx2x_phy *phy,
10210
+				     struct link_params *params)
1021910211 {
1022010212 	struct bnx2x *bp = params->bp;
1022110213 	u8 reset_gpios;
....@@ -10243,8 +10235,6 @@
1024310235 	udelay(10);
1024410236 	DP(NETIF_MSG_LINK, "84833 hw reset on pin values 0x%x\n",
1024510237 		reset_gpios);
10246
-
10247
-	return 0;
1024810238 }
1024910239 
1025010240 static int bnx2x_8483x_disable_eee(struct bnx2x_phy *phy,
....@@ -10287,9 +10277,9 @@
1028710277 }
1028810278 
1028910279 #define PHY84833_CONSTANT_LATENCY 1193
10290
-static int bnx2x_848x3_config_init(struct bnx2x_phy *phy,
10291
-				   struct link_params *params,
10292
-				   struct link_vars *vars)
10280
+static void bnx2x_848x3_config_init(struct bnx2x_phy *phy,
10281
+				    struct link_params *params,
10282
+				    struct link_vars *vars)
1029310283 {
1029410284 	struct bnx2x *bp = params->bp;
1029510285 	u8 port, initialize = 1;
....@@ -10434,7 +10424,7 @@
1043410424 		if (rc) {
1043510425 			DP(NETIF_MSG_LINK, "Failed to configure EEE timers\n");
1043610426 			bnx2x_8483x_disable_eee(phy, params, vars);
10437
-			return rc;
10427
+			return;
1043810428 		}
1043910429 
1044010430 		if ((phy->req_duplex == DUPLEX_FULL) &&
....@@ -10446,7 +10436,7 @@
1044610436 			rc = bnx2x_8483x_disable_eee(phy, params, vars);
1044710437 		if (rc) {
1044810438 			DP(NETIF_MSG_LINK, "Failed to set EEE advertisement\n");
10449
-			return rc;
10439
+			return;
1045010440 		}
1045110441 	} else {
1045210442 		vars->eee_status &= ~SHMEM_EEE_SUPPORTED_MASK;
....@@ -10485,7 +10475,6 @@
1048510475 					  MDIO_84833_TOP_CFG_XGPHY_STRAP1,
1048610476 					  (u16)~MDIO_84833_SUPER_ISOLATE);
1048710477 	}
10488
-	return rc;
1048910478 }
1049010479 
1049110480 static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy,
....@@ -11042,9 +11031,9 @@
1104211031 	}
1104311032 }
1104411033 
11045
-static int bnx2x_54618se_config_init(struct bnx2x_phy *phy,
11046
-					       struct link_params *params,
11047
-					       struct link_vars *vars)
11034
+static void bnx2x_54618se_config_init(struct bnx2x_phy *phy,
11035
+				      struct link_params *params,
11036
+				      struct link_vars *vars)
1104811037 {
1104911038 	struct bnx2x *bp = params->bp;
1105011039 	u8 port;
....@@ -11244,8 +11233,6 @@
1124411233 
1124511234 	bnx2x_cl22_write(bp, phy,
1124611235 			MDIO_PMA_REG_CTRL, autoneg_val);
11247
-
11248
-	return 0;
1124911236 }
1125011237 
1125111238 
....@@ -11469,9 +11456,9 @@
1146911456 			 MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100);
1147011457 }
1147111458 
11472
-static int bnx2x_7101_config_init(struct bnx2x_phy *phy,
11473
-				  struct link_params *params,
11474
-				  struct link_vars *vars)
11459
+static void bnx2x_7101_config_init(struct bnx2x_phy *phy,
11460
+				   struct link_params *params,
11461
+				   struct link_vars *vars)
1147511462 {
1147611463 	u16 fw_ver1, fw_ver2, val;
1147711464 	struct bnx2x *bp = params->bp;
....@@ -11506,7 +11493,6 @@
1150611493 			MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2);
1150711494 	bnx2x_save_spirom_version(bp, params->port,
1150811495 				  (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr);
11509
-	return 0;
1151011496 }
1151111497 
1151211498 static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy,
....@@ -11640,14 +11626,14 @@
1164011626 	.speed_cap_mask	= 0,
1164111627 	.req_duplex	= 0,
1164211628 	.rsrv		= 0,
11643
-	.config_init	= (config_init_t)NULL,
11644
-	.read_status	= (read_status_t)NULL,
11645
-	.link_reset	= (link_reset_t)NULL,
11646
-	.config_loopback = (config_loopback_t)NULL,
11647
-	.format_fw_ver	= (format_fw_ver_t)NULL,
11648
-	.hw_reset	= (hw_reset_t)NULL,
11649
-	.set_link_led	= (set_link_led_t)NULL,
11650
-	.phy_specific_func = (phy_specific_func_t)NULL
11629
+	.config_init	= NULL,
11630
+	.read_status	= NULL,
11631
+	.link_reset	= NULL,
11632
+	.config_loopback = NULL,
11633
+	.format_fw_ver	= NULL,
11634
+	.hw_reset	= NULL,
11635
+	.set_link_led	= NULL,
11636
+	.phy_specific_func = NULL
1165111637 };
1165211638 
1165311639 static const struct bnx2x_phy phy_serdes = {
....@@ -11675,14 +11661,14 @@
1167511661 	.speed_cap_mask	= 0,
1167611662 	.req_duplex	= 0,
1167711663 	.rsrv		= 0,
11678
-	.config_init	= (config_init_t)bnx2x_xgxs_config_init,
11679
-	.read_status	= (read_status_t)bnx2x_link_settings_status,
11680
-	.link_reset	= (link_reset_t)bnx2x_int_link_reset,
11681
-	.config_loopback = (config_loopback_t)NULL,
11682
-	.format_fw_ver	= (format_fw_ver_t)NULL,
11683
-	.hw_reset	= (hw_reset_t)NULL,
11684
-	.set_link_led	= (set_link_led_t)NULL,
11685
-	.phy_specific_func = (phy_specific_func_t)NULL
11664
+	.config_init	= bnx2x_xgxs_config_init,
11665
+	.read_status	= bnx2x_link_settings_status,
11666
+	.link_reset	= bnx2x_int_link_reset,
11667
+	.config_loopback = NULL,
11668
+	.format_fw_ver	= NULL,
11669
+	.hw_reset	= NULL,
11670
+	.set_link_led	= NULL,
11671
+	.phy_specific_func = NULL
1168611672 };
1168711673 
1168811674 static const struct bnx2x_phy phy_xgxs = {
....@@ -11711,14 +11697,14 @@
1171111697 	.speed_cap_mask	= 0,
1171211698 	.req_duplex	= 0,
1171311699 	.rsrv		= 0,
11714
-	.config_init	= (config_init_t)bnx2x_xgxs_config_init,
11715
-	.read_status	= (read_status_t)bnx2x_link_settings_status,
11716
-	.link_reset	= (link_reset_t)bnx2x_int_link_reset,
11717
-	.config_loopback = (config_loopback_t)bnx2x_set_xgxs_loopback,
11718
-	.format_fw_ver	= (format_fw_ver_t)NULL,
11719
-	.hw_reset	= (hw_reset_t)NULL,
11720
-	.set_link_led	= (set_link_led_t)NULL,
11721
-	.phy_specific_func = (phy_specific_func_t)bnx2x_xgxs_specific_func
11700
+	.config_init	= bnx2x_xgxs_config_init,
11701
+	.read_status	= bnx2x_link_settings_status,
11702
+	.link_reset	= bnx2x_int_link_reset,
11703
+	.config_loopback = bnx2x_set_xgxs_loopback,
11704
+	.format_fw_ver	= NULL,
11705
+	.hw_reset	= NULL,
11706
+	.set_link_led	= NULL,
11707
+	.phy_specific_func = bnx2x_xgxs_specific_func
1172211708 };
1172311709 static const struct bnx2x_phy phy_warpcore = {
1172411710 	.type		= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
....@@ -11749,14 +11735,14 @@
1174911735 	.speed_cap_mask	= 0,
1175011736 	/* req_duplex = */0,
1175111737 	/* rsrv = */0,
11752
-	.config_init	= (config_init_t)bnx2x_warpcore_config_init,
11753
-	.read_status	= (read_status_t)bnx2x_warpcore_read_status,
11754
-	.link_reset	= (link_reset_t)bnx2x_warpcore_link_reset,
11755
-	.config_loopback = (config_loopback_t)bnx2x_set_warpcore_loopback,
11756
-	.format_fw_ver	= (format_fw_ver_t)NULL,
11757
-	.hw_reset	= (hw_reset_t)bnx2x_warpcore_hw_reset,
11758
-	.set_link_led	= (set_link_led_t)NULL,
11759
-	.phy_specific_func = (phy_specific_func_t)NULL
11738
+	.config_init	= bnx2x_warpcore_config_init,
11739
+	.read_status	= bnx2x_warpcore_read_status,
11740
+	.link_reset	= bnx2x_warpcore_link_reset,
11741
+	.config_loopback = bnx2x_set_warpcore_loopback,
11742
+	.format_fw_ver	= NULL,
11743
+	.hw_reset	= bnx2x_warpcore_hw_reset,
11744
+	.set_link_led	= NULL,
11745
+	.phy_specific_func = NULL
1176011746 };
1176111747 
1176211748 
....@@ -11780,14 +11766,14 @@
1178011766 	.speed_cap_mask	= 0,
1178111767 	.req_duplex	= 0,
1178211768 	.rsrv		= 0,
11783
-	.config_init	= (config_init_t)bnx2x_7101_config_init,
11784
-	.read_status	= (read_status_t)bnx2x_7101_read_status,
11785
-	.link_reset	= (link_reset_t)bnx2x_common_ext_link_reset,
11786
-	.config_loopback = (config_loopback_t)bnx2x_7101_config_loopback,
11787
-	.format_fw_ver	= (format_fw_ver_t)bnx2x_7101_format_ver,
11788
-	.hw_reset	= (hw_reset_t)bnx2x_7101_hw_reset,
11789
-	.set_link_led	= (set_link_led_t)bnx2x_7101_set_link_led,
11790
-	.phy_specific_func = (phy_specific_func_t)NULL
11769
+	.config_init	= bnx2x_7101_config_init,
11770
+	.read_status	= bnx2x_7101_read_status,
11771
+	.link_reset	= bnx2x_common_ext_link_reset,
11772
+	.config_loopback = bnx2x_7101_config_loopback,
11773
+	.format_fw_ver	= bnx2x_7101_format_ver,
11774
+	.hw_reset	= bnx2x_7101_hw_reset,
11775
+	.set_link_led	= bnx2x_7101_set_link_led,
11776
+	.phy_specific_func = NULL
1179111777 };
1179211778 static const struct bnx2x_phy phy_8073 = {
1179311779 	.type		= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
....@@ -11811,14 +11797,14 @@
1181111797 	.speed_cap_mask	= 0,
1181211798 	.req_duplex	= 0,
1181311799 	.rsrv		= 0,
11814
-	.config_init	= (config_init_t)bnx2x_8073_config_init,
11815
-	.read_status	= (read_status_t)bnx2x_8073_read_status,
11816
-	.link_reset	= (link_reset_t)bnx2x_8073_link_reset,
11817
-	.config_loopback = (config_loopback_t)NULL,
11818
-	.format_fw_ver	= (format_fw_ver_t)bnx2x_format_ver,
11819
-	.hw_reset	= (hw_reset_t)NULL,
11820
-	.set_link_led	= (set_link_led_t)NULL,
11821
-	.phy_specific_func = (phy_specific_func_t)bnx2x_8073_specific_func
11800
+	.config_init	= bnx2x_8073_config_init,
11801
+	.read_status	= bnx2x_8073_read_status,
11802
+	.link_reset	= bnx2x_8073_link_reset,
11803
+	.config_loopback = NULL,
11804
+	.format_fw_ver	= bnx2x_format_ver,
11805
+	.hw_reset	= NULL,
11806
+	.set_link_led	= NULL,
11807
+	.phy_specific_func = bnx2x_8073_specific_func
1182211808 };
1182311809 static const struct bnx2x_phy phy_8705 = {
1182411810 	.type		= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705,
....@@ -11839,14 +11825,14 @@
1183911825 	.speed_cap_mask	= 0,
1184011826 	.req_duplex	= 0,
1184111827 	.rsrv		= 0,
11842
-	.config_init	= (config_init_t)bnx2x_8705_config_init,
11843
-	.read_status	= (read_status_t)bnx2x_8705_read_status,
11844
-	.link_reset	= (link_reset_t)bnx2x_common_ext_link_reset,
11845
-	.config_loopback = (config_loopback_t)NULL,
11846
-	.format_fw_ver	= (format_fw_ver_t)bnx2x_null_format_ver,
11847
-	.hw_reset	= (hw_reset_t)NULL,
11848
-	.set_link_led	= (set_link_led_t)NULL,
11849
-	.phy_specific_func = (phy_specific_func_t)NULL
11828
+	.config_init	= bnx2x_8705_config_init,
11829
+	.read_status	= bnx2x_8705_read_status,
11830
+	.link_reset	= bnx2x_common_ext_link_reset,
11831
+	.config_loopback = NULL,
11832
+	.format_fw_ver	= bnx2x_null_format_ver,
11833
+	.hw_reset	= NULL,
11834
+	.set_link_led	= NULL,
11835
+	.phy_specific_func = NULL
1185011836 };
1185111837 static const struct bnx2x_phy phy_8706 = {
1185211838 	.type		= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706,
....@@ -11868,14 +11854,14 @@
1186811854 	.speed_cap_mask	= 0,
1186911855 	.req_duplex	= 0,
1187011856 	.rsrv		= 0,
11871
-	.config_init	= (config_init_t)bnx2x_8706_config_init,
11872
-	.read_status	= (read_status_t)bnx2x_8706_read_status,
11873
-	.link_reset	= (link_reset_t)bnx2x_common_ext_link_reset,
11874
-	.config_loopback = (config_loopback_t)NULL,
11875
-	.format_fw_ver	= (format_fw_ver_t)bnx2x_format_ver,
11876
-	.hw_reset	= (hw_reset_t)NULL,
11877
-	.set_link_led	= (set_link_led_t)NULL,
11878
-	.phy_specific_func = (phy_specific_func_t)NULL
11857
+	.config_init	= bnx2x_8706_config_init,
11858
+	.read_status	= bnx2x_8706_read_status,
11859
+	.link_reset	= bnx2x_common_ext_link_reset,
11860
+	.config_loopback = NULL,
11861
+	.format_fw_ver	= bnx2x_format_ver,
11862
+	.hw_reset	= NULL,
11863
+	.set_link_led	= NULL,
11864
+	.phy_specific_func = NULL
1187911865 };
1188011866 
1188111867 static const struct bnx2x_phy phy_8726 = {
....@@ -11900,14 +11886,14 @@
1190011886 	.speed_cap_mask	= 0,
1190111887 	.req_duplex	= 0,
1190211888 	.rsrv		= 0,
11903
-	.config_init	= (config_init_t)bnx2x_8726_config_init,
11904
-	.read_status	= (read_status_t)bnx2x_8726_read_status,
11905
-	.link_reset	= (link_reset_t)bnx2x_8726_link_reset,
11906
-	.config_loopback = (config_loopback_t)bnx2x_8726_config_loopback,
11907
-	.format_fw_ver	= (format_fw_ver_t)bnx2x_format_ver,
11908
-	.hw_reset	= (hw_reset_t)NULL,
11909
-	.set_link_led	= (set_link_led_t)NULL,
11910
-	.phy_specific_func = (phy_specific_func_t)NULL
11889
+	.config_init	= bnx2x_8726_config_init,
11890
+	.read_status	= bnx2x_8726_read_status,
11891
+	.link_reset	= bnx2x_8726_link_reset,
11892
+	.config_loopback = bnx2x_8726_config_loopback,
11893
+	.format_fw_ver	= bnx2x_format_ver,
11894
+	.hw_reset	= NULL,
11895
+	.set_link_led	= NULL,
11896
+	.phy_specific_func = NULL
1191111897 };
1191211898 
1191311899 static const struct bnx2x_phy phy_8727 = {
....@@ -11931,14 +11917,14 @@
1193111917 	.speed_cap_mask	= 0,
1193211918 	.req_duplex	= 0,
1193311919 	.rsrv		= 0,
11934
-	.config_init	= (config_init_t)bnx2x_8727_config_init,
11935
-	.read_status	= (read_status_t)bnx2x_8727_read_status,
11936
-	.link_reset	= (link_reset_t)bnx2x_8727_link_reset,
11937
-	.config_loopback = (config_loopback_t)NULL,
11938
-	.format_fw_ver	= (format_fw_ver_t)bnx2x_format_ver,
11939
-	.hw_reset	= (hw_reset_t)bnx2x_8727_hw_reset,
11940
-	.set_link_led	= (set_link_led_t)bnx2x_8727_set_link_led,
11941
-	.phy_specific_func = (phy_specific_func_t)bnx2x_8727_specific_func
11920
+	.config_init	= bnx2x_8727_config_init,
11921
+	.read_status	= bnx2x_8727_read_status,
11922
+	.link_reset	= bnx2x_8727_link_reset,
11923
+	.config_loopback = NULL,
11924
+	.format_fw_ver	= bnx2x_format_ver,
11925
+	.hw_reset	= bnx2x_8727_hw_reset,
11926
+	.set_link_led	= bnx2x_8727_set_link_led,
11927
+	.phy_specific_func = bnx2x_8727_specific_func
1194211928 };
1194311929 static const struct bnx2x_phy phy_8481 = {
1194411930 	.type		= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
....@@ -11966,14 +11952,14 @@
1196611952 	.speed_cap_mask	= 0,
1196711953 	.req_duplex	= 0,
1196811954 	.rsrv		= 0,
11969
-	.config_init	= (config_init_t)bnx2x_8481_config_init,
11970
-	.read_status	= (read_status_t)bnx2x_848xx_read_status,
11971
-	.link_reset	= (link_reset_t)bnx2x_8481_link_reset,
11972
-	.config_loopback = (config_loopback_t)NULL,
11973
-	.format_fw_ver	= (format_fw_ver_t)bnx2x_848xx_format_ver,
11974
-	.hw_reset	= (hw_reset_t)bnx2x_8481_hw_reset,
11975
-	.set_link_led	= (set_link_led_t)bnx2x_848xx_set_link_led,
11976
-	.phy_specific_func = (phy_specific_func_t)NULL
11955
+	.config_init	= bnx2x_8481_config_init,
11956
+	.read_status	= bnx2x_848xx_read_status,
11957
+	.link_reset	= bnx2x_8481_link_reset,
11958
+	.config_loopback = NULL,
11959
+	.format_fw_ver	= bnx2x_848xx_format_ver,
11960
+	.hw_reset	= bnx2x_8481_hw_reset,
11961
+	.set_link_led	= bnx2x_848xx_set_link_led,
11962
+	.phy_specific_func = NULL
1197711963 };
1197811964 
1197911965 static const struct bnx2x_phy phy_84823 = {
....@@ -12003,14 +11989,14 @@
1200311989 	.speed_cap_mask	= 0,
1200411990 	.req_duplex	= 0,
1200511991 	.rsrv		= 0,
12006
-	.config_init	= (config_init_t)bnx2x_848x3_config_init,
12007
-	.read_status	= (read_status_t)bnx2x_848xx_read_status,
12008
-	.link_reset	= (link_reset_t)bnx2x_848x3_link_reset,
12009
-	.config_loopback = (config_loopback_t)NULL,
12010
-	.format_fw_ver	= (format_fw_ver_t)bnx2x_848xx_format_ver,
12011
-	.hw_reset	= (hw_reset_t)NULL,
12012
-	.set_link_led	= (set_link_led_t)bnx2x_848xx_set_link_led,
12013
-	.phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func
11992
+	.config_init	= bnx2x_848x3_config_init,
11993
+	.read_status	= bnx2x_848xx_read_status,
11994
+	.link_reset	= bnx2x_848x3_link_reset,
11995
+	.config_loopback = NULL,
11996
+	.format_fw_ver	= bnx2x_848xx_format_ver,
11997
+	.hw_reset	= NULL,
11998
+	.set_link_led	= bnx2x_848xx_set_link_led,
11999
+	.phy_specific_func = bnx2x_848xx_specific_func
1201412000 };
1201512001 
1201612002 static const struct bnx2x_phy phy_84833 = {
....@@ -12038,14 +12024,14 @@
1203812024 	.speed_cap_mask	= 0,
1203912025 	.req_duplex	= 0,
1204012026 	.rsrv		= 0,
12041
-	.config_init	= (config_init_t)bnx2x_848x3_config_init,
12042
-	.read_status	= (read_status_t)bnx2x_848xx_read_status,
12043
-	.link_reset	= (link_reset_t)bnx2x_848x3_link_reset,
12044
-	.config_loopback = (config_loopback_t)NULL,
12045
-	.format_fw_ver	= (format_fw_ver_t)bnx2x_848xx_format_ver,
12046
-	.hw_reset	= (hw_reset_t)bnx2x_84833_hw_reset_phy,
12047
-	.set_link_led	= (set_link_led_t)bnx2x_848xx_set_link_led,
12048
-	.phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func
12027
+	.config_init	= bnx2x_848x3_config_init,
12028
+	.read_status	= bnx2x_848xx_read_status,
12029
+	.link_reset	= bnx2x_848x3_link_reset,
12030
+	.config_loopback = NULL,
12031
+	.format_fw_ver	= bnx2x_848xx_format_ver,
12032
+	.hw_reset	= bnx2x_84833_hw_reset_phy,
12033
+	.set_link_led	= bnx2x_848xx_set_link_led,
12034
+	.phy_specific_func = bnx2x_848xx_specific_func
1204912035 };
1205012036 
1205112037 static const struct bnx2x_phy phy_84834 = {
....@@ -12072,14 +12058,14 @@
1207212058 	.speed_cap_mask	= 0,
1207312059 	.req_duplex	= 0,
1207412060 	.rsrv		= 0,
12075
-	.config_init	= (config_init_t)bnx2x_848x3_config_init,
12076
-	.read_status	= (read_status_t)bnx2x_848xx_read_status,
12077
-	.link_reset	= (link_reset_t)bnx2x_848x3_link_reset,
12078
-	.config_loopback = (config_loopback_t)NULL,
12079
-	.format_fw_ver	= (format_fw_ver_t)bnx2x_848xx_format_ver,
12080
-	.hw_reset	= (hw_reset_t)bnx2x_84833_hw_reset_phy,
12081
-	.set_link_led	= (set_link_led_t)bnx2x_848xx_set_link_led,
12082
-	.phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func
12061
+	.config_init	= bnx2x_848x3_config_init,
12062
+	.read_status	= bnx2x_848xx_read_status,
12063
+	.link_reset	= bnx2x_848x3_link_reset,
12064
+	.config_loopback = NULL,
12065
+	.format_fw_ver	= bnx2x_848xx_format_ver,
12066
+	.hw_reset	= bnx2x_84833_hw_reset_phy,
12067
+	.set_link_led	= bnx2x_848xx_set_link_led,
12068
+	.phy_specific_func = bnx2x_848xx_specific_func
1208312069 };
1208412070 
1208512071 static const struct bnx2x_phy phy_84858 = {
....@@ -12106,14 +12092,14 @@
1210612092 	.speed_cap_mask	= 0,
1210712093 	.req_duplex	= 0,
1210812094 	.rsrv		= 0,
12109
-	.config_init	= (config_init_t)bnx2x_848x3_config_init,
12110
-	.read_status	= (read_status_t)bnx2x_848xx_read_status,
12111
-	.link_reset	= (link_reset_t)bnx2x_848x3_link_reset,
12112
-	.config_loopback = (config_loopback_t)NULL,
12113
-	.format_fw_ver	= (format_fw_ver_t)bnx2x_8485x_format_ver,
12114
-	.hw_reset	= (hw_reset_t)bnx2x_84833_hw_reset_phy,
12115
-	.set_link_led	= (set_link_led_t)bnx2x_848xx_set_link_led,
12116
-	.phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func
12095
+	.config_init	= bnx2x_848x3_config_init,
12096
+	.read_status	= bnx2x_848xx_read_status,
12097
+	.link_reset	= bnx2x_848x3_link_reset,
12098
+	.config_loopback = NULL,
12099
+	.format_fw_ver	= bnx2x_8485x_format_ver,
12100
+	.hw_reset	= bnx2x_84833_hw_reset_phy,
12101
+	.set_link_led	= bnx2x_848xx_set_link_led,
12102
+	.phy_specific_func = bnx2x_848xx_specific_func
1211712103 };
1211812104 
1211912105 static const struct bnx2x_phy phy_54618se = {
....@@ -12140,14 +12126,14 @@
1214012126 	.speed_cap_mask	= 0,
1214112127 	/* req_duplex = */0,
1214212128 	/* rsrv = */0,
12143
-	.config_init	= (config_init_t)bnx2x_54618se_config_init,
12144
-	.read_status	= (read_status_t)bnx2x_54618se_read_status,
12145
-	.link_reset	= (link_reset_t)bnx2x_54618se_link_reset,
12146
-	.config_loopback = (config_loopback_t)bnx2x_54618se_config_loopback,
12147
-	.format_fw_ver	= (format_fw_ver_t)NULL,
12148
-	.hw_reset	= (hw_reset_t)NULL,
12149
-	.set_link_led	= (set_link_led_t)bnx2x_5461x_set_link_led,
12150
-	.phy_specific_func = (phy_specific_func_t)bnx2x_54618se_specific_func
12129
+	.config_init	= bnx2x_54618se_config_init,
12130
+	.read_status	= bnx2x_54618se_read_status,
12131
+	.link_reset	= bnx2x_54618se_link_reset,
12132
+	.config_loopback = bnx2x_54618se_config_loopback,
12133
+	.format_fw_ver	= NULL,
12134
+	.hw_reset	= NULL,
12135
+	.set_link_led	= bnx2x_5461x_set_link_led,
12136
+	.phy_specific_func = bnx2x_54618se_specific_func
1215112137 };
1215212138 /*****************************************************************/
1215312139 /*                                                               */
....@@ -12522,13 +12508,13 @@
1252212508 	switch (link_config  & PORT_FEATURE_LINK_SPEED_MASK) {
1252312509 	case PORT_FEATURE_LINK_SPEED_10M_HALF:
1252412510 		phy->req_duplex = DUPLEX_HALF;
12525
-		/* fall through */
12511
+		fallthrough;
1252612512 	case PORT_FEATURE_LINK_SPEED_10M_FULL:
1252712513 		phy->req_line_speed = SPEED_10;
1252812514 		break;
1252912515 	case PORT_FEATURE_LINK_SPEED_100M_HALF:
1253012516 		phy->req_duplex = DUPLEX_HALF;
12531
-		/* fall through */
12517
+		fallthrough;
1253212518 	case PORT_FEATURE_LINK_SPEED_100M_FULL:
1253312519 		phy->req_line_speed = SPEED_100;
1253412520 		break;
....@@ -12675,39 +12661,39 @@
1267512661 				     struct link_vars *vars)
1267612662 {
1267712663 	struct bnx2x *bp = params->bp;
12678
-		vars->link_up = 1;
12679
-		vars->line_speed = SPEED_10000;
12680
-		vars->duplex = DUPLEX_FULL;
12681
-		vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12682
-		vars->mac_type = MAC_TYPE_BMAC;
12664
+	vars->link_up = 1;
12665
+	vars->line_speed = SPEED_10000;
12666
+	vars->duplex = DUPLEX_FULL;
12667
+	vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12668
+	vars->mac_type = MAC_TYPE_BMAC;
1268312669 
12684
-		vars->phy_flags = PHY_XGXS_FLAG;
12670
+	vars->phy_flags = PHY_XGXS_FLAG;
1268512671 
12686
-		bnx2x_xgxs_deassert(params);
12672
+	bnx2x_xgxs_deassert(params);
1268712673 
12688
-		/* Set bmac loopback */
12689
-		bnx2x_bmac_enable(params, vars, 1, 1);
12674
+	/* Set bmac loopback */
12675
+	bnx2x_bmac_enable(params, vars, 1, 1);
1269012676 
12691
-		REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12677
+	REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);
1269212678 }
1269312679 
1269412680 static void bnx2x_init_emac_loopback(struct link_params *params,
1269512681 				     struct link_vars *vars)
1269612682 {
1269712683 	struct bnx2x *bp = params->bp;
12698
-		vars->link_up = 1;
12699
-		vars->line_speed = SPEED_1000;
12700
-		vars->duplex = DUPLEX_FULL;
12701
-		vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12702
-		vars->mac_type = MAC_TYPE_EMAC;
12684
+	vars->link_up = 1;
12685
+	vars->line_speed = SPEED_1000;
12686
+	vars->duplex = DUPLEX_FULL;
12687
+	vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12688
+	vars->mac_type = MAC_TYPE_EMAC;
1270312689 
12704
-		vars->phy_flags = PHY_XGXS_FLAG;
12690
+	vars->phy_flags = PHY_XGXS_FLAG;
1270512691 
12706
-		bnx2x_xgxs_deassert(params);
12707
-		/* Set bmac loopback */
12708
-		bnx2x_emac_enable(params, vars, 1);
12709
-		bnx2x_emac_program(params, vars);
12710
-		REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12692
+	bnx2x_xgxs_deassert(params);
12693
+	/* Set bmac loopback */
12694
+	bnx2x_emac_enable(params, vars, 1);
12695
+	bnx2x_emac_program(params, vars);
12696
+	REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);
1271112697 }
1271212698 
1271312699 static void bnx2x_init_xmac_loopback(struct link_params *params,
....@@ -13073,12 +13059,12 @@
1307313059 		REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
1307413060 	}
1307513061 
13076
-		if (!CHIP_IS_E3(bp)) {
13077
-			bnx2x_set_bmac_rx(bp, params->chip_id, port, 0);
13078
-		} else {
13079
-			bnx2x_set_xmac_rxtx(params, 0);
13080
-			bnx2x_set_umac_rxtx(params, 0);
13081
-		}
13062
+	if (!CHIP_IS_E3(bp)) {
13063
+		bnx2x_set_bmac_rx(bp, params->chip_id, port, 0);
13064
+	} else {
13065
+		bnx2x_set_xmac_rxtx(params, 0);
13066
+		bnx2x_set_umac_rxtx(params, 0);
13067
+	}
1308213068 	/* Disable emac */
1308313069 	if (!CHIP_IS_E3(bp))
1308413070 		REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);