forked from ~ljy/RK356X_SDK_RELEASE
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hc
2024-05-10 9999e48639b3cecb08ffb37358bcba3b48161b29 
 kernel/drivers/media/platform/rockchip/isp/regs.c
....@@ -33,6 +33,7 @@
3333  */
3434 
3535 #include <media/v4l2-common.h>
36
+#include <linux/rk-camera-module.h>
3637 #include "regs.h"
3738 
3839 void rkisp_disable_dcrop(struct rkisp_stream *stream, bool async)
....@@ -44,7 +45,7 @@
4445 
4546 	if (async && dev->hw_dev->is_single)
4647 		val = CIF_DUAL_CROP_GEN_CFG_UPD;
47
-	rkisp_set_bits(dev, stream->config->dual_crop.ctrl, mask, val, false);
48
+	rkisp_unite_set_bits(dev, stream->config->dual_crop.ctrl, mask, val, false);
4849 }
4950 
5051 void rkisp_config_dcrop(struct rkisp_stream *stream,
....@@ -52,16 +53,56 @@
5253 {
5354 	struct rkisp_device *dev = stream->ispdev;
5455 	u32 val = stream->config->dual_crop.yuvmode_mask;
56
+	bool is_unite = !!dev->hw_dev->unite;
57
+	struct v4l2_rect tmp = *rect;
58
+	u32 reg;
5559 
56
-	rkisp_write(dev, stream->config->dual_crop.h_offset, rect->left, false);
57
-	rkisp_write(dev, stream->config->dual_crop.v_offset, rect->top, false);
58
-	rkisp_write(dev, stream->config->dual_crop.h_size, rect->width, false);
59
-	rkisp_write(dev, stream->config->dual_crop.v_size, rect->height, false);
60
+	if (is_unite) {
61
+		tmp.width /= 2;
62
+		if (stream->id == RKISP_STREAM_FBC)
63
+			tmp.width &= ~0xf;
64
+	}
65
+	reg = stream->config->dual_crop.h_offset;
66
+	rkisp_write(dev, reg, tmp.left, false);
67
+	reg = stream->config->dual_crop.h_size;
68
+	rkisp_write(dev, reg, tmp.width, false);
69
+
70
+	reg = stream->config->dual_crop.v_offset;
71
+	rkisp_unite_write(dev, reg, tmp.top, false);
72
+	reg = stream->config->dual_crop.v_size;
73
+	rkisp_unite_write(dev, reg, tmp.height, false);
74
+
6075 	if (async && dev->hw_dev->is_single)
6176 		val |= CIF_DUAL_CROP_GEN_CFG_UPD;
6277 	else
6378 		val |= CIF_DUAL_CROP_CFG_UPD;
64
-	rkisp_set_bits(dev, stream->config->dual_crop.ctrl, 0, val, false);
79
+	if (is_unite) {
80
+		u32 right_w, left_w = tmp.width;
81
+
82
+		reg = stream->config->dual_crop.h_offset;
83
+		rkisp_next_write(dev, reg, RKMOUDLE_UNITE_EXTEND_PIXEL, false);
84
+		reg = stream->config->dual_crop.h_size;
85
+		right_w = rect->width - left_w;
86
+		rkisp_next_write(dev, reg, right_w, false);
87
+		reg = stream->config->dual_crop.ctrl;
88
+		rkisp_next_set_bits(dev, reg, 0, val, false);
89
+		/* output with scale */
90
+		if (stream->out_fmt.width < rect->width) {
91
+			left_w += RKMOUDLE_UNITE_EXTEND_PIXEL;
92
+			reg = stream->config->dual_crop.h_size;
93
+			rkisp_write(dev, reg, left_w, false);
94
+		}
95
+		v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
96
+			 "left dcrop (%d, %d) %dx%d\n",
97
+			 tmp.left, tmp.top, left_w, tmp.height);
98
+		v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
99
+			 "right dcrop (%d, %d) %dx%d\n",
100
+			 RKMOUDLE_UNITE_EXTEND_PIXEL, tmp.top, right_w, tmp.height);
101
+	}
102
+	if (val) {
103
+		reg = stream->config->dual_crop.ctrl;
104
+		rkisp_set_bits(dev, reg, 0, val, false);
105
+	}
65106 }
66107 
67108 void rkisp_dump_rsz_regs(struct rkisp_stream *stream)
....@@ -107,7 +148,7 @@
107148 
108149 	if (async && dev->hw_dev->is_single)
109150 		val = CIF_RSZ_CTRL_CFG_UPD_AUTO;
110
-	rkisp_set_bits(dev, stream->config->rsz.ctrl, 0, val, false);
151
+	rkisp_unite_set_bits(dev, stream->config->rsz.ctrl, 0, val, false);
111152 }
112153 
113154 static void set_scale(struct rkisp_stream *stream, struct v4l2_rect *in_y,
....@@ -121,7 +162,8 @@
121162 	u32 scale_vy_addr = stream->config->rsz.scale_vy;
122163 	u32 scale_vc_addr = stream->config->rsz.scale_vc;
123164 	u32 rsz_ctrl_addr = stream->config->rsz.ctrl;
124
-	u32 scale_hy, scale_hc, scale_vy, scale_vc, rsz_ctrl = 0;
165
+	u32 scale_hy = 1, scale_hc = 1, scale_vy = 1, scale_vc = 1;
166
+	u32 rsz_ctrl = 0;
125167 
126168 	if (in_y->width < out_y->width) {
127169 		rsz_ctrl |= CIF_RSZ_CTRL_SCALE_HY_ENABLE |
....@@ -176,7 +218,159 @@
176218 		rkisp_write(dev, scale_vc_addr, scale_vc, false);
177219 	}
178220 
221
+	if (dev->hw_dev->unite) {
222
+		u32 hy_size_reg, hc_size_reg, hy_offs_mi_reg, hc_offs_mi_reg, in_crop_offs_reg;
223
+		u32 isp_in_w = in_y->width / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL;
224
+		u32 scl_w = out_y->width / 2;
225
+		u32 left_y = scale_hy == 1 ? scl_w : DIV_ROUND_UP(scl_w * 65536, scale_hy);
226
+		u32 left_c = scale_hc == 1 ? scl_w / 2 : DIV_ROUND_UP(scl_w * 65536 / 2, scale_hc);
227
+		u32 phase_src_y = left_y * scale_hy;
228
+		u32 phase_dst_y = scl_w * 65536;
229
+		u32 phase_left_y = scale_hy == 1 ? 0 : scale_hy - (phase_src_y - phase_dst_y);
230
+		u32 phase_src_c = left_c * scale_hc;
231
+		u32 phase_dst_c = scl_w * 65536 / 2;
232
+		u32 phase_left_c = scale_hc == 1 ? 0 : scale_hc - (phase_src_c - phase_dst_c);
233
+		u32 right_y = phase_left_y ? in_y->width - (left_y - 1) : in_y->width - left_y;
234
+		u32 right_c = phase_left_c ? in_y->width - (left_c - 1) * 2 : in_y->width - left_c * 2;
235
+		u32 right_crop_y = isp_in_w - right_y;
236
+		u32 right_crop_c = isp_in_w - right_c;
237
+		u32 extend = RKMOUDLE_UNITE_EXTEND_PIXEL;
238
+		u32 right_scl_in_y;
239
+		u32 right_scl_in_c;
240
+
241
+		switch (stream->id) {
242
+		case RKISP_STREAM_MP:
243
+			hy_size_reg = ISP3X_MAIN_RESIZE_HY_SIZE;
244
+			hc_size_reg = ISP3X_MAIN_RESIZE_HC_SIZE;
245
+			hy_offs_mi_reg = ISP3X_MAIN_RESIZE_HY_OFFS_MI;
246
+			hc_offs_mi_reg = ISP3X_MAIN_RESIZE_HC_OFFS_MI;
247
+			in_crop_offs_reg = ISP3X_MAIN_RESIZE_IN_CROP_OFFSET;
248
+			break;
249
+		case RKISP_STREAM_SP:
250
+			hy_size_reg = ISP3X_SELF_RESIZE_HY_SIZE;
251
+			hc_size_reg = ISP3X_SELF_RESIZE_HC_SIZE;
252
+			hy_offs_mi_reg = ISP3X_SELF_RESIZE_HY_OFFS_MI;
253
+			hc_offs_mi_reg = ISP3X_SELF_RESIZE_HC_OFFS_MI;
254
+			in_crop_offs_reg = ISP3X_SELF_RESIZE_IN_CROP_OFFSET;
255
+			break;
256
+		case RKISP_STREAM_BP:
257
+			hy_size_reg = ISP32_BP_RESIZE_HY_SIZE;
258
+			hc_size_reg = ISP32_BP_RESIZE_HC_SIZE;
259
+			hy_offs_mi_reg = ISP32_BP_RESIZE_HY_OFFS_MI;
260
+			hc_offs_mi_reg = ISP32_BP_RESIZE_HC_OFFS_MI;
261
+			in_crop_offs_reg = ISP32_BP_RESIZE_IN_CROP_OFFSET;
262
+			break;
263
+		default:
264
+			v4l2_warn(&dev->v4l2_dev, "%s no support unite for stream:%d\n",
265
+				  __func__, stream->id);
266
+			return;
267
+		}
268
+
269
+		if (right_crop_y < RKMOUDLE_UNITE_EXTEND_PIXEL) {
270
+			u32 reg;
271
+
272
+			extend = right_crop_y & ~0x1;
273
+			reg = stream->config->dual_crop.h_offset;
274
+			rkisp_next_write(dev, reg, extend, false);
275
+			reg = stream->config->dual_crop.h_size;
276
+			rkisp_next_write(dev, reg, isp_in_w - extend, false);
277
+			reg = stream->config->dual_crop.ctrl;
278
+			rkisp_next_write(dev, reg, rkisp_next_read_reg_cache(dev, reg), false);
279
+		}
280
+		right_scl_in_y = right_crop_y - extend;
281
+		right_scl_in_c = right_crop_c - extend;
282
+
283
+		/* left isp */
284
+		rkisp_write(dev, hy_size_reg, scl_w, false);
285
+		rkisp_write(dev, hc_size_reg, scl_w, false);
286
+		rkisp_write(dev, hy_offs_mi_reg, 0, false);
287
+		rkisp_write(dev, hc_offs_mi_reg, 0, false);
288
+		rkisp_write(dev, in_crop_offs_reg, 0, false);
289
+
290
+		/* right isp */
291
+		rkisp_next_write(dev, hy_size_reg, scl_w, false);
292
+		rkisp_next_write(dev, hc_size_reg, scl_w, false);
293
+		rkisp_next_write(dev, scale_hy_addr, scale_hy, false);
294
+		rkisp_next_write(dev, scale_hcb_addr, scale_hc, false);
295
+		rkisp_next_write(dev, scale_hcr_addr, scale_hc, false);
296
+		rkisp_next_write(dev, scale_vy_addr, scale_vy, false);
297
+		rkisp_next_write(dev, scale_vc_addr, scale_vc, false);
298
+		rkisp_next_write(dev, stream->config->rsz.phase_hy, phase_left_y, false);
299
+		rkisp_next_write(dev, stream->config->rsz.phase_hc, phase_left_c, false);
300
+		rkisp_next_write(dev, stream->config->rsz.phase_vy, 0, false);
301
+		rkisp_next_write(dev, stream->config->rsz.phase_vc, 0, false);
302
+		rkisp_next_write(dev, hy_offs_mi_reg, scl_w & 15, false);
303
+		rkisp_next_write(dev, hc_offs_mi_reg, scl_w & 15, false);
304
+		rkisp_next_write(dev, in_crop_offs_reg,
305
+				 right_scl_in_c << 4 | right_scl_in_y, false);
306
+
307
+		rsz_ctrl |= ISP3X_SCL_CLIP_EN;
308
+		rkisp_next_write(dev, rsz_ctrl_addr,
309
+				 rsz_ctrl | ISP3X_SCL_HPHASE_EN | ISP3X_SCL_IN_CLIP_EN, false);
310
+		v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
311
+			 "scl:%dx%d, scl factor[hy:%d hc:%d vy:%d vc:%d]\n",
312
+			 scl_w, out_y->height, scale_hy, scale_hc, scale_vy, scale_vc);
313
+		v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
314
+			 "scl_left size[y:%d c:%d] phase[y:%d c:%d]\n",
315
+			 left_y, left_c, phase_left_y, phase_left_c);
316
+		v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
317
+			 "scl_right size[y:%d c:%d] offs_mi[y:%d c:%d] in_crop[y:%d c:%d]\n",
318
+			 right_y, right_c, scl_w & 15, scl_w & 15, right_scl_in_y, right_scl_in_c);
319
+	}
179320 	rkisp_write(dev, rsz_ctrl_addr, rsz_ctrl, false);
321
+}
322
+
323
+static void set_bilinear_scale(struct rkisp_stream *stream, struct v4l2_rect *in_y,
324
+				struct v4l2_rect *in_c, struct v4l2_rect *out_y,
325
+				struct v4l2_rect *out_c, bool async)
326
+{
327
+	struct rkisp_device *dev = stream->ispdev;
328
+	u32 rsz_ctrl = 0, val, hy, hc;
329
+	bool is_avg = false;
330
+
331
+	rkisp_write(dev, ISP32_SELF_SCALE_HY_OFFS, 0, true);
332
+	rkisp_write(dev, ISP32_SELF_SCALE_HC_OFFS, 0, true);
333
+	rkisp_write(dev, ISP32_SELF_SCALE_PHASE_HY, 0, true);
334
+	rkisp_write(dev, ISP32_SELF_SCALE_PHASE_HC, 0, true);
335
+	rkisp_write(dev, ISP32_SELF_SCALE_PHASE_VY, 0, true);
336
+	rkisp_write(dev, ISP32_SELF_SCALE_PHASE_VC, 0, true);
337
+
338
+	val = in_y->width | in_y->height << 16;
339
+	rkisp_write(dev, ISP32_SELF_SCALE_SRC_SIZE, val, false);
340
+	val = out_y->width | out_y->height << 16;
341
+	rkisp_write(dev, ISP32_SELF_SCALE_DST_SIZE, val, false);
342
+
343
+	if (in_y->width != out_y->width) {
344
+		rsz_ctrl |= CIF_RSZ_CTRL_SCALE_HY_ENABLE | CIF_RSZ_CTRL_SCALE_HC_ENABLE;
345
+		if (is_avg) {
346
+			hy = ((out_y->width - 1) * ISP32_SCALE_AVE_FACTOR) / (in_y->width - 1) + 1;
347
+			hc = ((out_c->width - 1) * ISP32_SCALE_AVE_FACTOR) / (in_c->width - 1) + 1;
348
+			rsz_ctrl |= ISP32_SCALE_AVG_H_EN;
349
+		} else {
350
+			hy = ((in_y->width - 1) * ISP32_SCALE_BIL_FACTOR) / (out_y->width - 1);
351
+			hc = ((in_c->width - 1) * ISP32_SCALE_BIL_FACTOR) / (out_c->width - 1);
352
+		}
353
+		rkisp_write(dev, ISP32_SELF_SCALE_HY_FAC, hy, false);
354
+		rkisp_write(dev, ISP32_SELF_SCALE_HC_FAC, hc, false);
355
+	}
356
+
357
+	if (in_y->height != out_y->height) {
358
+		rsz_ctrl |= CIF_RSZ_CTRL_SCALE_VY_ENABLE | CIF_RSZ_CTRL_SCALE_VC_ENABLE;
359
+		if (is_avg) {
360
+			val = ((out_y->height - 1) * ISP32_SCALE_AVE_FACTOR) / (in_y->height - 1) + 1;
361
+			rsz_ctrl |= ISP32_SCALE_AVG_V_EN;
362
+		} else {
363
+			val = ((in_y->height - 1) * ISP32_SCALE_BIL_FACTOR) / (out_y->height - 1);
364
+		}
365
+		rkisp_write(dev, ISP32_SELF_SCALE_VY_FAC, val, false);
366
+		rkisp_write(dev, ISP32_SELF_SCALE_VC_FAC, val, false);
367
+	}
368
+
369
+	rkisp_write(dev, ISP32_SELF_SCALE_CTRL, rsz_ctrl, false);
370
+	val = ISP32_SCALE_FORCE_UPD;
371
+	if (async && dev->hw_dev->is_single)
372
+		val = ISP32_SCALE_GEN_UPD;
373
+	rkisp_write(dev, ISP32_SELF_SCALE_UPDATE, val, true);
180374 }
181375 
182376 void rkisp_config_rsz(struct rkisp_stream *stream, struct v4l2_rect *in_y,
....@@ -186,6 +380,11 @@
186380 	struct rkisp_device *dev = stream->ispdev;
187381 	int i = 0;
188382 
383
+	if (dev->isp_ver == ISP_V32_L && stream->id == RKISP_STREAM_SP) {
384
+		set_bilinear_scale(stream, in_y, in_c, out_y, out_c, async);
385
+		return;
386
+	}
387
+
189388 	/* No phase offset */
190389 	rkisp_write(dev, stream->config->rsz.phase_hy, 0, true);
191390 	rkisp_write(dev, stream->config->rsz.phase_hc, 0, true);
....@@ -194,8 +393,8 @@
194393 
195394 	/* Linear interpolation */
196395 	for (i = 0; i < 64; i++) {
197
-		rkisp_write(dev, stream->config->rsz.scale_lut_addr, i, true);
198
-		rkisp_write(dev, stream->config->rsz.scale_lut, i, true);
396
+		rkisp_unite_write(dev, stream->config->rsz.scale_lut_addr, i, true);
397
+		rkisp_unite_write(dev, stream->config->rsz.scale_lut, i, true);
199398 	}
200399 
201400 	set_scale(stream, in_y, in_c, out_y, out_c);
....@@ -205,8 +404,8 @@
205404 
206405 void rkisp_disable_rsz(struct rkisp_stream *stream, bool async)
207406 {
208
-	rkisp_write(stream->ispdev, stream->config->rsz.ctrl, 0, false);
209
-
210
-	if (!async)
211
-		update_rsz_shadow(stream, async);
407
+	rkisp_unite_write(stream->ispdev, stream->config->rsz.ctrl, 0, false);
408
+	if (stream->ispdev->isp_ver == ISP_V32_L && stream->id == RKISP_STREAM_SP)
409
+		return;
410
+	update_rsz_shadow(stream, async);
212411 }