forked from ~ljy/RK356X_SDK_RELEASE
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hc
2024-05-10 9999e48639b3cecb08ffb37358bcba3b48161b29 
 kernel/drivers/media/platform/rockchip/isp/hw.c
....@@ -9,13 +9,14 @@
99 #include <linux/mfd/syscon.h>
1010 #include <linux/module.h>
1111 #include <linux/of.h>
12
+#include <linux/of_address.h>
1213 #include <linux/of_graph.h>
1314 #include <linux/of_platform.h>
1415 #include <linux/of_reserved_mem.h>
1516 #include <linux/pinctrl/consumer.h>
1617 #include <linux/pm_runtime.h>
1718 #include <linux/reset.h>
18
-#include <media/videobuf2-dma-contig.h>
19
+#include <media/videobuf2-cma-sg.h>
1920 #include <media/videobuf2-dma-sg.h>
2021 #include <soc/rockchip/rockchip_iommu.h>
2122 
....@@ -33,6 +34,12 @@
3334  *                         |
3435  *                     rkisp_hw
3536  */
37
+
38
+struct backup_reg {
39
+	const u32 base;
40
+	const u32 shd;
41
+	u32 val;
42
+};
3643 
3744 struct isp_irqs_data {
3845 	const char *name;
....@@ -72,6 +79,38 @@
7279 		ISP_RAWHIST_BIG3_BASE, ISP_YUVAE_CTRL, ISP_RAWAF_CTRL,
7380 		ISP21_RAWAWB_CTRL,
7481 	};
82
+	u32 v30_reg[] = {
83
+		ISP3X_VI_ISP_PATH, ISP3X_IMG_EFF_CTRL, ISP3X_CMSK_CTRL0,
84
+		ISP3X_CCM_CTRL, ISP3X_CPROC_CTRL, ISP3X_DUAL_CROP_CTRL,
85
+		ISP3X_GAMMA_OUT_CTRL, ISP3X_SELF_RESIZE_CTRL, ISP3X_MAIN_RESIZE_CTRL,
86
+		ISP3X_LSC_CTRL, ISP3X_DEBAYER_CONTROL, ISP3X_CAC_CTRL,
87
+		ISP3X_YNR_GLOBAL_CTRL, ISP3X_CNR_CTRL, ISP3X_SHARP_EN,
88
+		ISP3X_BAY3D_CTRL, ISP3X_GIC_CONTROL, ISP3X_BLS_CTRL,
89
+		ISP3X_DPCC0_MODE, ISP3X_DPCC1_MODE, ISP3X_DPCC2_MODE,
90
+		ISP3X_HDRMGE_CTRL, ISP3X_DRC_CTRL0, ISP3X_BAYNR_CTRL,
91
+		ISP3X_LDCH_STS, ISP3X_DHAZ_CTRL, ISP3X_3DLUT_CTRL,
92
+		ISP3X_GAIN_CTRL, ISP3X_RAWAE_LITE_CTRL, ISP3X_RAWAE_BIG1_BASE,
93
+		ISP3X_RAWAE_BIG2_BASE, ISP3X_RAWAE_BIG3_BASE, ISP3X_RAWHIST_LITE_CTRL,
94
+		ISP3X_RAWHIST_BIG1_BASE, ISP3X_RAWHIST_BIG2_BASE, ISP3X_RAWHIST_BIG3_BASE,
95
+		ISP3X_RAWAF_CTRL, ISP3X_RAWAWB_CTRL,
96
+	};
97
+	u32 v32_reg[] = {
98
+		ISP3X_VI_ISP_PATH, ISP3X_IMG_EFF_CTRL, ISP3X_CMSK_CTRL0,
99
+		ISP3X_CCM_CTRL, ISP3X_CPROC_CTRL, ISP3X_DUAL_CROP_CTRL,
100
+		ISP3X_GAMMA_OUT_CTRL, ISP3X_SELF_RESIZE_CTRL, ISP3X_MAIN_RESIZE_CTRL,
101
+		ISP32_BP_RESIZE_BASE, ISP3X_MI_BP_WR_CTRL, ISP32_MI_MPDS_WR_CTRL,
102
+		ISP32_MI_BPDS_WR_CTRL, ISP32_MI_WR_WRAP_CTRL,
103
+		ISP3X_LSC_CTRL, ISP3X_DEBAYER_CONTROL, ISP3X_CAC_CTRL,
104
+		ISP3X_YNR_GLOBAL_CTRL, ISP3X_CNR_CTRL, ISP3X_SHARP_EN,
105
+		ISP3X_BAY3D_CTRL, ISP3X_GIC_CONTROL, ISP3X_BLS_CTRL,
106
+		ISP3X_DPCC0_MODE, ISP3X_DPCC1_MODE, ISP3X_DPCC2_MODE,
107
+		ISP3X_HDRMGE_CTRL, ISP3X_DRC_CTRL0, ISP3X_BAYNR_CTRL,
108
+		ISP3X_LDCH_STS, ISP3X_DHAZ_CTRL, ISP3X_3DLUT_CTRL,
109
+		ISP3X_GAIN_CTRL, ISP3X_RAWAE_LITE_CTRL, ISP3X_RAWAE_BIG1_BASE,
110
+		ISP3X_RAWAE_BIG2_BASE, ISP3X_RAWAE_BIG3_BASE, ISP3X_RAWHIST_LITE_CTRL,
111
+		ISP3X_RAWHIST_BIG1_BASE, ISP3X_RAWHIST_BIG2_BASE, ISP3X_RAWHIST_BIG3_BASE,
112
+		ISP3X_RAWAF_CTRL, ISP3X_RAWAWB_CTRL,
113
+	};
75114 	u32 i, *flag, *reg, size;
76115 
77116 	switch (dev->isp_ver) {
....@@ -83,6 +122,15 @@
83122 		reg = v21_reg;
84123 		size = ARRAY_SIZE(v21_reg);
85124 		break;
125
+	case ISP_V30:
126
+		reg = v30_reg;
127
+		size = ARRAY_SIZE(v30_reg);
128
+		break;
129
+	case ISP_V32:
130
+	case ISP_V32_L:
131
+		reg = v32_reg;
132
+		size = ARRAY_SIZE(v32_reg);
133
+		break;
86134 	default:
87135 		return;
88136 	}
....@@ -90,6 +138,10 @@
90138 	for (i = 0; i < size; i++) {
91139 		flag = dev->sw_base_addr + reg[i] + RKISP_ISP_SW_REG_SIZE;
92140 		*flag = SW_REG_CACHE;
141
+		if (dev->hw_dev->unite) {
142
+			flag += RKISP_ISP_SW_MAX_SIZE / 4;
143
+			*flag = SW_REG_CACHE;
144
+		}
93145 	}
94146 }
95147 
....@@ -98,39 +150,55 @@
98150 	struct device *dev = ctx;
99151 	struct rkisp_hw_dev *hw_dev = dev_get_drvdata(dev);
100152 	struct rkisp_device *isp = hw_dev->isp[hw_dev->mipi_dev_id];
153
+	void __iomem *base = hw_dev->unite != ISP_UNITE_TWO ?
154
+		hw_dev->base_addr : hw_dev->base_next_addr;
155
+	ktime_t t = 0;
156
+	s64 us;
101157 
102158 	if (hw_dev->is_thunderboot)
103159 		return IRQ_HANDLED;
104160 
161
+	if (rkisp_irq_dbg)
162
+		t = ktime_get();
163
+
105164 	if (hw_dev->isp_ver == ISP_V13 || hw_dev->isp_ver == ISP_V12) {
106165 		u32 err1, err2, err3;
107166 
108
-		err1 = readl(hw_dev->base_addr + CIF_ISP_CSI0_ERR1);
109
-		err2 = readl(hw_dev->base_addr + CIF_ISP_CSI0_ERR2);
110
-		err3 = readl(hw_dev->base_addr + CIF_ISP_CSI0_ERR3);
167
+		err1 = readl(base + CIF_ISP_CSI0_ERR1);
168
+		err2 = readl(base + CIF_ISP_CSI0_ERR2);
169
+		err3 = readl(base + CIF_ISP_CSI0_ERR3);
111170 
112171 		if (err1 || err2 || err3)
113172 			rkisp_mipi_v13_isr(err1, err2, err3, isp);
114
-	} else if (hw_dev->isp_ver == ISP_V20 || hw_dev->isp_ver == ISP_V21) {
173
+	} else if (hw_dev->isp_ver >= ISP_V20) {
115174 		u32 phy, packet, overflow, state;
116175 
117
-		state = readl(hw_dev->base_addr + CSI2RX_ERR_STAT);
118
-		phy = readl(hw_dev->base_addr + CSI2RX_ERR_PHY);
119
-		packet = readl(hw_dev->base_addr + CSI2RX_ERR_PACKET);
120
-		overflow = readl(hw_dev->base_addr + CSI2RX_ERR_OVERFLOW);
176
+		state = readl(base + CSI2RX_ERR_STAT);
177
+		phy = readl(base + CSI2RX_ERR_PHY);
178
+		packet = readl(base + CSI2RX_ERR_PACKET);
179
+		overflow = readl(base + CSI2RX_ERR_OVERFLOW);
121180 		if (phy | packet | overflow | state) {
122181 			if (hw_dev->isp_ver == ISP_V20)
123182 				rkisp_mipi_v20_isr(phy, packet, overflow, state, isp);
124
-			else
183
+			else if (hw_dev->isp_ver == ISP_V21)
125184 				rkisp_mipi_v21_isr(phy, packet, overflow, state, isp);
185
+			else if (hw_dev->isp_ver == ISP_V30)
186
+				rkisp_mipi_v30_isr(phy, packet, overflow, state, isp);
187
+			else
188
+				rkisp_mipi_v32_isr(phy, packet, overflow, state, isp);
126189 		}
127190 	} else {
128
-		u32 mis_val = readl(hw_dev->base_addr + CIF_MIPI_MIS);
191
+		u32 mis_val = readl(base + CIF_MIPI_MIS);
129192 
130193 		if (mis_val)
131194 			rkisp_mipi_isr(mis_val, isp);
132195 	}
133196 
197
+	if (rkisp_irq_dbg) {
198
+		us = ktime_us_delta(ktime_get(), t);
199
+		v4l2_dbg(0, rkisp_debug, &isp->v4l2_dev,
200
+			 "%s %lldus\n", __func__, us);
201
+	}
134202 	return IRQ_HANDLED;
135203 }
136204 
....@@ -139,13 +207,20 @@
139207 	struct device *dev = ctx;
140208 	struct rkisp_hw_dev *hw_dev = dev_get_drvdata(dev);
141209 	struct rkisp_device *isp = hw_dev->isp[hw_dev->cur_dev_id];
210
+	void __iomem *base = hw_dev->unite != ISP_UNITE_TWO ?
211
+		hw_dev->base_addr : hw_dev->base_next_addr;
142212 	u32 mis_val, tx_isr = MI_RAW0_WR_FRAME | MI_RAW1_WR_FRAME |
143213 		MI_RAW2_WR_FRAME | MI_RAW3_WR_FRAME;
214
+	ktime_t t = 0;
215
+	s64 us;
144216 
145217 	if (hw_dev->is_thunderboot)
146218 		return IRQ_HANDLED;
147219 
148
-	mis_val = readl(hw_dev->base_addr + CIF_MI_MIS);
220
+	if (rkisp_irq_dbg)
221
+		t = ktime_get();
222
+
223
+	mis_val = readl(base + CIF_MI_MIS);
149224 	if (mis_val) {
150225 		if (mis_val & ~tx_isr)
151226 			rkisp_mi_isr(mis_val & ~tx_isr, isp);
....@@ -153,6 +228,12 @@
153228 			isp = hw_dev->isp[hw_dev->mipi_dev_id];
154229 			rkisp_mi_isr(mis_val & tx_isr, isp);
155230 		}
231
+	}
232
+
233
+	if (rkisp_irq_dbg) {
234
+		us = ktime_us_delta(ktime_get(), t);
235
+		v4l2_dbg(0, rkisp_debug, &isp->v4l2_dev,
236
+			 "%s:0x%x %lldus\n", __func__, mis_val, us);
156237 	}
157238 	return IRQ_HANDLED;
158239 }
....@@ -162,17 +243,29 @@
162243 	struct device *dev = ctx;
163244 	struct rkisp_hw_dev *hw_dev = dev_get_drvdata(dev);
164245 	struct rkisp_device *isp = hw_dev->isp[hw_dev->cur_dev_id];
246
+	void __iomem *base = hw_dev->unite != ISP_UNITE_TWO ?
247
+		hw_dev->base_addr : hw_dev->base_next_addr;
165248 	unsigned int mis_val, mis_3a = 0;
249
+	ktime_t t = 0;
250
+	s64 us;
166251 
167252 	if (hw_dev->is_thunderboot)
168253 		return IRQ_HANDLED;
169254 
170
-	mis_val = readl(hw_dev->base_addr + CIF_ISP_MIS);
171
-	if (hw_dev->isp_ver == ISP_V20 || hw_dev->isp_ver == ISP_V21)
172
-		mis_3a = readl(hw_dev->base_addr + ISP_ISP3A_MIS);
255
+	if (rkisp_irq_dbg)
256
+		t = ktime_get();
257
+
258
+	mis_val = readl(base + CIF_ISP_MIS);
259
+	if (hw_dev->isp_ver >= ISP_V20)
260
+		mis_3a = readl(base + ISP_ISP3A_MIS);
173261 	if (mis_val || mis_3a)
174262 		rkisp_isp_isr(mis_val, mis_3a, isp);
175263 
264
+	if (rkisp_irq_dbg) {
265
+		us = ktime_us_delta(ktime_get(), t);
266
+		v4l2_dbg(0, rkisp_debug, &isp->v4l2_dev,
267
+			 "%s:0x%x %lldus\n", __func__, mis_val, us);
268
+	}
176269 	return IRQ_HANDLED;
177270 }
178271 
....@@ -184,7 +277,7 @@
184277 	unsigned int mis_val, mis_3a = 0;
185278 
186279 	mis_val = readl(hw_dev->base_addr + CIF_ISP_MIS);
187
-	if (hw_dev->isp_ver == ISP_V20 || hw_dev->isp_ver == ISP_V21)
280
+	if (hw_dev->isp_ver >= ISP_V20)
188281 		mis_3a = readl(hw_dev->base_addr + ISP_ISP3A_MIS);
189282 	if (mis_val || mis_3a)
190283 		rkisp_isp_isr(mis_val, mis_3a, isp);
....@@ -261,42 +354,196 @@
261354 	return 0;
262355 }
263356 
264
-static const char * const rk1808_isp_clks[] = {
265
-	"clk_isp",
266
-	"aclk_isp",
267
-	"hclk_isp",
268
-	"pclk_isp",
269
-};
357
+void rkisp_hw_reg_save(struct rkisp_hw_dev *dev)
358
+{
359
+	void *buf = dev->sw_reg;
270360 
271
-static const char * const rk3288_isp_clks[] = {
272
-	"clk_isp",
273
-	"aclk_isp",
274
-	"hclk_isp",
275
-	"pclk_isp_in",
276
-	"sclk_isp_jpe",
277
-};
361
+	memcpy_fromio(buf, dev->base_addr, RKISP_ISP_SW_REG_SIZE);
362
+	if (dev->unite == ISP_UNITE_TWO) {
363
+		buf += RKISP_ISP_SW_REG_SIZE;
364
+		memcpy_fromio(buf, dev->base_next_addr, RKISP_ISP_SW_REG_SIZE);
365
+	}
366
+}
278367 
279
-static const char * const rk3326_isp_clks[] = {
280
-	"clk_isp",
281
-	"aclk_isp",
282
-	"hclk_isp",
283
-	"pclk_isp",
284
-};
368
+void rkisp_hw_reg_restore(struct rkisp_hw_dev *dev)
369
+{
370
+	struct rkisp_device *isp = dev->isp[dev->cur_dev_id];
371
+	void __iomem *base = dev->base_addr;
372
+	void *reg_buf = dev->sw_reg;
373
+	u32 val, *reg, *reg1, i, j;
374
+	u32 self_upd_reg[] = {
375
+		ISP21_BAY3D_BASE, ISP21_DRC_BASE, ISP3X_BAY3D_CTRL,
376
+		ISP_DHAZ_CTRL, ISP3X_3DLUT_BASE, ISP_RAWAE_LITE_BASE,
377
+		RAWAE_BIG1_BASE, RAWAE_BIG2_BASE, RAWAE_BIG3_BASE,
378
+		ISP_RAWHIST_LITE_BASE, ISP_RAWHIST_BIG1_BASE,
379
+		ISP_RAWHIST_BIG2_BASE, ISP_RAWHIST_BIG3_BASE,
380
+		ISP_RAWAF_BASE, ISP_RAWAWB_BASE, ISP_LDCH_BASE,
381
+		ISP3X_CAC_BASE,
382
+	};
383
+	struct backup_reg backup[] = {
384
+		{
385
+			.base = MI_MP_WR_Y_BASE,
386
+			.shd = MI_MP_WR_Y_BASE_SHD,
387
+		}, {
388
+			.base = MI_MP_WR_CB_BASE,
389
+			.shd = MI_MP_WR_CB_BASE_SHD,
390
+		}, {
391
+			.base = MI_MP_WR_CR_BASE,
392
+			.shd = MI_MP_WR_CR_BASE_SHD,
393
+		}, {
394
+			.base = MI_SP_WR_Y_BASE,
395
+			.shd = MI_SP_WR_Y_BASE_SHD,
396
+		}, {
397
+			.base = MI_SP_WR_CB_BASE,
398
+			.shd = MI_SP_WR_CB_BASE_AD_SHD,
399
+		}, {
400
+			.base = MI_SP_WR_CR_BASE,
401
+			.shd = MI_SP_WR_CR_BASE_AD_SHD,
402
+		}, {
403
+			.base = ISP3X_MI_BP_WR_Y_BASE,
404
+			.shd = ISP3X_MI_BP_WR_Y_BASE_SHD,
405
+		}, {
406
+			.base = ISP3X_MI_BP_WR_CB_BASE,
407
+			.shd = ISP3X_MI_BP_WR_CB_BASE_SHD,
408
+		}, {
409
+			.base = ISP32_MI_MPDS_WR_Y_BASE,
410
+			.shd = ISP32_MI_MPDS_WR_Y_BASE_SHD,
411
+		}, {
412
+			.base = ISP32_MI_MPDS_WR_CB_BASE,
413
+			.shd = ISP32_MI_MPDS_WR_CB_BASE_SHD,
414
+		}, {
415
+			.base = ISP32_MI_BPDS_WR_Y_BASE,
416
+			.shd = ISP32_MI_BPDS_WR_Y_BASE_SHD,
417
+		}, {
418
+			.base = ISP32_MI_BPDS_WR_CB_BASE,
419
+			.shd = ISP32_MI_BPDS_WR_CB_BASE_SHD,
420
+		}, {
421
+			.base = MI_RAW0_WR_BASE,
422
+			.shd = MI_RAW0_WR_BASE_SHD,
423
+		}, {
424
+			.base = MI_RAW1_WR_BASE,
425
+			.shd = MI_RAW1_WR_BASE_SHD,
426
+		}, {
427
+			.base = MI_RAW2_WR_BASE,
428
+			.shd = MI_RAW2_WR_BASE_SHD,
429
+		}, {
430
+			.base = MI_RAW3_WR_BASE,
431
+			.shd = MI_RAW3_WR_BASE_SHD,
432
+		}, {
433
+			.base = MI_RAW0_RD_BASE,
434
+			.shd = MI_RAW0_RD_BASE_SHD,
435
+		}, {
436
+			.base = MI_RAW1_RD_BASE,
437
+			.shd = MI_RAW1_RD_BASE_SHD,
438
+		}, {
439
+			.base = MI_RAW2_RD_BASE,
440
+			.shd = MI_RAW2_RD_BASE_SHD,
441
+		}, {
442
+			.base = MI_GAIN_WR_BASE,
443
+			.shd = MI_GAIN_WR_BASE_SHD,
444
+		}
445
+	};
285446 
286
-static const char * const rk3368_isp_clks[] = {
287
-	"clk_isp",
288
-	"aclk_isp",
289
-	"hclk_isp",
290
-	"pclk_isp",
291
-};
447
+	for (i = 0; i <= !!dev->unite; i++) {
448
+		if (dev->unite != ISP_UNITE_TWO && i)
449
+			break;
292450 
293
-static const char * const rk3399_isp_clks[] = {
294
-	"clk_isp",
451
+		if (i) {
452
+			reg_buf += RKISP_ISP_SW_REG_SIZE;
453
+			base = dev->base_next_addr;
454
+		}
455
+
456
+		/* process special reg */
457
+		for (j = 0; j < ARRAY_SIZE(self_upd_reg); j++) {
458
+			reg = reg_buf + self_upd_reg[j];
459
+			*reg &= ~ISP21_SELF_FORCE_UPD;
460
+			if (self_upd_reg[j] == ISP3X_3DLUT_BASE && *reg & ISP_3DLUT_EN) {
461
+				reg = reg_buf + ISP3X_3DLUT_UPDATE;
462
+				*reg = 1;
463
+			}
464
+		}
465
+		reg = reg_buf + ISP_CTRL;
466
+		*reg &= ~(CIF_ISP_CTRL_ISP_ENABLE |
467
+			  CIF_ISP_CTRL_ISP_INFORM_ENABLE |
468
+			  CIF_ISP_CTRL_ISP_CFG_UPD);
469
+		reg = reg_buf + MI_WR_INIT;
470
+		*reg = 0;
471
+		reg = reg_buf + CSI2RX_CTRL0;
472
+		*reg &= ~SW_CSI2RX_EN;
473
+		for (j = 0; j < RKISP_ISP_SW_REG_SIZE; j += 4) {
474
+			/* skip table RAM */
475
+			if ((j > ISP3X_LSC_CTRL && j < ISP3X_LSC_XGRAD_01) ||
476
+			    (j > ISP32_CAC_OFFSET && j < ISP3X_CAC_RO_CNT) ||
477
+			    (j > ISP3X_3DLUT_UPDATE && j < ISP3X_GAIN_BASE) ||
478
+			    (j == 0x4840 || j == 0x4a80 || j == 0x4b40 || j == 0x5660))
479
+				continue;
480
+			/* skip mmu range */
481
+			if (dev->isp_ver < ISP_V30 &&
482
+			    j > ISP21_MI_BAY3D_RD_BASE_SHD && j < CSI2RX_CTRL0)
483
+				continue;
484
+			/* reg value of read diff to write */
485
+			if (j == ISP_MPFBC_CTRL ||
486
+			    j == ISP32_ISP_AWB1_GAIN_G || j == ISP32_ISP_AWB1_GAIN_RB)
487
+				reg = isp->sw_base_addr + j;
488
+			else
489
+				reg = reg_buf + j;
490
+			writel(*reg, base + j);
491
+		}
492
+
493
+		/* config shd_reg to base_reg */
494
+		for (j = 0; j < ARRAY_SIZE(backup); j++) {
495
+			reg = reg_buf + backup[j].base;
496
+			reg1 = reg_buf + backup[j].shd;
497
+			backup[j].val = *reg;
498
+			writel(*reg1, base + backup[j].base);
499
+		}
500
+
501
+		/* update module */
502
+		reg = reg_buf + DUAL_CROP_CTRL;
503
+		if (*reg & 0xf)
504
+			writel(*reg | CIF_DUAL_CROP_CFG_UPD, base + DUAL_CROP_CTRL);
505
+		reg = reg_buf + SELF_RESIZE_CTRL;
506
+		if (*reg & 0xf) {
507
+			if (dev->isp_ver == ISP_V32_L)
508
+				writel(*reg | ISP32_SCALE_FORCE_UPD, base + ISP32_SELF_SCALE_UPDATE);
509
+			else
510
+				writel(*reg | CIF_RSZ_CTRL_CFG_UPD, base + SELF_RESIZE_CTRL);
511
+		}
512
+		reg = reg_buf + MAIN_RESIZE_CTRL;
513
+		if (*reg & 0xf)
514
+			writel(*reg | CIF_RSZ_CTRL_CFG_UPD, base + MAIN_RESIZE_CTRL);
515
+		reg = reg_buf + ISP32_BP_RESIZE_CTRL;
516
+		if (*reg & 0xf)
517
+			writel(*reg | CIF_RSZ_CTRL_CFG_UPD, base + ISP32_BP_RESIZE_CTRL);
518
+
519
+		/* update mi and isp, base_reg will update to shd_reg */
520
+		writel(CIF_MI_INIT_SOFT_UPD, base + MI_WR_INIT);
521
+
522
+		/* config base_reg */
523
+		for (j = 0; j < ARRAY_SIZE(backup); j++)
524
+			writel(backup[j].val, base + backup[j].base);
525
+		/* base_reg = shd_reg, write is base but read is shd */
526
+		val = rkisp_read_reg_cache(isp, ISP_MPFBC_HEAD_PTR);
527
+		writel(val, base + ISP_MPFBC_HEAD_PTR);
528
+		val = rkisp_read_reg_cache(isp, MI_SWS_3A_WR_BASE);
529
+		writel(val, base + MI_SWS_3A_WR_BASE);
530
+	}
531
+
532
+	rkisp_params_cfgsram(&isp->params_vdev, false);
533
+
534
+	reg = reg_buf + ISP_CTRL;
535
+	*reg |= CIF_ISP_CTRL_ISP_ENABLE |
536
+		CIF_ISP_CTRL_ISP_CFG_UPD |
537
+		CIF_ISP_CTRL_ISP_INFORM_ENABLE;
538
+	writel(*reg, dev->base_addr + ISP_CTRL);
539
+	if (dev->unite == ISP_UNITE_TWO)
540
+		writel(*reg, dev->base_next_addr + ISP_CTRL);
541
+}
542
+
543
+static const char * const rk3562_isp_clks[] = {
544
+	"clk_isp_core",
295545 	"aclk_isp",
296546 	"hclk_isp",
297
-	"aclk_isp_wrap",
298
-	"hclk_isp_wrap",
299
-	"pclk_isp_wrap"
300547 };
301548 
302549 static const char * const rk3568_isp_clks[] = {
....@@ -305,35 +552,54 @@
305552 	"hclk_isp",
306553 };
307554 
555
+static const char * const rk3588_isp_clks[] = {
556
+	"clk_isp_core",
557
+	"aclk_isp",
558
+	"hclk_isp",
559
+	"clk_isp_core_marvin",
560
+	"clk_isp_core_vicap",
561
+};
562
+
563
+static const char * const rk3588_isp_unite_clks[] = {
564
+	"clk_isp_core0",
565
+	"aclk_isp0",
566
+	"hclk_isp0",
567
+	"clk_isp_core_marvin0",
568
+	"clk_isp_core_vicap0",
569
+	"clk_isp_core1",
570
+	"aclk_isp1",
571
+	"hclk_isp1",
572
+	"clk_isp_core_marvin1",
573
+	"clk_isp_core_vicap1",
574
+};
575
+
576
+static const char * const rv1106_isp_clks[] = {
577
+	"clk_isp_core",
578
+	"aclk_isp",
579
+	"hclk_isp",
580
+	"clk_isp_core_vicap",
581
+};
582
+
308583 static const char * const rv1126_isp_clks[] = {
309584 	"clk_isp",
310585 	"aclk_isp",
311586 	"hclk_isp",
312587 };
313588 
314
-/* isp clock adjustment table (MHz) */
315
-static const struct isp_clk_info rk1808_isp_clk_rate[] = {
316
-	{300, }, {400, }, {500, }, {600, }
317
-};
318
-
319
-/* isp clock adjustment table (MHz) */
320
-static const struct isp_clk_info rk3288_isp_clk_rate[] = {
321
-	{150, }, {384, }, {500, }, {594, }
322
-};
323
-
324
-/* isp clock adjustment table (MHz) */
325
-static const struct isp_clk_info rk3326_isp_clk_rate[] = {
326
-	{300, }, {347, }, {400, }, {520, }, {600, }
327
-};
328
-
329
-/* isp clock adjustment table (MHz) */
330
-static const struct isp_clk_info rk3368_isp_clk_rate[] = {
331
-	{300, }, {400, }, {600, }
332
-};
333
-
334
-/* isp clock adjustment table (MHz) */
335
-static const struct isp_clk_info rk3399_isp_clk_rate[] = {
336
-	{300, }, {400, }, {600, }
589
+static const struct isp_clk_info rk3562_isp_clk_rate[] = {
590
+	{
591
+		.clk_rate = 300,
592
+		.refer_data = 1920, //width
593
+	}, {
594
+		.clk_rate = 400,
595
+		.refer_data = 2688,
596
+	}, {
597
+		.clk_rate = 500,
598
+		.refer_data = 3072,
599
+	}, {
600
+		.clk_rate = 600,
601
+		.refer_data = 3840,
602
+	}
337603 };
338604 
339605 static const struct isp_clk_info rk3568_isp_clk_rate[] = {
....@@ -348,6 +614,41 @@
348614 		.refer_data = 3072,
349615 	}, {
350616 		.clk_rate = 600,
617
+		.refer_data = 3840,
618
+	}
619
+};
620
+
621
+static const struct isp_clk_info rk3588_isp_clk_rate[] = {
622
+	{
623
+		.clk_rate = 300,
624
+		.refer_data = 1920, //width
625
+	}, {
626
+		.clk_rate = 400,
627
+		.refer_data = 2688,
628
+	}, {
629
+		.clk_rate = 500,
630
+		.refer_data = 3072,
631
+	}, {
632
+		.clk_rate = 600,
633
+		.refer_data = 3840,
634
+	}, {
635
+		.clk_rate = 702,
636
+		.refer_data = 4672,
637
+	}
638
+};
639
+
640
+static const struct isp_clk_info rv1106_isp_clk_rate[] = {
641
+	{
642
+		.clk_rate = 200,
643
+		.refer_data = 1920, //width
644
+	}, {
645
+		.clk_rate = 200,
646
+		.refer_data = 2688,
647
+	}, {
648
+		.clk_rate = 350,
649
+		.refer_data = 3072,
650
+	}, {
651
+		.clk_rate = 440,
351652 		.refer_data = 3840,
352653 	}
353654 };
....@@ -371,31 +672,25 @@
371672 	}
372673 };
373674 
374
-static struct isp_irqs_data rk1808_isp_irqs[] = {
675
+static struct isp_irqs_data rk3562_isp_irqs[] = {
375676 	{"isp_irq", isp_irq_hdl},
376677 	{"mi_irq", mi_irq_hdl},
377678 	{"mipi_irq", mipi_irq_hdl}
378
-};
379
-
380
-static struct isp_irqs_data rk3288_isp_irqs[] = {
381
-	{"isp_irq", irq_handler}
382
-};
383
-
384
-static struct isp_irqs_data rk3326_isp_irqs[] = {
385
-	{"isp_irq", isp_irq_hdl},
386
-	{"mi_irq", mi_irq_hdl},
387
-	{"mipi_irq", mipi_irq_hdl}
388
-};
389
-
390
-static struct isp_irqs_data rk3368_isp_irqs[] = {
391
-	{"isp_irq", irq_handler}
392
-};
393
-
394
-static struct isp_irqs_data rk3399_isp_irqs[] = {
395
-	{"isp_irq", irq_handler}
396679 };
397680 
398681 static struct isp_irqs_data rk3568_isp_irqs[] = {
682
+	{"isp_irq", isp_irq_hdl},
683
+	{"mi_irq", mi_irq_hdl},
684
+	{"mipi_irq", mipi_irq_hdl}
685
+};
686
+
687
+static struct isp_irqs_data rk3588_isp_irqs[] = {
688
+	{"isp_irq", isp_irq_hdl},
689
+	{"mi_irq", mi_irq_hdl},
690
+	{"mipi_irq", mipi_irq_hdl}
691
+};
692
+
693
+static struct isp_irqs_data rv1106_isp_irqs[] = {
399694 	{"isp_irq", isp_irq_hdl},
400695 	{"mi_irq", mi_irq_hdl},
401696 	{"mipi_irq", mipi_irq_hdl}
....@@ -407,6 +702,17 @@
407702 	{"mipi_irq", mipi_irq_hdl}
408703 };
409704 
705
+static const struct isp_match_data rv1106_isp_match_data = {
706
+	.clks = rv1106_isp_clks,
707
+	.num_clks = ARRAY_SIZE(rv1106_isp_clks),
708
+	.isp_ver = ISP_V32,
709
+	.clk_rate_tbl = rv1106_isp_clk_rate,
710
+	.num_clk_rate_tbl = ARRAY_SIZE(rv1106_isp_clk_rate),
711
+	.irqs = rv1106_isp_irqs,
712
+	.num_irqs = ARRAY_SIZE(rv1106_isp_irqs),
713
+	.unite = false,
714
+};
715
+
410716 static const struct isp_match_data rv1126_isp_match_data = {
411717 	.clks = rv1126_isp_clks,
412718 	.num_clks = ARRAY_SIZE(rv1126_isp_clks),
....@@ -414,57 +720,19 @@
414720 	.clk_rate_tbl = rv1126_isp_clk_rate,
415721 	.num_clk_rate_tbl = ARRAY_SIZE(rv1126_isp_clk_rate),
416722 	.irqs = rv1126_isp_irqs,
417
-	.num_irqs = ARRAY_SIZE(rv1126_isp_irqs)
723
+	.num_irqs = ARRAY_SIZE(rv1126_isp_irqs),
724
+	.unite = false,
418725 };
419726 
420
-static const struct isp_match_data rk1808_isp_match_data = {
421
-	.clks = rk1808_isp_clks,
422
-	.num_clks = ARRAY_SIZE(rk1808_isp_clks),
423
-	.isp_ver = ISP_V13,
424
-	.clk_rate_tbl = rk1808_isp_clk_rate,
425
-	.num_clk_rate_tbl = ARRAY_SIZE(rk1808_isp_clk_rate),
426
-	.irqs = rk1808_isp_irqs,
427
-	.num_irqs = ARRAY_SIZE(rk1808_isp_irqs)
428
-};
429
-
430
-static const struct isp_match_data rk3288_isp_match_data = {
431
-	.clks = rk3288_isp_clks,
432
-	.num_clks = ARRAY_SIZE(rk3288_isp_clks),
433
-	.isp_ver = ISP_V10,
434
-	.clk_rate_tbl = rk3288_isp_clk_rate,
435
-	.num_clk_rate_tbl = ARRAY_SIZE(rk3288_isp_clk_rate),
436
-	.irqs = rk3288_isp_irqs,
437
-	.num_irqs = ARRAY_SIZE(rk3288_isp_irqs)
438
-};
439
-
440
-static const struct isp_match_data rk3326_isp_match_data = {
441
-	.clks = rk3326_isp_clks,
442
-	.num_clks = ARRAY_SIZE(rk3326_isp_clks),
443
-	.isp_ver = ISP_V12,
444
-	.clk_rate_tbl = rk3326_isp_clk_rate,
445
-	.num_clk_rate_tbl = ARRAY_SIZE(rk3326_isp_clk_rate),
446
-	.irqs = rk3326_isp_irqs,
447
-	.num_irqs = ARRAY_SIZE(rk3326_isp_irqs)
448
-};
449
-
450
-static const struct isp_match_data rk3368_isp_match_data = {
451
-	.clks = rk3368_isp_clks,
452
-	.num_clks = ARRAY_SIZE(rk3368_isp_clks),
453
-	.isp_ver = ISP_V10_1,
454
-	.clk_rate_tbl = rk3368_isp_clk_rate,
455
-	.num_clk_rate_tbl = ARRAY_SIZE(rk3368_isp_clk_rate),
456
-	.irqs = rk3368_isp_irqs,
457
-	.num_irqs = ARRAY_SIZE(rk3368_isp_irqs)
458
-};
459
-
460
-static const struct isp_match_data rk3399_isp_match_data = {
461
-	.clks = rk3399_isp_clks,
462
-	.num_clks = ARRAY_SIZE(rk3399_isp_clks),
463
-	.isp_ver = ISP_V10,
464
-	.clk_rate_tbl = rk3399_isp_clk_rate,
465
-	.num_clk_rate_tbl = ARRAY_SIZE(rk3399_isp_clk_rate),
466
-	.irqs = rk3399_isp_irqs,
467
-	.num_irqs = ARRAY_SIZE(rk3399_isp_irqs)
727
+static const struct isp_match_data rk3562_isp_match_data = {
728
+	.clks = rk3562_isp_clks,
729
+	.num_clks = ARRAY_SIZE(rk3562_isp_clks),
730
+	.isp_ver = ISP_V32_L,
731
+	.clk_rate_tbl = rk3562_isp_clk_rate,
732
+	.num_clk_rate_tbl = ARRAY_SIZE(rk3562_isp_clk_rate),
733
+	.irqs = rk3562_isp_irqs,
734
+	.num_irqs = ARRAY_SIZE(rk3562_isp_irqs),
735
+	.unite = false,
468736 };
469737 
470738 static const struct isp_match_data rk3568_isp_match_data = {
....@@ -474,32 +742,66 @@
474742 	.clk_rate_tbl = rk3568_isp_clk_rate,
475743 	.num_clk_rate_tbl = ARRAY_SIZE(rk3568_isp_clk_rate),
476744 	.irqs = rk3568_isp_irqs,
477
-	.num_irqs = ARRAY_SIZE(rk3568_isp_irqs)
745
+	.num_irqs = ARRAY_SIZE(rk3568_isp_irqs),
746
+	.unite = false,
747
+};
748
+
749
+static const struct isp_match_data rk3588_isp_match_data = {
750
+	.clks = rk3588_isp_clks,
751
+	.num_clks = ARRAY_SIZE(rk3588_isp_clks),
752
+	.isp_ver = ISP_V30,
753
+	.clk_rate_tbl = rk3588_isp_clk_rate,
754
+	.num_clk_rate_tbl = ARRAY_SIZE(rk3588_isp_clk_rate),
755
+	.irqs = rk3588_isp_irqs,
756
+	.num_irqs = ARRAY_SIZE(rk3588_isp_irqs),
757
+	.unite = false,
758
+};
759
+
760
+static const struct isp_match_data rk3588_isp_unite_match_data = {
761
+	.clks = rk3588_isp_unite_clks,
762
+	.num_clks = ARRAY_SIZE(rk3588_isp_unite_clks),
763
+	.isp_ver = ISP_V30,
764
+	.clk_rate_tbl = rk3588_isp_clk_rate,
765
+	.num_clk_rate_tbl = ARRAY_SIZE(rk3588_isp_clk_rate),
766
+	.irqs = rk3588_isp_irqs,
767
+	.num_irqs = ARRAY_SIZE(rk3588_isp_irqs),
768
+	.unite = true,
478769 };
479770 
480771 static const struct of_device_id rkisp_hw_of_match[] = {
772
+#ifdef CONFIG_CPU_RK3562
481773 	{
482
-		.compatible = "rockchip,rk1808-rkisp1",
483
-		.data = &rk1808_isp_match_data,
484
-	}, {
485
-		.compatible = "rockchip,rk3288-rkisp1",
486
-		.data = &rk3288_isp_match_data,
487
-	}, {
488
-		.compatible = "rockchip,rk3326-rkisp1",
489
-		.data = &rk3326_isp_match_data,
490
-	}, {
491
-		.compatible = "rockchip,rk3368-rkisp1",
492
-		.data = &rk3368_isp_match_data,
493
-	}, {
494
-		.compatible = "rockchip,rk3399-rkisp1",
495
-		.data = &rk3399_isp_match_data,
496
-	}, {
774
+		.compatible = "rockchip,rk3562-rkisp",
775
+		.data = &rk3562_isp_match_data,
776
+	},
777
+#endif
778
+#ifdef CONFIG_CPU_RK3568
779
+	{
497780 		.compatible = "rockchip,rk3568-rkisp",
498781 		.data = &rk3568_isp_match_data,
782
+	},
783
+#endif
784
+#ifdef CONFIG_CPU_RK3588
785
+	{
786
+		.compatible = "rockchip,rk3588-rkisp",
787
+		.data = &rk3588_isp_match_data,
499788 	}, {
789
+		.compatible = "rockchip,rk3588-rkisp-unite",
790
+		.data = &rk3588_isp_unite_match_data,
791
+	},
792
+#endif
793
+#ifdef CONFIG_CPU_RV1106
794
+	{
795
+		.compatible = "rockchip,rv1106-rkisp",
796
+		.data = &rv1106_isp_match_data,
797
+	},
798
+#endif
799
+#ifdef CONFIG_CPU_RV1126
800
+	{
500801 		.compatible = "rockchip,rv1126-rkisp",
501802 		.data = &rv1126_isp_match_data,
502803 	},
804
+#endif
503805 	{},
504806 };
505807 
....@@ -524,12 +826,23 @@
524826 void rkisp_soft_reset(struct rkisp_hw_dev *dev, bool is_secure)
525827 {
526828 	void __iomem *base = dev->base_addr;
829
+	u32 val, iccl0, iccl1, clk_ctrl0, clk_ctrl1;
830
+
831
+	/* record clk config and recover */
832
+	iccl0 = readl(base + CIF_ICCL);
833
+	clk_ctrl0 = readl(base + CTRL_VI_ISP_CLK_CTRL);
834
+	if (dev->unite == ISP_UNITE_TWO) {
835
+		iccl1 = readl(dev->base_next_addr + CIF_ICCL);
836
+		clk_ctrl1 = readl(dev->base_next_addr + CTRL_VI_ISP_CLK_CTRL);
837
+	}
527838 
528839 	if (is_secure) {
529840 		/* if isp working, cru reset isn't secure.
530841 		 * isp soft reset first to protect isp reset.
531842 		 */
532843 		writel(0xffff, base + CIF_IRCL);
844
+		if (dev->unite == ISP_UNITE_TWO)
845
+			writel(0xffff, dev->base_next_addr + CIF_IRCL);
533846 		udelay(10);
534847 	}
535848 
....@@ -543,13 +856,47 @@
543856 	/* reset for Dehaze */
544857 	if (dev->isp_ver == ISP_V20)
545858 		writel(CIF_ISP_CTRL_ISP_MODE_BAYER_ITU601, base + CIF_ISP_CTRL);
546
-	writel(0xffff, base + CIF_IRCL);
859
+	val = 0xffff;
860
+	if (dev->isp_ver == ISP_V32) {
861
+		val = 0x3fffffff;
862
+		rv1106_sdmmc_get_lock();
863
+	}
864
+	writel(val, base + CIF_IRCL);
865
+	if (dev->isp_ver == ISP_V32)
866
+		rv1106_sdmmc_put_lock();
867
+	if (dev->unite == ISP_UNITE_TWO)
868
+		writel(0xffff, dev->base_next_addr + CIF_IRCL);
547869 	udelay(10);
548870 
549871 	/* refresh iommu after reset */
550872 	if (dev->is_mmu) {
551873 		rockchip_iommu_disable(dev->dev);
552874 		rockchip_iommu_enable(dev->dev);
875
+	}
876
+
877
+	writel(iccl0, base + CIF_ICCL);
878
+	writel(clk_ctrl0, base + CTRL_VI_ISP_CLK_CTRL);
879
+	if (dev->unite == ISP_UNITE_TWO) {
880
+		writel(iccl1, dev->base_next_addr + CIF_ICCL);
881
+		writel(clk_ctrl1, dev->base_next_addr + CTRL_VI_ISP_CLK_CTRL);
882
+	}
883
+
884
+	/* default config */
885
+	if (dev->isp_ver == ISP_V12 || dev->isp_ver == ISP_V13) {
886
+		/* disable csi_rx interrupt */
887
+		writel(0, dev->base_addr + CIF_ISP_CSI0_CTRL0);
888
+		writel(0, dev->base_addr + CIF_ISP_CSI0_MASK1);
889
+		writel(0, dev->base_addr + CIF_ISP_CSI0_MASK2);
890
+		writel(0, dev->base_addr + CIF_ISP_CSI0_MASK3);
891
+	} else if (dev->isp_ver == ISP_V32) {
892
+		/* disable down samplling default */
893
+		writel(ISP32_DS_DS_DIS, dev->base_addr + ISP32_MI_MPDS_WR_CTRL);
894
+		writel(ISP32_DS_DS_DIS, dev->base_addr + ISP32_MI_BPDS_WR_CTRL);
895
+
896
+		writel(0, dev->base_addr + ISP32_BLS_ISP_OB_PREDGAIN);
897
+		writel(0x37, dev->base_addr + ISP32_MI_WR_WRAP_CTRL);
898
+	} else if (dev->isp_ver == ISP_V32_L) {
899
+		writel(0, dev->base_addr + ISP32_BLS_ISP_OB_PREDGAIN);
553900 	}
554901 }
555902 
....@@ -560,10 +907,18 @@
560907 		CIF_ICCL_SRSZ_CLK | CIF_ICCL_JPEG_CLK | CIF_ICCL_MI_CLK |
561908 		CIF_ICCL_IE_CLK | CIF_ICCL_MIPI_CLK | CIF_ICCL_DCROP_CLK;
562909 
563
-	if (dev->isp_ver == ISP_V20 && on)
910
+	if ((dev->isp_ver == ISP_V20 || dev->isp_ver >= ISP_V30) && on)
564911 		val |= ICCL_MPFBC_CLK;
565
-
912
+	if (dev->isp_ver >= ISP_V32) {
913
+		val |= ISP32_BRSZ_CLK_ENABLE | BIT(0) | BIT(16);
914
+		if (dev->isp_ver == ISP_V32)
915
+			rv1106_sdmmc_get_lock();
916
+	}
566917 	writel(val, dev->base_addr + CIF_ICCL);
918
+	if (dev->isp_ver == ISP_V32)
919
+		rv1106_sdmmc_put_lock();
920
+	if (dev->unite == ISP_UNITE_TWO)
921
+		writel(val, dev->base_next_addr + CIF_ICCL);
567922 
568923 	if (dev->isp_ver == ISP_V12 || dev->isp_ver == ISP_V13) {
569924 		val = !on ? 0 :
....@@ -573,7 +928,7 @@
573928 		      CIF_CLK_CTRL_CP | CIF_CLK_CTRL_IE;
574929 
575930 		writel(val, dev->base_addr + CIF_VI_ISP_CLK_CTRL_V12);
576
-	} else if (dev->isp_ver == ISP_V20 || dev->isp_ver == ISP_V21) {
931
+	} else if (dev->isp_ver >= ISP_V20) {
577932 		val = !on ? 0 :
578933 		      CLK_CTRL_MI_LDC | CLK_CTRL_MI_MP |
579934 		      CLK_CTRL_MI_JPEG | CLK_CTRL_MI_DP |
....@@ -582,9 +937,18 @@
582937 		      CLK_CTRL_MI_READ | CLK_CTRL_MI_RAWRD |
583938 		      CLK_CTRL_ISP_RAW;
584939 
585
-		if (dev->isp_ver == ISP_V20 && on)
940
+		if (dev->isp_ver >= ISP_V30)
941
+			val = 0;
942
+
943
+		if ((dev->isp_ver == ISP_V20 || dev->isp_ver == ISP_V30) && on)
586944 			val |= CLK_CTRL_ISP_3A;
945
+		if (dev->isp_ver == ISP_V32)
946
+			rv1106_sdmmc_get_lock();
587947 		writel(val, dev->base_addr + CTRL_VI_ISP_CLK_CTRL);
948
+		if (dev->isp_ver == ISP_V32)
949
+			rv1106_sdmmc_put_lock();
950
+		if (dev->unite == ISP_UNITE_TWO)
951
+			writel(val, dev->base_next_addr + CTRL_VI_ISP_CLK_CTRL);
588952 	}
589953 }
590954 
....@@ -616,25 +980,52 @@
616980 		}
617981 	}
618982 
619
-	rkisp_set_clk_rate(dev->clks[0],
620
-			   dev->clk_rate_tbl[0].clk_rate * 1000000UL);
621983 	rkisp_soft_reset(dev, false);
622984 	isp_config_clk(dev, true);
623
-
624
-	if (dev->isp_ver == ISP_V12 || dev->isp_ver == ISP_V13) {
625
-		/* disable csi_rx interrupt */
626
-		writel(0, dev->base_addr + CIF_ISP_CSI0_CTRL0);
627
-		writel(0, dev->base_addr + CIF_ISP_CSI0_MASK1);
628
-		writel(0, dev->base_addr + CIF_ISP_CSI0_MASK2);
629
-		writel(0, dev->base_addr + CIF_ISP_CSI0_MASK3);
630
-	}
631
-
632985 	return 0;
633986 err:
634987 	for (--i; i >= 0; --i)
635988 		if (!IS_ERR(dev->clks[i]))
636989 			clk_disable_unprepare(dev->clks[i]);
637990 	return ret;
991
+}
992
+
993
+static int rkisp_get_sram(struct rkisp_hw_dev *hw_dev)
994
+{
995
+	struct device *dev = hw_dev->dev;
996
+	struct rkisp_sram *sram = &hw_dev->sram;
997
+	struct device_node *np;
998
+	struct resource res;
999
+	int ret, size;
1000
+
1001
+	sram->size = 0;
1002
+	np = of_parse_phandle(dev->of_node, "rockchip,sram", 0);
1003
+	if (!np) {
1004
+		dev_warn(dev, "no find phandle sram\n");
1005
+		return -ENODEV;
1006
+	}
1007
+
1008
+	ret = of_address_to_resource(np, 0, &res);
1009
+	of_node_put(np);
1010
+	if (ret) {
1011
+		dev_err(dev, "get sram res error\n");
1012
+		return ret;
1013
+	}
1014
+	size = resource_size(&res);
1015
+	sram->dma_addr = dma_map_resource(dev, res.start, size, DMA_BIDIRECTIONAL, 0);
1016
+	if (dma_mapping_error(dev, sram->dma_addr))
1017
+		return -ENOMEM;
1018
+	sram->size = size;
1019
+	dev_info(dev, "get sram size:%d\n", size);
1020
+	return 0;
1021
+}
1022
+
1023
+static void rkisp_put_sram(struct rkisp_hw_dev *hw_dev)
1024
+{
1025
+	if (hw_dev->sram.size)
1026
+		dma_unmap_resource(hw_dev->dev, hw_dev->sram.dma_addr,
1027
+				   hw_dev->sram.size, DMA_BIDIRECTIONAL, 0);
1028
+	hw_dev->sram.size = 0;
6381029 }
6391030 
6401031 static int rkisp_hw_probe(struct platform_device *pdev)
....@@ -645,27 +1036,29 @@
6451036 	struct device *dev = &pdev->dev;
6461037 	struct rkisp_hw_dev *hw_dev;
6471038 	struct resource *res;
648
-	int i, ret;
1039
+	int i, ret, mult = 1;
6491040 	bool is_mem_reserved = true;
1041
+	u32 clk_rate = 0;
6501042 
6511043 	match = of_match_node(rkisp_hw_of_match, node);
6521044 	if (IS_ERR(match))
6531045 		return PTR_ERR(match);
1046
+	match_data = match->data;
6541047 
6551048 	hw_dev = devm_kzalloc(dev, sizeof(*hw_dev), GFP_KERNEL);
6561049 	if (!hw_dev)
6571050 		return -ENOMEM;
6581051 
1052
+	if (match_data->unite)
1053
+		mult = 2;
1054
+	hw_dev->sw_reg = devm_kzalloc(dev, RKISP_ISP_SW_REG_SIZE * mult, GFP_KERNEL);
1055
+	if (!hw_dev->sw_reg)
1056
+		return -ENOMEM;
6591057 	dev_set_drvdata(dev, hw_dev);
6601058 	hw_dev->dev = dev;
6611059 	hw_dev->is_thunderboot = IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP);
6621060 	dev_info(dev, "is_thunderboot: %d\n", hw_dev->is_thunderboot);
663
-	hw_dev->max_in.w = 0;
664
-	hw_dev->max_in.h = 0;
665
-	hw_dev->max_in.fps = 0;
666
-	of_property_read_u32_array(node, "max-input", &hw_dev->max_in.w, 3);
667
-	dev_info(dev, "max input:%dx%d@%dfps\n",
668
-		 hw_dev->max_in.w, hw_dev->max_in.h, hw_dev->max_in.fps);
1061
+
6691062 	hw_dev->grf = syscon_regmap_lookup_by_phandle(node, "rockchip,grf");
6701063 	if (IS_ERR(hw_dev->grf))
6711064 		dev_warn(dev, "Missing rockchip,grf property\n");
....@@ -689,9 +1082,51 @@
6891082 		goto err;
6901083 	}
6911084 
692
-	rkisp_monitor = device_property_read_bool(dev, "rockchip,restart-monitor-en");
1085
+	hw_dev->base_next_addr = NULL;
1086
+	if (match_data->unite) {
1087
+		res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1088
+		if (!res) {
1089
+			dev_err(dev, "get next resource failed\n");
1090
+			ret = -EINVAL;
1091
+			goto err;
1092
+		}
1093
+		hw_dev->base_next_addr = devm_ioremap_resource(dev, res);
1094
+		if (PTR_ERR(hw_dev->base_next_addr) == -EBUSY) {
1095
+			resource_size_t offset = res->start;
1096
+			resource_size_t size = resource_size(res);
6931097 
694
-	match_data = match->data;
1098
+			hw_dev->base_next_addr = devm_ioremap(dev, offset, size);
1099
+		}
1100
+
1101
+		if (IS_ERR(hw_dev->base_next_addr)) {
1102
+			dev_err(dev, "ioremap next failed\n");
1103
+			ret = PTR_ERR(hw_dev->base_next_addr);
1104
+			goto err;
1105
+		}
1106
+	}
1107
+
1108
+	hw_dev->isp_ver = match_data->isp_ver;
1109
+	if (match_data->unite) {
1110
+		hw_dev->unite = ISP_UNITE_TWO;
1111
+	} else if (device_property_read_bool(dev, "rockchip,unite-en")) {
1112
+		hw_dev->unite = ISP_UNITE_ONE;
1113
+		hw_dev->base_next_addr = hw_dev->base_addr;
1114
+	} else {
1115
+		hw_dev->unite = ISP_UNITE_NONE;
1116
+	}
1117
+
1118
+	memset(&hw_dev->max_in, 0, sizeof(hw_dev->max_in));
1119
+	if (!of_property_read_u32_array(node, "max-input", &hw_dev->max_in.w, 3)) {
1120
+		hw_dev->max_in.is_fix = true;
1121
+		if (hw_dev->unite) {
1122
+			hw_dev->max_in.w /= 2;
1123
+			hw_dev->max_in.w += RKMOUDLE_UNITE_EXTEND_PIXEL;
1124
+		}
1125
+	}
1126
+	dev_info(dev, "max input:%dx%d@%dfps\n",
1127
+		 hw_dev->max_in.w, hw_dev->max_in.h, hw_dev->max_in.fps);
1128
+
1129
+	rkisp_monitor = device_property_read_bool(dev, "rockchip,restart-monitor-en");
6951130 	hw_dev->mipi_irq = -1;
6961131 
6971132 	hw_dev->pdev = pdev;
....@@ -702,13 +1137,21 @@
7021137 	for (i = 0; i < match_data->num_clks; i++) {
7031138 		struct clk *clk = devm_clk_get(dev, match_data->clks[i]);
7041139 
705
-		if (IS_ERR(clk))
706
-			dev_dbg(dev, "failed to get %s\n", match_data->clks[i]);
1140
+		if (IS_ERR(clk)) {
1141
+			dev_err(dev, "failed to get %s\n", match_data->clks[i]);
1142
+			ret = PTR_ERR(clk);
1143
+			goto err;
1144
+		}
7071145 		hw_dev->clks[i] = clk;
7081146 	}
7091147 	hw_dev->num_clks = match_data->num_clks;
7101148 	hw_dev->clk_rate_tbl = match_data->clk_rate_tbl;
7111149 	hw_dev->num_clk_rate_tbl = match_data->num_clk_rate_tbl;
1150
+
1151
+	hw_dev->is_assigned_clk = false;
1152
+	ret = of_property_read_u32(node, "assigned-clock-rates", &clk_rate);
1153
+	if (!ret && clk_rate)
1154
+		hw_dev->is_assigned_clk = true;
7121155 
7131156 	hw_dev->reset = devm_reset_control_array_get(dev, false, false);
7141157 	if (IS_ERR(hw_dev->reset)) {
....@@ -722,14 +1165,17 @@
7221165 	else
7231166 		hw_dev->is_feature_on = false;
7241167 
1168
+	rkisp_get_sram(hw_dev);
1169
+
7251170 	hw_dev->dev_num = 0;
1171
+	hw_dev->dev_link_num = 0;
7261172 	hw_dev->cur_dev_id = 0;
7271173 	hw_dev->mipi_dev_id = 0;
728
-	hw_dev->isp_ver = match_data->isp_ver;
1174
+	hw_dev->pre_dev_id = -1;
1175
+	hw_dev->is_multi_overflow = false;
7291176 	mutex_init(&hw_dev->dev_lock);
7301177 	spin_lock_init(&hw_dev->rdbk_lock);
7311178 	atomic_set(&hw_dev->refcnt, 0);
732
-	atomic_set(&hw_dev->tb_ref, 0);
7331179 	spin_lock_init(&hw_dev->buf_lock);
7341180 	INIT_LIST_HEAD(&hw_dev->list);
7351181 	INIT_LIST_HEAD(&hw_dev->rpt_list);
....@@ -738,29 +1184,19 @@
7381184 	hw_dev->is_single = true;
7391185 	hw_dev->is_mi_update = false;
7401186 	hw_dev->is_dma_contig = true;
741
-	hw_dev->is_dma_sg_ops = false;
1187
+	hw_dev->is_dma_sg_ops = true;
7421188 	hw_dev->is_buf_init = false;
7431189 	hw_dev->is_shutdown = false;
7441190 	hw_dev->is_mmu = is_iommu_enable(dev);
7451191 	ret = of_reserved_mem_device_init(dev);
7461192 	if (ret) {
7471193 		is_mem_reserved = false;
748
-
7491194 		if (!hw_dev->is_mmu)
7501195 			dev_info(dev, "No reserved memory region. default cma area!\n");
751
-		else
752
-			hw_dev->is_dma_contig = false;
7531196 	}
754
-	if (is_mem_reserved) {
755
-		/* reserved memory using rdma_sg */
756
-		hw_dev->mem_ops = &vb2_rdma_sg_memops;
757
-		hw_dev->is_dma_sg_ops = true;
758
-	} else if (hw_dev->is_mmu) {
759
-		hw_dev->mem_ops = &vb2_dma_sg_memops;
760
-		hw_dev->is_dma_sg_ops = true;
761
-	} else {
762
-		hw_dev->mem_ops = &vb2_dma_contig_memops;
763
-	}
1197
+	if (hw_dev->is_mmu && !is_mem_reserved)
1198
+		hw_dev->is_dma_contig = false;
1199
+	hw_dev->mem_ops = &vb2_cma_sg_memops;
7641200 
7651201 	pm_runtime_enable(dev);
7661202 
....@@ -773,6 +1209,7 @@
7731209 {
7741210 	struct rkisp_hw_dev *hw_dev = platform_get_drvdata(pdev);
7751211 
1212
+	rkisp_put_sram(hw_dev);
7761213 	pm_runtime_disable(&pdev->dev);
7771214 	mutex_destroy(&hw_dev->dev_lock);
7781215 	return 0;
....@@ -783,47 +1220,134 @@
7831220 	struct rkisp_hw_dev *hw_dev = platform_get_drvdata(pdev);
7841221 
7851222 	hw_dev->is_shutdown = true;
786
-	if (pm_runtime_active(&pdev->dev))
1223
+	if (pm_runtime_active(&pdev->dev)) {
7871224 		writel(0xffff, hw_dev->base_addr + CIF_IRCL);
1225
+		if (hw_dev->unite == ISP_UNITE_TWO)
1226
+			writel(0xffff, hw_dev->base_next_addr + CIF_IRCL);
1227
+	}
7881228 	dev_info(&pdev->dev, "%s\n", __func__);
7891229 }
7901230 
7911231 static int __maybe_unused rkisp_runtime_suspend(struct device *dev)
7921232 {
7931233 	struct rkisp_hw_dev *hw_dev = dev_get_drvdata(dev);
1234
+	int i;
7941235 
1236
+	hw_dev->is_idle = true;
1237
+	if (dev->power.runtime_status) {
1238
+		hw_dev->dev_link_num = 0;
1239
+		hw_dev->is_single = true;
1240
+		hw_dev->is_multi_overflow = false;
1241
+		hw_dev->is_frm_buf = false;
1242
+	} else {
1243
+		/* system suspend */
1244
+		for (i = 0; i < hw_dev->dev_num; i++) {
1245
+			if (hw_dev->isp_size[i].is_on) {
1246
+				rkisp_hw_reg_save(hw_dev);
1247
+				break;
1248
+			}
1249
+		}
1250
+	}
7951251 	disable_sys_clk(hw_dev);
7961252 	return pinctrl_pm_select_sleep_state(dev);
1253
+}
1254
+
1255
+void rkisp_hw_enum_isp_size(struct rkisp_hw_dev *hw_dev)
1256
+{
1257
+	struct rkisp_device *isp;
1258
+	u32 w, h, i;
1259
+
1260
+	if (!hw_dev->max_in.is_fix) {
1261
+		hw_dev->max_in.w = 0;
1262
+		hw_dev->max_in.h = 0;
1263
+	}
1264
+	hw_dev->dev_link_num = 0;
1265
+	hw_dev->is_single = true;
1266
+	hw_dev->is_multi_overflow = false;
1267
+	hw_dev->is_frm_buf = false;
1268
+	for (i = 0; i < hw_dev->dev_num; i++) {
1269
+		isp = hw_dev->isp[i];
1270
+		if (!isp || (isp && !isp->is_hw_link))
1271
+			continue;
1272
+		if (hw_dev->dev_link_num++)
1273
+			hw_dev->is_single = false;
1274
+		w = isp->isp_sdev.in_crop.width;
1275
+		h = isp->isp_sdev.in_crop.height;
1276
+		if (hw_dev->unite)
1277
+			w = w / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL;
1278
+		hw_dev->isp_size[i].w = w;
1279
+		hw_dev->isp_size[i].h = h;
1280
+		hw_dev->isp_size[i].size = w * h;
1281
+		if (!hw_dev->max_in.is_fix) {
1282
+			if (hw_dev->max_in.w < w)
1283
+				hw_dev->max_in.w = w;
1284
+			if (hw_dev->max_in.h < h)
1285
+				hw_dev->max_in.h = h;
1286
+		}
1287
+	}
1288
+	if (hw_dev->unite == ISP_UNITE_ONE)
1289
+		hw_dev->is_single = false;
1290
+	for (i = 0; i < hw_dev->dev_num; i++) {
1291
+		isp = hw_dev->isp[i];
1292
+		if (!isp || (isp && !isp->is_hw_link))
1293
+			continue;
1294
+		rkisp_params_check_bigmode(&isp->params_vdev);
1295
+	}
7971296 }
7981297 
7991298 static int __maybe_unused rkisp_runtime_resume(struct device *dev)
8001299 {
8011300 	struct rkisp_hw_dev *hw_dev = dev_get_drvdata(dev);
8021301 	void __iomem *base = hw_dev->base_addr;
1302
+	struct rkisp_device *isp;
1303
+	int mult = hw_dev->unite ? 2 : 1;
8031304 	int ret, i;
1305
+	void *buf;
8041306 
8051307 	ret = pinctrl_pm_select_default_state(dev);
8061308 	if (ret < 0)
8071309 		return ret;
8081310 
8091311 	enable_sys_clk(hw_dev);
1312
+	if (dev->power.runtime_status) {
1313
+		if (!hw_dev->is_assigned_clk) {
1314
+			unsigned long rate = hw_dev->clk_rate_tbl[0].clk_rate * 1000000UL;
8101315 
811
-	for (i = 0; i < hw_dev->dev_num; i++) {
812
-		void *buf = hw_dev->isp[i]->sw_base_addr;
813
-
814
-		memset(buf, 0, RKISP_ISP_SW_MAX_SIZE);
815
-		memcpy_fromio(buf, base, RKISP_ISP_SW_REG_SIZE);
816
-		default_sw_reg_flag(hw_dev->isp[i]);
1316
+			rkisp_set_clk_rate(hw_dev->clks[0], rate);
1317
+			if (hw_dev->unite == ISP_UNITE_TWO)
1318
+				rkisp_set_clk_rate(hw_dev->clks[5], rate);
1319
+		}
1320
+		for (i = 0; i < hw_dev->dev_num; i++) {
1321
+			isp = hw_dev->isp[i];
1322
+			if (!isp || !isp->sw_base_addr)
1323
+				continue;
1324
+			buf = isp->sw_base_addr;
1325
+			memset(buf, 0, RKISP_ISP_SW_MAX_SIZE * mult);
1326
+			memcpy_fromio(buf, base, RKISP_ISP_SW_REG_SIZE);
1327
+			if (hw_dev->unite) {
1328
+				buf += RKISP_ISP_SW_MAX_SIZE;
1329
+				base = hw_dev->base_next_addr;
1330
+				memcpy_fromio(buf, base, RKISP_ISP_SW_REG_SIZE);
1331
+			}
1332
+			default_sw_reg_flag(hw_dev->isp[i]);
1333
+		}
1334
+		rkisp_hw_enum_isp_size(hw_dev);
1335
+		hw_dev->monitor.is_en = rkisp_monitor;
1336
+	} else {
1337
+		/* system resume */
1338
+		for (i = 0; i < hw_dev->dev_num; i++) {
1339
+			if (hw_dev->isp_size[i].is_on) {
1340
+				rkisp_hw_reg_restore(hw_dev);
1341
+				break;
1342
+			}
1343
+		}
8171344 	}
818
-	hw_dev->monitor.is_en = rkisp_monitor;
8191345 	return 0;
8201346 }
8211347 
8221348 static const struct dev_pm_ops rkisp_hw_pm_ops = {
823
-	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
824
-				pm_runtime_force_resume)
825
-	SET_RUNTIME_PM_OPS(rkisp_runtime_suspend,
826
-			   rkisp_runtime_resume, NULL)
1349
+	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
1350
+	SET_RUNTIME_PM_OPS(rkisp_runtime_suspend, rkisp_runtime_resume, NULL)
8271351 };
8281352 
8291353 static struct platform_driver rkisp_hw_drv = {
....@@ -851,4 +1375,15 @@
8511375 	return ret;
8521376 }
8531377 
1378
+static void __exit rkisp_hw_drv_exit(void)
1379
+{
1380
+	platform_driver_unregister(&rkisp_plat_drv);
1381
+	platform_driver_unregister(&rkisp_hw_drv);
1382
+}
1383
+
1384
+#if defined(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP) && !defined(CONFIG_INITCALL_ASYNC)
1385
+subsys_initcall(rkisp_hw_drv_init);
1386
+#else
8541387 module_init(rkisp_hw_drv_init);
1388
+#endif
1389
+module_exit(rkisp_hw_drv_exit);