forked from ~ljy/RK356X_SDK_RELEASE

blame | history | patch | commit | commitdiff
hc
2024-05-10 9999e48639b3cecb08ffb37358bcba3b48161b29 
 kernel/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
....@@ -1,87 +1,126 @@
1
+/* SPDX-License-Identifier: GPL-2.0-only */
12 /*
23  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
34  * Author:Mark Yao <mark.yao@rock-chips.com>
45  *
56  * based on exynos_drm_drv.h
6
- *
7
- * This software is licensed under the terms of the GNU General Public
8
- * License version 2, as published by the Free Software Foundation, and
9
- * may be copied, distributed, and modified under those terms.
10
- *
11
- * This program is distributed in the hope that it will be useful,
12
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
13
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14
- * GNU General Public License for more details.
157  */
168 
179 #ifndef _ROCKCHIP_DRM_DRV_H
1810 #define _ROCKCHIP_DRM_DRV_H
1911 
20
-#include <drm/drm_crtc.h>
21
-#include <drm/drm_fb_helper.h>
2212 #include <drm/drm_atomic_helper.h>
13
+#include <drm/drm_dsc.h>
14
+#include <drm/drm_fb_helper.h>
15
+#include <drm/drm_fourcc.h>
2316 #include <drm/drm_gem.h>
2417 #include <drm/rockchip_drm.h>
25
-
2618 #include <linux/module.h>
2719 #include <linux/component.h>
28
-#include <linux/dmabuf_page_pool.h>
20
+
21
+#include <soc/rockchip/rockchip_dmc.h>
22
+
23
+#include "../panel/panel-simple.h"
24
+
25
+#include "rockchip_drm_debugfs.h"
2926 
3027 #define ROCKCHIP_MAX_FB_BUFFER	3
3128 #define ROCKCHIP_MAX_CONNECTOR	2
3229 #define ROCKCHIP_MAX_CRTC	4
3330 #define ROCKCHIP_MAX_LAYER	16
3431 
32
+
3533 struct drm_device;
3634 struct drm_connector;
3735 struct iommu_domain;
36
+
37
+#define VOP_COLOR_KEY_NONE	(0 << 31)
38
+#define VOP_COLOR_KEY_MASK	(1 << 31)
39
+
40
+#define VOP_OUTPUT_IF_RGB	BIT(0)
41
+#define VOP_OUTPUT_IF_BT1120	BIT(1)
42
+#define VOP_OUTPUT_IF_BT656	BIT(2)
43
+#define VOP_OUTPUT_IF_LVDS0	BIT(3)
44
+#define VOP_OUTPUT_IF_LVDS1	BIT(4)
45
+#define VOP_OUTPUT_IF_MIPI0	BIT(5)
46
+#define VOP_OUTPUT_IF_MIPI1	BIT(6)
47
+#define VOP_OUTPUT_IF_eDP0	BIT(7)
48
+#define VOP_OUTPUT_IF_eDP1	BIT(8)
49
+#define VOP_OUTPUT_IF_DP0	BIT(9)
50
+#define VOP_OUTPUT_IF_DP1	BIT(10)
51
+#define VOP_OUTPUT_IF_HDMI0	BIT(11)
52
+#define VOP_OUTPUT_IF_HDMI1	BIT(12)
53
+
54
+#ifndef DRM_FORMAT_NV20
55
+#define DRM_FORMAT_NV20		fourcc_code('N', 'V', '2', '0') /* 2x1 subsampled Cr:Cb plane */
56
+#endif
57
+
58
+#ifndef DRM_FORMAT_NV30
59
+#define DRM_FORMAT_NV30		fourcc_code('N', 'V', '3', '0') /* non-subsampled Cr:Cb plane */
60
+#endif
61
+
62
+#define RK_IF_PROP_COLOR_DEPTH		"color_depth"
63
+#define RK_IF_PROP_COLOR_FORMAT		"color_format"
64
+#define RK_IF_PROP_COLOR_DEPTH_CAPS	"color_depth_caps"
65
+#define RK_IF_PROP_COLOR_FORMAT_CAPS	"color_format_caps"
66
+#define RK_IF_PROP_ENCRYPTED		"hdcp_encrypted"
67
+
68
+enum rockchip_drm_debug_category {
69
+	VOP_DEBUG_PLANE		= BIT(0),
70
+	VOP_DEBUG_OVERLAY	= BIT(1),
71
+	VOP_DEBUG_WB		= BIT(2),
72
+	VOP_DEBUG_CFG_DONE	= BIT(3),
73
+	VOP_DEBUG_VSYNC		= BIT(7),
74
+};
75
+
76
+enum rk_if_color_depth {
77
+	RK_IF_DEPTH_8,
78
+	RK_IF_DEPTH_10,
79
+	RK_IF_DEPTH_12,
80
+	RK_IF_DEPTH_16,
81
+	RK_IF_DEPTH_420_10,
82
+	RK_IF_DEPTH_420_12,
83
+	RK_IF_DEPTH_420_16,
84
+	RK_IF_DEPTH_6,
85
+	RK_IF_DEPTH_MAX,
86
+};
87
+
88
+enum rk_if_color_format {
89
+	RK_IF_FORMAT_RGB, /* default RGB */
90
+	RK_IF_FORMAT_YCBCR444, /* YCBCR 444 */
91
+	RK_IF_FORMAT_YCBCR422, /* YCBCR 422 */
92
+	RK_IF_FORMAT_YCBCR420, /* YCBCR 420 */
93
+	RK_IF_FORMAT_YCBCR_HQ, /* Highest subsampled YUV */
94
+	RK_IF_FORMAT_YCBCR_LQ, /* Lowest subsampled YUV */
95
+	RK_IF_FORMAT_MAX,
96
+};
97
+
98
+enum rockchip_hdcp_encrypted {
99
+	RK_IF_HDCP_ENCRYPTED_NONE = 0,
100
+	RK_IF_HDCP_ENCRYPTED_LEVEL1,
101
+	RK_IF_HDCP_ENCRYPTED_LEVEL2,
102
+};
103
+
104
+enum rockchip_color_bar_mode {
105
+	ROCKCHIP_COLOR_BAR_OFF = 0,
106
+	ROCKCHIP_COLOR_BAR_HORIZONTAL = 1,
107
+	ROCKCHIP_COLOR_BAR_VERTICAL = 2,
108
+};
109
+
110
+enum rockchip_drm_split_area {
111
+	ROCKCHIP_DRM_SPLIT_UNSET = 0,
112
+	ROCKCHIP_DRM_SPLIT_LEFT_SIDE = 1,
113
+	ROCKCHIP_DRM_SPLIT_RIGHT_SIDE = 2,
114
+};
38115 
39116 struct rockchip_drm_sub_dev {
40117 	struct list_head list;
41118 	struct drm_connector *connector;
42119 	struct device_node *of_node;
43
-};
44
-
45
-/*
46
- * Rockchip drm private crtc funcs.
47
- * @loader_protect: protect loader logo crtc's power
48
- * @enable_vblank: enable crtc vblank irq.
49
- * @disable_vblank: disable crtc vblank irq.
50
- * @bandwidth: report present crtc bandwidth consume.
51
- */
52
-struct rockchip_crtc_funcs {
53
-	int (*loader_protect)(struct drm_crtc *crtc, bool on);
54
-	int (*enable_vblank)(struct drm_crtc *crtc);
55
-	void (*disable_vblank)(struct drm_crtc *crtc);
56
-	size_t (*bandwidth)(struct drm_crtc *crtc,
57
-			    struct drm_crtc_state *crtc_state,
58
-			    size_t *frame_bw_mbyte,
59
-			    unsigned int *plane_num_total);
60
-	void (*cancel_pending_vblank)(struct drm_crtc *crtc,
61
-				      struct drm_file *file_priv);
62
-	int (*debugfs_init)(struct drm_minor *minor, struct drm_crtc *crtc);
63
-	int (*debugfs_dump)(struct drm_crtc *crtc, struct seq_file *s);
64
-	void (*regs_dump)(struct drm_crtc *crtc, struct seq_file *s);
65
-	void (*active_regs_dump)(struct drm_crtc *crtc, struct seq_file *s);
66
-	enum drm_mode_status (*mode_valid)(struct drm_crtc *crtc,
67
-					   const struct drm_display_mode *mode,
68
-					   int output_type);
69
-	void (*crtc_close)(struct drm_crtc *crtc);
70
-	void (*crtc_send_mcu_cmd)(struct drm_crtc *crtc, u32 type, u32 value);
71
-	void (*te_handler)(struct drm_crtc *crtc);
72
-};
73
-
74
-struct rockchip_atomic_commit {
75
-	struct drm_atomic_state *state;
76
-	struct drm_device *dev;
77
-	size_t line_bw_mbyte;
78
-	size_t frame_bw_mbyte;
79
-	unsigned int plane_num;
80
-};
81
-
82
-struct rockchip_dclk_pll {
83
-	struct clk *pll;
84
-	unsigned int use_count;
120
+	int (*loader_protect)(struct drm_encoder *encoder, bool on);
121
+	void (*oob_hotplug_event)(struct drm_connector *connector);
122
+	void (*update_vfp_for_vrr)(struct drm_connector *connector, struct drm_display_mode *mode,
123
+				   int vfp);
85124 };
86125 
87126 struct rockchip_sdr2hdr_state {
....@@ -104,9 +143,6 @@
104143 	struct rockchip_sdr2hdr_state sdr2hdr_state;
105144 };
106145 
107
-#define VOP_COLOR_KEY_NONE	(0 << 31)
108
-#define VOP_COLOR_KEY_MASK	(1 << 31)
109
-
110146 struct rockchip_bcsh_state {
111147 	int brightness;
112148 	int contrast;
....@@ -115,24 +151,88 @@
115151 	int cos_hue;
116152 };
117153 
118
-#define VOP_OUTPUT_IF_RGB	BIT(0)
119
-#define VOP_OUTPUT_IF_BT1120	BIT(1)
120
-#define VOP_OUTPUT_IF_BT656	BIT(2)
121
-#define VOP_OUTPUT_IF_LVDS0	BIT(3)
122
-#define VOP_OUTPUT_IF_LVDS1	BIT(4)
123
-#define VOP_OUTPUT_IF_MIPI0	BIT(5)
124
-#define VOP_OUTPUT_IF_MIPI1	BIT(6)
125
-#define VOP_OUTPUT_IF_eDP0	BIT(7)
126
-#define VOP_OUTPUT_IF_eDP1	BIT(8)
127
-#define VOP_OUTPUT_IF_DP0	BIT(9)
128
-#define VOP_OUTPUT_IF_DP1	BIT(10)
129
-#define VOP_OUTPUT_IF_HDMI0	BIT(11)
130
-#define VOP_OUTPUT_IF_HDMI1	BIT(12)
154
+struct rockchip_crtc {
155
+	struct drm_crtc crtc;
156
+#if defined(CONFIG_ROCKCHIP_DRM_DEBUG)
157
+	/**
158
+	 * @vop_dump_status the status of vop dump control
159
+	 * @vop_dump_list_head the list head of vop dump list
160
+	 * @vop_dump_list_init_flag init once
161
+	 * @vop_dump_times control the dump times
162
+	 * @frme_count the frame of dump buf
163
+	 */
164
+	enum vop_dump_status vop_dump_status;
165
+	struct list_head vop_dump_list_head;
166
+	bool vop_dump_list_init_flag;
167
+	int vop_dump_times;
168
+	int frame_count;
169
+#endif
170
+};
171
+
172
+struct rockchip_dsc_sink_cap {
173
+	/**
174
+	 * @slice_width: the number of pixel columns that comprise the slice width
175
+	 * @slice_height: the number of pixel rows that comprise the slice height
176
+	 * @block_pred: Does block prediction
177
+	 * @native_420: Does sink support DSC with 4:2:0 compression
178
+	 * @bpc_supported: compressed bpc supported by sink : 10, 12 or 16 bpc
179
+	 * @version_major: DSC major version
180
+	 * @version_minor: DSC minor version
181
+	 * @target_bits_per_pixel_x16: bits num after compress and multiply 16
182
+	 */
183
+	u16 slice_width;
184
+	u16 slice_height;
185
+	bool block_pred;
186
+	bool native_420;
187
+	u8 bpc_supported;
188
+	u8 version_major;
189
+	u8 version_minor;
190
+	u16 target_bits_per_pixel_x16;
191
+};
192
+
193
+#define ACM_GAIN_LUT_HY_LENGTH		(9*17)
194
+#define ACM_GAIN_LUT_HY_TOTAL_LENGTH	(ACM_GAIN_LUT_HY_LENGTH * 3)
195
+#define ACM_GAIN_LUT_HS_LENGTH		(13*17)
196
+#define ACM_GAIN_LUT_HS_TOTAL_LENGTH	(ACM_GAIN_LUT_HS_LENGTH * 3)
197
+#define ACM_DELTA_LUT_H_LENGTH		65
198
+#define ACM_DELTA_LUT_H_TOTAL_LENGTH	(ACM_DELTA_LUT_H_LENGTH * 3)
199
+
200
+struct post_acm {
201
+	s16 delta_lut_h[ACM_DELTA_LUT_H_TOTAL_LENGTH];
202
+	s16 gain_lut_hy[ACM_GAIN_LUT_HY_TOTAL_LENGTH];
203
+	s16 gain_lut_hs[ACM_GAIN_LUT_HS_TOTAL_LENGTH];
204
+	u16 y_gain;
205
+	u16 h_gain;
206
+	u16 s_gain;
207
+	u16 acm_enable;
208
+};
209
+
210
+struct post_csc {
211
+	u16 hue;
212
+	u16 saturation;
213
+	u16 contrast;
214
+	u16 brightness;
215
+	u16 r_gain;
216
+	u16 g_gain;
217
+	u16 b_gain;
218
+	u16 r_offset;
219
+	u16 g_offset;
220
+	u16 b_offset;
221
+	u16 csc_enable;
222
+};
131223 
132224 struct rockchip_crtc_state {
133225 	struct drm_crtc_state base;
134
-
135226 	int vp_id;
227
+	int output_type;
228
+	int output_mode;
229
+	int output_bpc;
230
+	int output_flags;
231
+	bool enable_afbc;
232
+	/**
233
+	 * @splice_mode: enabled when display a hdisplay > 4096 on rk3588
234
+	 */
235
+	bool splice_mode;
136236 
137237 	/**
138238 	 * @hold_mode: enabled when it's:
....@@ -163,11 +263,8 @@
163263 	int afbdc_win_xoffset;
164264 	int afbdc_win_yoffset;
165265 	int dsp_layer_sel;
166
-	int output_type;
167
-	int output_mode;
168
-	int output_bpc;
169
-	int output_flags;
170266 	u32 output_if;
267
+	u32 output_if_left_panel;
171268 	u32 bus_format;
172269 	u32 bus_flags;
173270 	int yuv_overlay;
....@@ -180,8 +277,29 @@
180277 	u32 background;
181278 	u32 line_flag;
182279 	u8 mode_update;
280
+	u8 dsc_id;
281
+	u8 dsc_enable;
282
+
283
+	u8 dsc_slice_num;
284
+	u8 dsc_pixel_num;
285
+
286
+	u64 dsc_txp_clk_rate;
287
+	u64 dsc_pxl_clk_rate;
288
+	u64 dsc_cds_clk_rate;
289
+
290
+	struct drm_dsc_picture_parameter_set pps;
291
+	struct rockchip_dsc_sink_cap dsc_sink_cap;
183292 	struct rockchip_hdr_state hdr;
293
+	struct drm_property_blob *hdr_ext_data;
294
+	struct drm_property_blob *acm_lut_data;
295
+	struct drm_property_blob *post_csc_data;
296
+	struct drm_property_blob *cubic_lut_data;
297
+
298
+	int request_refresh_rate;
299
+	int max_refresh_rate;
300
+	int min_refresh_rate;
184301 };
302
+
185303 #define to_rockchip_crtc_state(s) \
186304 		container_of(s, struct rockchip_crtc_state, base)
187305 
....@@ -193,15 +311,159 @@
193311 
194312 struct rockchip_logo {
195313 	dma_addr_t dma_addr;
314
+	struct drm_mm_node logo_reserved_node;
196315 	void *kvaddr;
197316 	phys_addr_t start;
198317 	phys_addr_t size;
199318 	int count;
200319 };
201320 
321
+struct rockchip_mcu_timing {
322
+	int mcu_pix_total;
323
+	int mcu_cs_pst;
324
+	int mcu_cs_pend;
325
+	int mcu_rw_pst;
326
+	int mcu_rw_pend;
327
+	int mcu_hold_mode;
328
+};
329
+
202330 struct loader_cubic_lut {
203331 	bool enable;
204332 	u32 offset;
333
+};
334
+
335
+struct rockchip_drm_dsc_cap {
336
+	bool v_1p2;
337
+	bool native_420;
338
+	bool all_bpp;
339
+	u8 bpc_supported;
340
+	u8 max_slices;
341
+	u8 max_lanes;
342
+	u8 max_frl_rate_per_lane;
343
+	u8 total_chunk_kbytes;
344
+	int clk_per_slice;
345
+};
346
+
347
+struct ver_26_v0 {
348
+	u8 yuv422_12bit;
349
+	u8 support_2160p_60;
350
+	u8 global_dimming;
351
+	u8 dm_major_ver;
352
+	u8 dm_minor_ver;
353
+	u16 t_min_pq;
354
+	u16 t_max_pq;
355
+	u16 rx;
356
+	u16 ry;
357
+	u16 gx;
358
+	u16 gy;
359
+	u16 bx;
360
+	u16 by;
361
+	u16 wx;
362
+	u16 wy;
363
+} __packed;
364
+
365
+struct ver_15_v1 {
366
+	u8 yuv422_12bit;
367
+	u8 support_2160p_60;
368
+	u8 global_dimming;
369
+	u8 dm_version;
370
+	u8 colorimetry;
371
+	u8 t_max_lum;
372
+	u8 t_min_lum;
373
+	u8 rx;
374
+	u8 ry;
375
+	u8 gx;
376
+	u8 gy;
377
+	u8 bx;
378
+	u8 by;
379
+} __packed;
380
+
381
+struct ver_12_v1 {
382
+	u8 yuv422_12bit;
383
+	u8 support_2160p_60;
384
+	u8 global_dimming;
385
+	u8 dm_version;
386
+	u8 colorimetry;
387
+	u8 low_latency;
388
+	u8 t_max_lum;
389
+	u8 t_min_lum;
390
+	u8 unique_rx;
391
+	u8 unique_ry;
392
+	u8 unique_gx;
393
+	u8 unique_gy;
394
+	u8 unique_bx;
395
+	u8 unique_by;
396
+} __packed;
397
+
398
+struct ver_12_v2 {
399
+	u8 yuv422_12bit;
400
+	u8 backlt_ctrl;
401
+	u8 global_dimming;
402
+	u8 dm_version;
403
+	u8 backlt_min_luma;
404
+	u8 interface;
405
+	u8 yuv444_10b_12b;
406
+	u8 t_min_pq_v2;
407
+	u8 t_max_pq_v2;
408
+	u8 unique_rx;
409
+	u8 unique_ry;
410
+	u8 unique_gx;
411
+	u8 unique_gy;
412
+	u8 unique_bx;
413
+	u8 unique_by;
414
+} __packed;
415
+
416
+struct next_hdr_sink_data {
417
+	u8 version;
418
+	struct ver_26_v0 ver_26_v0;
419
+	struct ver_15_v1 ver_15_v1;
420
+	struct ver_12_v1 ver_12_v1;
421
+	struct ver_12_v2 ver_12_v2;
422
+} __packed;
423
+
424
+/*
425
+ * Rockchip drm private crtc funcs.
426
+ * @loader_protect: protect loader logo crtc's power
427
+ * @enable_vblank: enable crtc vblank irq.
428
+ * @disable_vblank: disable crtc vblank irq.
429
+ * @bandwidth: report present crtc bandwidth consume.
430
+ * @cancel_pending_vblank: cancel pending vblank.
431
+ * @debugfs_init: init crtc debugfs.
432
+ * @debugfs_dump: debugfs to dump crtc and plane state.
433
+ * @regs_dump: dump vop current register config.
434
+ * @mode_valid: verify that the current mode is supported.
435
+ * @crtc_close: close vop.
436
+ * @crtc_send_mcu_cmd: send mcu panel init cmd.
437
+ * @te_handler: soft te hand for cmd mode panel.
438
+ * @wait_vact_end: wait the last active line.
439
+ */
440
+struct rockchip_crtc_funcs {
441
+	int (*loader_protect)(struct drm_crtc *crtc, bool on, void *data);
442
+	int (*enable_vblank)(struct drm_crtc *crtc);
443
+	void (*disable_vblank)(struct drm_crtc *crtc);
444
+	size_t (*bandwidth)(struct drm_crtc *crtc,
445
+			    struct drm_crtc_state *crtc_state,
446
+			    struct dmcfreq_vop_info *vop_bw_info);
447
+	void (*cancel_pending_vblank)(struct drm_crtc *crtc,
448
+				      struct drm_file *file_priv);
449
+	int (*debugfs_init)(struct drm_minor *minor, struct drm_crtc *crtc);
450
+	int (*debugfs_dump)(struct drm_crtc *crtc, struct seq_file *s);
451
+	void (*regs_dump)(struct drm_crtc *crtc, struct seq_file *s);
452
+	void (*active_regs_dump)(struct drm_crtc *crtc, struct seq_file *s);
453
+	enum drm_mode_status (*mode_valid)(struct drm_crtc *crtc,
454
+					   const struct drm_display_mode *mode,
455
+					   int output_type);
456
+	void (*crtc_close)(struct drm_crtc *crtc);
457
+	void (*crtc_send_mcu_cmd)(struct drm_crtc *crtc, u32 type, u32 value);
458
+	void (*te_handler)(struct drm_crtc *crtc);
459
+	int (*wait_vact_end)(struct drm_crtc *crtc, unsigned int mstimeout);
460
+	void (*crtc_standby)(struct drm_crtc *crtc, bool standby);
461
+	int (*crtc_set_color_bar)(struct drm_crtc *crtc, enum rockchip_color_bar_mode mode);
462
+};
463
+
464
+struct rockchip_dclk_pll {
465
+	struct clk *pll;
466
+	unsigned int use_count;
205467 };
206468 
207469 /*
....@@ -213,42 +475,47 @@
213475  */
214476 struct rockchip_drm_private {
215477 	struct rockchip_logo *logo;
216
-	struct dmabuf_page_pool *page_pools;
217
-	struct drm_property *eotf_prop;
218
-	struct drm_property *color_space_prop;
219
-	struct drm_property *global_alpha_prop;
220
-	struct drm_property *blend_mode_prop;
221
-	struct drm_property *alpha_scale_prop;
222
-	struct drm_property *async_commit_prop;
223
-	struct drm_property *share_id_prop;
224
-	struct drm_property *connector_id_prop;
225478 	struct drm_fb_helper *fbdev_helper;
226479 	struct drm_gem_object *fbdev_bo;
227
-	const struct rockchip_crtc_funcs *crtc_funcs[ROCKCHIP_MAX_CRTC];
228
-	struct drm_atomic_state *state;
229
-
230
-	struct rockchip_atomic_commit *commit;
231
-	/* protect async commit */
480
+	struct iommu_domain *domain;
481
+	struct gen_pool *secure_buffer_pool;
482
+	struct mutex mm_lock;
483
+	struct drm_mm mm;
484
+	struct list_head psr_list;
485
+	struct mutex psr_list_lock;
232486 	struct mutex commit_lock;
487
+
488
+	/* private crtc prop */
489
+	struct drm_property *soc_id_prop;
490
+	struct drm_property *port_id_prop;
491
+	struct drm_property *aclk_prop;
492
+	struct drm_property *bg_prop;
493
+	struct drm_property *line_flag_prop;
494
+	struct drm_property *cubic_lut_prop;
495
+	struct drm_property *cubic_lut_size_prop;
496
+
497
+	/* private plane prop */
498
+	struct drm_property *eotf_prop;
499
+	struct drm_property *color_space_prop;
500
+	struct drm_property *async_commit_prop;
501
+	struct drm_property *share_id_prop;
502
+
503
+	/* private connector prop */
504
+	struct drm_property *connector_id_prop;
505
+	struct drm_property *split_area_prop;
506
+
507
+	const struct rockchip_crtc_funcs *crtc_funcs[ROCKCHIP_MAX_CRTC];
508
+
509
+	struct rockchip_dclk_pll default_pll;
510
+	struct rockchip_dclk_pll hdmi_pll;
511
+
233512 	/*
234513 	 * protect some shared overlay resource
235514 	 * OVL_LAYER_SEL/OVL_PORT_SEL
236515 	 */
237516 	struct mutex ovl_lock;
238
-	struct work_struct commit_work;
239
-	struct iommu_domain *domain;
240
-	struct gen_pool *secure_buffer_pool;
241
-	/* protect drm_mm on multi-threads */
242
-	struct mutex mm_lock;
243
-	struct drm_mm mm;
244
-	struct rockchip_dclk_pll default_pll;
245
-	struct rockchip_dclk_pll hdmi_pll;
246
-	struct devfreq *devfreq;
247
-	u8 dmc_support;
248
-	struct list_head psr_list;
249
-	struct mutex psr_list_lock;
250
-	struct rockchip_drm_vcnt vcnt[ROCKCHIP_MAX_CRTC];
251517 
518
+	struct rockchip_drm_vcnt vcnt[ROCKCHIP_MAX_CRTC];
252519 	/**
253520 	 * @loader_protect
254521 	 * ignore restore_fbdev_mode_atomic when in logo on state
....@@ -257,58 +524,78 @@
257524 
258525 	dma_addr_t cubic_lut_dma_addr;
259526 	void *cubic_lut_kvaddr;
527
+	struct drm_mm_node *clut_reserved_node;
260528 	struct loader_cubic_lut cubic_lut[ROCKCHIP_MAX_CRTC];
261529 };
262530 
263
-#ifndef MODULE
264
-void rockchip_free_loader_memory(struct drm_device *drm);
265
-#endif
266
-void rockchip_drm_atomic_work(struct work_struct *work);
531
+void rockchip_connector_update_vfp_for_vrr(struct drm_crtc *crtc, struct drm_display_mode *mode,
532
+					   int vfp);
267533 int rockchip_drm_dma_attach_device(struct drm_device *drm_dev,
268534 				   struct device *dev);
269535 void rockchip_drm_dma_detach_device(struct drm_device *drm_dev,
270536 				    struct device *dev);
537
+int rockchip_drm_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout);
271538 int rockchip_register_crtc_funcs(struct drm_crtc *crtc,
272539 				 const struct rockchip_crtc_funcs *crtc_funcs);
273540 void rockchip_unregister_crtc_funcs(struct drm_crtc *crtc);
274
-int rockchip_drm_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout);
541
+void rockchip_drm_crtc_standby(struct drm_crtc *crtc, bool standby);
275542 
276543 void rockchip_drm_register_sub_dev(struct rockchip_drm_sub_dev *sub_dev);
277544 void rockchip_drm_unregister_sub_dev(struct rockchip_drm_sub_dev *sub_dev);
278545 struct rockchip_drm_sub_dev *rockchip_drm_get_sub_dev(struct device_node *node);
279546 int rockchip_drm_add_modes_noedid(struct drm_connector *connector);
280547 void rockchip_drm_te_handle(struct drm_crtc *crtc);
281
-#if IS_ENABLED(CONFIG_DRM_ROCKCHIP)
548
+void drm_mode_convert_to_split_mode(struct drm_display_mode *mode);
549
+void drm_mode_convert_to_origin_mode(struct drm_display_mode *mode);
550
+u32 rockchip_drm_get_dclk_by_width(int width);
551
+#if IS_REACHABLE(CONFIG_DRM_ROCKCHIP)
282552 int rockchip_drm_get_sub_dev_type(void);
553
+u32 rockchip_drm_get_scan_line_time_ns(void);
283554 #else
284555 static inline int rockchip_drm_get_sub_dev_type(void)
285556 {
286557 	return DRM_MODE_CONNECTOR_Unknown;
287558 }
288
-#endif
289559 
290
-#if IS_ENABLED(CONFIG_DRM_ROCKCHIP)
291
-int rockchip_drm_crtc_send_mcu_cmd(struct drm_device *drm_dev,
292
-				   struct device_node *np_crtc,
293
-				   u32 type, u32 value);
294
-#else
295
-static inline int rockchip_drm_crtc_send_mcu_cmd(struct drm_device *drm_dev,
296
-						 struct device_node *np_crtc,
297
-						 u32 type, u32 value)
560
+static inline u32 rockchip_drm_get_scan_line_time_ns(void)
298561 {
299562 	return 0;
300563 }
301564 #endif
302565 
566
+int rockchip_drm_endpoint_is_subdriver(struct device_node *ep);
567
+uint32_t rockchip_drm_of_find_possible_crtcs(struct drm_device *dev,
568
+					     struct device_node *port);
569
+uint32_t rockchip_drm_get_bpp(const struct drm_format_info *info);
570
+uint32_t rockchip_drm_get_cycles_per_pixel(uint32_t bus_format);
571
+int rockchip_drm_get_yuv422_format(struct drm_connector *connector,
572
+				   struct edid *edid);
573
+int rockchip_drm_parse_cea_ext(struct rockchip_drm_dsc_cap *dsc_cap,
574
+			       u8 *max_frl_rate_per_lane, u8 *max_lanes, u8 *add_func,
575
+			       const struct edid *edid);
576
+int rockchip_drm_parse_next_hdr(struct next_hdr_sink_data *sink_data,
577
+				const struct edid *edid);
578
+int rockchip_drm_parse_colorimetry_data_block(u8 *colorimetry, const struct edid *edid);
579
+long rockchip_drm_dclk_round_rate(u32 version, struct clk *dclk, unsigned long rate);
580
+int rockchip_drm_dclk_set_rate(u32 version, struct clk *dclk, unsigned long rate);
581
+
582
+__printf(3, 4)
583
+void rockchip_drm_dbg(const struct device *dev, enum rockchip_drm_debug_category category,
584
+		      const char *format, ...);
585
+
303586 extern struct platform_driver cdn_dp_driver;
304587 extern struct platform_driver dw_hdmi_rockchip_pltfm_driver;
305
-extern struct platform_driver dw_mipi_dsi_driver;
588
+extern struct platform_driver dw_mipi_dsi_rockchip_driver;
589
+extern struct platform_driver dw_mipi_dsi2_rockchip_driver;
306590 extern struct platform_driver inno_hdmi_driver;
307591 extern struct platform_driver rockchip_dp_driver;
308592 extern struct platform_driver rockchip_lvds_driver;
309
-extern struct platform_driver rockchip_tve_driver;
310593 extern struct platform_driver vop_platform_driver;
311594 extern struct platform_driver vop2_platform_driver;
312
-extern struct platform_driver vvop_platform_driver;
595
+extern struct platform_driver rk3066_hdmi_driver;
313596 extern struct platform_driver rockchip_rgb_driver;
597
+extern struct platform_driver rockchip_tve_driver;
598
+extern struct platform_driver dw_dp_driver;
599
+extern struct platform_driver vconn_platform_driver;
600
+extern struct platform_driver vvop_platform_driver;
314601 #endif /* _ROCKCHIP_DRM_DRV_H_ */