hc
2024-05-10 9999e48639b3cecb08ffb37358bcba3b48161b29
kernel/drivers/gpu/drm/radeon/radeon_vm.c
....@@ -25,7 +25,7 @@
2525 * Alex Deucher
2626 * Jerome Glisse
2727 */
28
-#include <drm/drmP.h>
28
+
2929 #include <drm/radeon_drm.h>
3030 #include "radeon.h"
3131 #include "radeon_trace.h"
....@@ -142,7 +142,7 @@
142142 list[0].preferred_domains = RADEON_GEM_DOMAIN_VRAM;
143143 list[0].allowed_domains = RADEON_GEM_DOMAIN_VRAM;
144144 list[0].tv.bo = &vm->page_directory->tbo;
145
- list[0].tv.shared = true;
145
+ list[0].tv.num_shared = 1;
146146 list[0].tiling_flags = 0;
147147 list_add(&list[0].tv.head, head);
148148
....@@ -154,7 +154,7 @@
154154 list[idx].preferred_domains = RADEON_GEM_DOMAIN_VRAM;
155155 list[idx].allowed_domains = RADEON_GEM_DOMAIN_VRAM;
156156 list[idx].tv.bo = &list[idx].robj->tbo;
157
- list[idx].tv.shared = true;
157
+ list[idx].tv.num_shared = 1;
158158 list[idx].tiling_flags = 0;
159159 list_add(&list[idx++].tv.head, head);
160160 }
....@@ -188,7 +188,7 @@
188188 vm_id->last_id_use == rdev->vm_manager.active[vm_id->id])
189189 return NULL;
190190
191
- /* we definately need to flush */
191
+ /* we definitely need to flush */
192192 vm_id->pd_gpu_addr = ~0ll;
193193
194194 /* skip over VMID 0, since it is the system VM */
....@@ -296,9 +296,9 @@
296296 struct radeon_bo_va *bo_va;
297297
298298 list_for_each_entry(bo_va, &bo->va, bo_list) {
299
- if (bo_va->vm == vm) {
299
+ if (bo_va->vm == vm)
300300 return bo_va;
301
- }
301
+
302302 }
303303 return NULL;
304304 }
....@@ -323,9 +323,9 @@
323323 struct radeon_bo_va *bo_va;
324324
325325 bo_va = kzalloc(sizeof(struct radeon_bo_va), GFP_KERNEL);
326
- if (bo_va == NULL) {
326
+ if (bo_va == NULL)
327327 return NULL;
328
- }
328
+
329329 bo_va->vm = vm;
330330 bo_va->bo = bo;
331331 bo_va->it.start = 0;
....@@ -702,7 +702,7 @@
702702 if (ib.length_dw != 0) {
703703 radeon_asic_vm_pad_ib(rdev, &ib);
704704
705
- radeon_sync_resv(rdev, &ib.sync, pd->tbo.resv, true);
705
+ radeon_sync_resv(rdev, &ib.sync, pd->tbo.base.resv, true);
706706 WARN_ON(ib.length_dw > ndw);
707707 r = radeon_ib_schedule(rdev, &ib, NULL, false);
708708 if (r) {
....@@ -830,8 +830,8 @@
830830 uint64_t pte;
831831 int r;
832832
833
- radeon_sync_resv(rdev, &ib->sync, pt->tbo.resv, true);
834
- r = reservation_object_reserve_shared(pt->tbo.resv);
833
+ radeon_sync_resv(rdev, &ib->sync, pt->tbo.base.resv, true);
834
+ r = dma_resv_reserve_shared(pt->tbo.base.resv, 1);
835835 if (r)
836836 return r;
837837
....@@ -911,7 +911,7 @@
911911 */
912912 int radeon_vm_bo_update(struct radeon_device *rdev,
913913 struct radeon_bo_va *bo_va,
914
- struct ttm_mem_reg *mem)
914
+ struct ttm_resource *mem)
915915 {
916916 struct radeon_vm *vm = bo_va->vm;
917917 struct radeon_ib ib;
....@@ -942,14 +942,14 @@
942942 bo_va->flags &= ~RADEON_VM_PAGE_VALID;
943943 bo_va->flags &= ~RADEON_VM_PAGE_SYSTEM;
944944 bo_va->flags &= ~RADEON_VM_PAGE_SNOOPED;
945
- if (bo_va->bo && radeon_ttm_tt_is_readonly(bo_va->bo->tbo.ttm))
945
+ if (bo_va->bo && radeon_ttm_tt_is_readonly(rdev, bo_va->bo->tbo.ttm))
946946 bo_va->flags &= ~RADEON_VM_PAGE_WRITEABLE;
947947
948948 if (mem) {
949
- addr = mem->start << PAGE_SHIFT;
950
- if (mem->mem_type != TTM_PL_SYSTEM) {
949
+ addr = (u64)mem->start << PAGE_SHIFT;
950
+ if (mem->mem_type != TTM_PL_SYSTEM)
951951 bo_va->flags |= RADEON_VM_PAGE_VALID;
952
- }
952
+
953953 if (mem->mem_type == TTM_PL_TT) {
954954 bo_va->flags |= RADEON_VM_PAGE_SYSTEM;
955955 if (!(bo_va->bo->flags & (RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC)))
....@@ -1233,9 +1233,9 @@
12331233 struct radeon_bo_va *bo_va, *tmp;
12341234 int i, r;
12351235
1236
- if (!RB_EMPTY_ROOT(&vm->va.rb_root)) {
1236
+ if (!RB_EMPTY_ROOT(&vm->va.rb_root))
12371237 dev_err(rdev->dev, "still active bo inside vm\n");
1238
- }
1238
+
12391239 rbtree_postorder_for_each_entry_safe(bo_va, tmp,
12401240 &vm->va.rb_root, it.rb) {
12411241 interval_tree_remove(&bo_va->it, &vm->va);