add ax88772_rst

hc

2024-05-10 9999e48639b3cecb08ffb37358bcba3b48161b29

 kernel/drivers/gpu/drm/radeon/radeon_device.c
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@@ -25,16 +25,23 @@
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  *          Alex Deucher
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  *          Jerome Glisse
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  */
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+
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 #include <linux/console.h>
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-#include <linux/slab.h>
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-#include <drm/drmP.h>
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-#include <drm/drm_crtc_helper.h>
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-#include <drm/drm_cache.h>
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-#include <drm/radeon_drm.h>
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-#include <linux/pm_runtime.h>
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-#include <linux/vgaarb.h>
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-#include <linux/vga_switcheroo.h>
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 #include <linux/efi.h>
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+#include <linux/pci.h>
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+#include <linux/pm_runtime.h>
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+#include <linux/slab.h>
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+#include <linux/vga_switcheroo.h>
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+#include <linux/vgaarb.h>
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+
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+#include <drm/drm_cache.h>
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+#include <drm/drm_crtc_helper.h>
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+#include <drm/drm_debugfs.h>
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+#include <drm/drm_device.h>
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+#include <drm/drm_file.h>
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+#include <drm/drm_probe_helper.h>
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+#include <drm/radeon_drm.h>
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+
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 #include "radeon_reg.h"
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 #include "radeon.h"
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 #include "atom.h"
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@@ -1015,6 +1022,7 @@
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 {
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 	if (rdev->mode_info.atom_context) {
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 		kfree(rdev->mode_info.atom_context->scratch);
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+		kfree(rdev->mode_info.atom_context->iio);
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 	}
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 	kfree(rdev->mode_info.atom_context);
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 	rdev->mode_info.atom_context = NULL;
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@@ -1256,7 +1264,7 @@
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 	 * locking inversion with the driver load path. And the access here is
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 	 * completely racy anyway. So don't bother with locking for now.
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 	 */
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-	return dev->open_count == 0;
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+	return atomic_read(&dev->open_count) == 0;
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 }
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 static const struct vga_switcheroo_client_ops radeon_switcheroo_ops = {
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@@ -1318,8 +1326,6 @@
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 	init_rwsem(&rdev->pm.mclk_lock);
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 	init_rwsem(&rdev->exclusive_lock);
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 	init_waitqueue_head(&rdev->irq.vblank_queue);
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-	mutex_init(&rdev->mn_lock);
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-	hash_init(rdev->mn_hash);
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 	r = radeon_gem_init(rdev);
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 	if (r)
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 		return r;
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@@ -1358,36 +1364,29 @@
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 	else
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 		rdev->mc.mc_mask = 0xffffffffULL; /* 32 bit MC */
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-	/* set DMA mask + need_dma32 flags.
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+	/* set DMA mask.
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 	 * PCIE - can handle 40-bits.
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 	 * IGP - can handle 40-bits
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 	 * AGP - generally dma32 is safest
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 	 * PCI - dma32 for legacy pci gart, 40 bits on newer asics
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 	 */
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-	rdev->need_dma32 = false;
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+	dma_bits = 40;
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 	if (rdev->flags & RADEON_IS_AGP)
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-		rdev->need_dma32 = true;
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+		dma_bits = 32;
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 	if ((rdev->flags & RADEON_IS_PCI) &&
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 	    (rdev->family <= CHIP_RS740))
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-		rdev->need_dma32 = true;
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+		dma_bits = 32;
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 #ifdef CONFIG_PPC64
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 	if (rdev->family == CHIP_CEDAR)
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-		rdev->need_dma32 = true;
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+		dma_bits = 32;
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 #endif
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-	dma_bits = rdev->need_dma32 ? 32 : 40;
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-	r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
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+	r = dma_set_mask_and_coherent(&rdev->pdev->dev, DMA_BIT_MASK(dma_bits));
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 	if (r) {
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-		rdev->need_dma32 = true;
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-		dma_bits = 32;
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 		pr_warn("radeon: No suitable DMA available\n");
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+		return r;
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 	}
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-	r = pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
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-	if (r) {
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-		pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(32));
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-		pr_warn("radeon: No coherent DMA available\n");
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-	}
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-	rdev->need_swiotlb = drm_get_max_iomem() > ((u64)1 << dma_bits);
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+	rdev->need_swiotlb = drm_need_swiotlb(dma_bits);
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 	/* Registers mapping */
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 	/* TODO: block userspace mapping of io register */
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@@ -1625,6 +1624,9 @@
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 		if (r) {
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 			/* delay GPU reset to resume */
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 			radeon_fence_driver_force_completion(rdev, i);
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+		} else {
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+			/* finish executing delayed work */
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+			flush_delayed_work(&rdev->fence_drv[i].lockup_work);
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 		}
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 	}
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