add ax88772_rst

hc

2024-05-10 9999e48639b3cecb08ffb37358bcba3b48161b29

 kernel/drivers/gpu/drm/pl111/pl111_drm.h
..
..
@@ -1,32 +1,100 @@
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+/* SPDX-License-Identifier: GPL-2.0-only */
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 /*
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  *
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  * (C) COPYRIGHT 2012-2013 ARM Limited. All rights reserved.
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- *
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  *
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  * Parts of this file were based on sources as follows:
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  *
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  * Copyright (c) 2006-2008 Intel Corporation
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  * Copyright (c) 2007 Dave Airlie <airlied@linux.ie>
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  * Copyright (C) 2011 Texas Instruments
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- *
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- * This program is free software and is provided to you under the terms of the
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- * GNU General Public License version 2 as published by the Free Software
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- * Foundation, and any use by you of this program is subject to the terms of
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- * such GNU licence.
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- *
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  */
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 #ifndef _PL111_DRM_H_
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 #define _PL111_DRM_H_
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-#include <drm/drm_gem.h>
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-#include <drm/drm_simple_kms_helper.h>
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-#include <drm/drm_connector.h>
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-#include <drm/drm_encoder.h>
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-#include <drm/drm_panel.h>
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-#include <drm/drm_bridge.h>
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 #include <linux/clk-provider.h>
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 #include <linux/interrupt.h>
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+
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+#include <drm/drm_bridge.h>
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+#include <drm/drm_connector.h>
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+#include <drm/drm_encoder.h>
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+#include <drm/drm_gem.h>
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+#include <drm/drm_panel.h>
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+#include <drm/drm_simple_kms_helper.h>
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+
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+/*
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+ * CLCD Controller Internal Register addresses
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+ */
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+#define CLCD_TIM0		0x00000000
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+#define CLCD_TIM1		0x00000004
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+#define CLCD_TIM2		0x00000008
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+#define CLCD_TIM3		0x0000000c
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+#define CLCD_UBAS		0x00000010
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+#define CLCD_LBAS		0x00000014
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+
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+#define CLCD_PL110_IENB		0x00000018
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+#define CLCD_PL110_CNTL		0x0000001c
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+#define CLCD_PL110_STAT		0x00000020
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+#define CLCD_PL110_INTR		0x00000024
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+#define CLCD_PL110_UCUR		0x00000028
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+#define CLCD_PL110_LCUR		0x0000002C
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+
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+#define CLCD_PL111_CNTL		0x00000018
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+#define CLCD_PL111_IENB		0x0000001c
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+#define CLCD_PL111_RIS		0x00000020
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+#define CLCD_PL111_MIS		0x00000024
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+#define CLCD_PL111_ICR		0x00000028
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+#define CLCD_PL111_UCUR		0x0000002c
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+#define CLCD_PL111_LCUR		0x00000030
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+
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+#define CLCD_PALL		0x00000200
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+#define CLCD_PALETTE		0x00000200
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+
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+#define TIM2_PCD_LO_MASK	GENMASK(4, 0)
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+#define TIM2_PCD_LO_BITS	5
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+#define TIM2_CLKSEL		(1 << 5)
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+#define TIM2_ACB_MASK		GENMASK(10, 6)
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+#define TIM2_IVS		(1 << 11)
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+#define TIM2_IHS		(1 << 12)
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+#define TIM2_IPC		(1 << 13)
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+#define TIM2_IOE		(1 << 14)
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+#define TIM2_BCD		(1 << 26)
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+#define TIM2_PCD_HI_MASK	GENMASK(31, 27)
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+#define TIM2_PCD_HI_BITS	5
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+#define TIM2_PCD_HI_SHIFT	27
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+
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+#define CNTL_LCDEN		(1 << 0)
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+#define CNTL_LCDBPP1		(0 << 1)
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+#define CNTL_LCDBPP2		(1 << 1)
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+#define CNTL_LCDBPP4		(2 << 1)
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+#define CNTL_LCDBPP8		(3 << 1)
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+#define CNTL_LCDBPP16		(4 << 1)
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+#define CNTL_LCDBPP16_565	(6 << 1)
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+#define CNTL_LCDBPP16_444	(7 << 1)
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+#define CNTL_LCDBPP24		(5 << 1)
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+#define CNTL_LCDBW		(1 << 4)
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+#define CNTL_LCDTFT		(1 << 5)
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+#define CNTL_LCDMONO8		(1 << 6)
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+#define CNTL_LCDDUAL		(1 << 7)
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+#define CNTL_BGR		(1 << 8)
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+#define CNTL_BEBO		(1 << 9)
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+#define CNTL_BEPO		(1 << 10)
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+#define CNTL_LCDPWR		(1 << 11)
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+#define CNTL_LCDVCOMP(x)	((x) << 12)
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+#define CNTL_LDMAFIFOTIME	(1 << 15)
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+#define CNTL_WATERMARK		(1 << 16)
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+
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+/* ST Microelectronics variant bits */
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+#define CNTL_ST_1XBPP_444	0x0
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+#define CNTL_ST_1XBPP_5551	(1 << 17)
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+#define CNTL_ST_1XBPP_565	(1 << 18)
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+#define CNTL_ST_CDWID_12	0x0
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+#define CNTL_ST_CDWID_16	(1 << 19)
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+#define CNTL_ST_CDWID_18	(1 << 20)
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+#define CNTL_ST_CDWID_24	((1 << 19) | (1 << 20))
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+#define CNTL_ST_CEAEN		(1 << 21)
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+#define CNTL_ST_LCDBPP24_PACKED	(6 << 1)
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 #define CLCD_IRQ_NEXTBASE_UPDATE BIT(2)
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..
..
@@ -89,6 +157,6 @@
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 int pl111_display_init(struct drm_device *dev);
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 irqreturn_t pl111_irq(int irq, void *data);
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-int pl111_debugfs_init(struct drm_minor *minor);
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+void pl111_debugfs_init(struct drm_minor *minor);
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 #endif /* _PL111_DRM_H_ */