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2024-05-10 9999e48639b3cecb08ffb37358bcba3b48161b29 
 kernel/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
....@@ -1,19 +1,8 @@
1
+/* SPDX-License-Identifier: GPL-2.0-only */
12 /*
23  * Copyright (c) 2015-2018 The Linux Foundation. All rights reserved.
34  * Copyright (C) 2013 Red Hat
45  * Author: Rob Clark <robdclark@gmail.com>
5
- *
6
- * This program is free software; you can redistribute it and/or modify it
7
- * under the terms of the GNU General Public License version 2 as published by
8
- * the Free Software Foundation.
9
- *
10
- * This program is distributed in the hope that it will be useful, but WITHOUT
11
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
- * more details.
14
- *
15
- * You should have received a copy of the GNU General Public License along with
16
- * this program.  If not, see <http://www.gnu.org/licenses/>.
176  */
187 
198 #ifndef _DPU_CRTC_H_
....@@ -83,15 +72,15 @@
8372 /**
8473  * struct dpu_crtc_mixer: stores the map for each virtual pipeline in the CRTC
8574  * @hw_lm:	LM HW Driver context
86
- * @hw_ctl:	CTL Path HW driver context
87
- * @encoder:	Encoder attached to this lm & ctl
75
+ * @lm_ctl:	CTL Path HW driver context
76
+ * @lm_dspp:	DSPP HW driver context
8877  * @mixer_op_mode:	mixer blending operation mode
8978  * @flush_mask:	mixer flush mask for ctl, mixer and pipe
9079  */
9180 struct dpu_crtc_mixer {
9281 	struct dpu_hw_mixer *hw_lm;
93
-	struct dpu_hw_ctl *hw_ctl;
94
-	struct drm_encoder *encoder;
82
+	struct dpu_hw_ctl *lm_ctl;
83
+	struct dpu_hw_dspp *hw_dspp;
9584 	u32 mixer_op_mode;
9685 	u32 flush_mask;
9786 };
....@@ -121,11 +110,6 @@
121110  * struct dpu_crtc - virtualized CRTC data structure
122111  * @base          : Base drm crtc structure
123112  * @name          : ASCII description of this crtc
124
- * @num_ctls      : Number of ctl paths in use
125
- * @num_mixers    : Number of mixers in use
126
- * @mixers_swapped: Whether the mixers have been swapped for left/right update
127
- *                  especially in the case of DSC Merge.
128
- * @mixers        : List of active mixers
129113  * @event         : Pointer to last received drm vblank event. If there is a
130114  *                  pending vblank event, this will be non-null.
131115  * @vsync_count   : Running count of received vsync events
....@@ -137,8 +121,6 @@
137121  * @vblank_cb_count : count of vblank callback since last reset
138122  * @play_count    : frame count between crtc enable and disable
139123  * @vblank_cb_time  : ktime at vblank count reset
140
- * @vblank_requested : whether the user has requested vblank events
141
- * @suspend         : whether or not a suspend operation is in progress
142124  * @enabled       : whether the DPU CRTC is currently enabled. updated in the
143125  *                  commit-thread, not state-swap time which is earlier, so
144126  *                  safe to make decisions on during VBLANK on/off work
....@@ -147,7 +129,6 @@
147129  * @dirty_list    : list of color processing features are dirty
148130  * @ad_dirty: list containing ad properties that are dirty
149131  * @ad_active: list containing ad properties that are active
150
- * @crtc_lock     : crtc lock around create, destroy and access.
151132  * @frame_pending : Whether or not an update is pending
152133  * @frame_events  : static allocation of in-flight frame events
153134  * @frame_event_list : available frame event list
....@@ -156,26 +137,12 @@
156137  * @event_thread  : Pointer to event handler thread
157138  * @event_worker  : Event worker queue
158139  * @event_lock    : Spinlock around event handling code
159
- * @misr_enable   : boolean entry indicates misr enable/disable status.
160
- * @misr_frame_count  : misr frame count provided by client
161
- * @misr_data     : store misr data before turning off the clocks.
162140  * @phandle: Pointer to power handler
163
- * @power_event   : registered power event handle
164141  * @cur_perf      : current performance committed to clock/bandwidth driver
165
- * @rp_lock       : serialization lock for resource pool
166
- * @rp_head       : list of active resource pool
167
- * @scl3_cfg_lut  : qseed3 lut config
168142  */
169143 struct dpu_crtc {
170144 	struct drm_crtc base;
171145 	char name[DPU_CRTC_NAME_SIZE];
172
-
173
-	/* HW Resources reserved for the crtc */
174
-	u32 num_ctls;
175
-	u32 num_mixers;
176
-	bool mixers_swapped;
177
-	struct dpu_crtc_mixer mixers[CRTC_DUAL_MIXERS];
178
-	struct dpu_hw_scaler3_lut_cfg *scl3_lut_cfg;
179146 
180147 	struct drm_pending_vblank_event *event;
181148 	u32 vsync_count;
....@@ -186,8 +153,6 @@
186153 	u32 vblank_cb_count;
187154 	u64 play_count;
188155 	ktime_t vblank_cb_time;
189
-	bool vblank_requested;
190
-	bool suspend;
191156 	bool enabled;
192157 
193158 	struct list_head feature_list;
....@@ -195,8 +160,6 @@
195160 	struct list_head dirty_list;
196161 	struct list_head ad_dirty;
197162 	struct list_head ad_active;
198
-
199
-	struct mutex crtc_lock;
200163 
201164 	atomic_t frame_pending;
202165 	struct dpu_crtc_frame_event frame_events[DPU_CRTC_FRAME_EVENT_SIZE];
....@@ -206,17 +169,8 @@
206169 
207170 	/* for handling internal event thread */
208171 	spinlock_t event_lock;
209
-	bool misr_enable;
210
-	u32 misr_frame_count;
211
-	u32 misr_data[CRTC_DUAL_MIXERS];
212
-
213
-	struct dpu_power_handle *phandle;
214
-	struct dpu_power_event *power_event;
215172 
216173 	struct dpu_core_perf_params cur_perf;
217
-
218
-	struct mutex rp_lock;
219
-	struct list_head rp_head;
220174 
221175 	struct dpu_crtc_smmu_state_data smmu_state;
222176 };
....@@ -224,59 +178,8 @@
224178 #define to_dpu_crtc(x) container_of(x, struct dpu_crtc, base)
225179 
226180 /**
227
- * struct dpu_crtc_res_ops - common operations for crtc resources
228
- * @get: get given resource
229
- * @put: put given resource
230
- */
231
-struct dpu_crtc_res_ops {
232
-	void *(*get)(void *val, u32 type, u64 tag);
233
-	void (*put)(void *val);
234
-};
235
-
236
-#define DPU_CRTC_RES_FLAG_FREE		BIT(0)
237
-
238
-/**
239
- * struct dpu_crtc_res - definition of crtc resources
240
- * @list: list of crtc resource
241
- * @type: crtc resource type
242
- * @tag: unique identifier per type
243
- * @refcount: reference/usage count
244
- * @ops: callback operations
245
- * @val: resource handle associated with type/tag
246
- * @flags: customization flags
247
- */
248
-struct dpu_crtc_res {
249
-	struct list_head list;
250
-	u32 type;
251
-	u64 tag;
252
-	atomic_t refcount;
253
-	struct dpu_crtc_res_ops ops;
254
-	void *val;
255
-	u32 flags;
256
-};
257
-
258
-/**
259
- * dpu_crtc_respool - crtc resource pool
260
- * @rp_lock: pointer to serialization lock
261
- * @rp_head: pointer to head of active resource pools of this crtc
262
- * @rp_list: list of crtc resource pool
263
- * @sequence_id: sequence identifier, incremented per state duplication
264
- * @res_list: list of resource managed by this resource pool
265
- * @ops: resource operations for parent resource pool
266
- */
267
-struct dpu_crtc_respool {
268
-	struct mutex *rp_lock;
269
-	struct list_head *rp_head;
270
-	struct list_head rp_list;
271
-	u32 sequence_id;
272
-	struct list_head res_list;
273
-	struct dpu_crtc_res_ops ops;
274
-};
275
-
276
-/**
277181  * struct dpu_crtc_state - dpu container for atomic crtc state
278182  * @base: Base drm crtc state structure
279
- * @is_ppsplit    : Whether current topology requires PPSplit special handling
280183  * @bw_control    : true if bw/clk controlled by core bw/clk properties
281184  * @bw_split_vote : true if bw controlled by llcc/dram bw properties
282185  * @lm_bounds     : LM boundaries based on current mode full resolution, no ROI.
....@@ -285,55 +188,32 @@
285188  * @property_values: Current crtc property values
286189  * @input_fence_timeout_ns : Cached input fence timeout, in ns
287190  * @new_perf: new performance state being requested
191
+ * @num_mixers    : Number of mixers in use
192
+ * @mixers        : List of active mixers
193
+ * @num_ctls      : Number of ctl paths in use
194
+ * @hw_ctls       : List of active ctl paths
288195  */
289196 struct dpu_crtc_state {
290197 	struct drm_crtc_state base;
291198 
292199 	bool bw_control;
293200 	bool bw_split_vote;
294
-
295
-	bool is_ppsplit;
296201 	struct drm_rect lm_bounds[CRTC_DUAL_MIXERS];
297202 
298203 	uint64_t input_fence_timeout_ns;
299204 
300205 	struct dpu_core_perf_params new_perf;
301
-	struct dpu_crtc_respool rp;
206
+
207
+	/* HW Resources reserved for the crtc */
208
+	u32 num_mixers;
209
+	struct dpu_crtc_mixer mixers[CRTC_DUAL_MIXERS];
210
+
211
+	u32 num_ctls;
212
+	struct dpu_hw_ctl *hw_ctls[CRTC_DUAL_MIXERS];
302213 };
303214 
304215 #define to_dpu_crtc_state(x) \
305216 	container_of(x, struct dpu_crtc_state, base)
306
-
307
-/**
308
- * dpu_crtc_get_mixer_width - get the mixer width
309
- * Mixer width will be same as panel width(/2 for split)
310
- */
311
-static inline int dpu_crtc_get_mixer_width(struct dpu_crtc *dpu_crtc,
312
-	struct dpu_crtc_state *cstate, struct drm_display_mode *mode)
313
-{
314
-	u32 mixer_width;
315
-
316
-	if (!dpu_crtc || !cstate || !mode)
317
-		return 0;
318
-
319
-	mixer_width = (dpu_crtc->num_mixers == CRTC_DUAL_MIXERS ?
320
-			mode->hdisplay / CRTC_DUAL_MIXERS : mode->hdisplay);
321
-
322
-	return mixer_width;
323
-}
324
-
325
-/**
326
- * dpu_crtc_get_mixer_height - get the mixer height
327
- * Mixer height will be same as panel height
328
- */
329
-static inline int dpu_crtc_get_mixer_height(struct dpu_crtc *dpu_crtc,
330
-		struct dpu_crtc_state *cstate, struct drm_display_mode *mode)
331
-{
332
-	if (!dpu_crtc || !cstate || !mode)
333
-		return 0;
334
-
335
-	return mode->vdisplay;
336
-}
337217 
338218 /**
339219  * dpu_crtc_frame_pending - retun the number of pending frames
....@@ -341,13 +221,7 @@
341221  */
342222 static inline int dpu_crtc_frame_pending(struct drm_crtc *crtc)
343223 {
344
-	struct dpu_crtc *dpu_crtc;
345
-
346
-	if (!crtc)
347
-		return -EINVAL;
348
-
349
-	dpu_crtc = to_dpu_crtc(crtc);
350
-	return atomic_read(&dpu_crtc->frame_pending);
224
+	return crtc ? atomic_read(&to_dpu_crtc(crtc)->frame_pending) : -EINVAL;
351225 }
352226 
353227 /**
....@@ -358,6 +232,12 @@
358232 int dpu_crtc_vblank(struct drm_crtc *crtc, bool en);
359233 
360234 /**
235
+ * dpu_crtc_vblank_callback - called on vblank irq, issues completion events
236
+ * @crtc: Pointer to drm crtc object
237
+ */
238
+void dpu_crtc_vblank_callback(struct drm_crtc *crtc);
239
+
240
+/**
361241  * dpu_crtc_commit_kickoff - trigger kickoff of the commit for this crtc
362242  * @crtc: Pointer to drm crtc object
363243  */
....@@ -366,18 +246,18 @@
366246 /**
367247  * dpu_crtc_complete_commit - callback signalling completion of current commit
368248  * @crtc: Pointer to drm crtc object
369
- * @old_state: Pointer to drm crtc old state object
370249  */
371
-void dpu_crtc_complete_commit(struct drm_crtc *crtc,
372
-		struct drm_crtc_state *old_state);
250
+void dpu_crtc_complete_commit(struct drm_crtc *crtc);
373251 
374252 /**
375253  * dpu_crtc_init - create a new crtc object
376254  * @dev: dpu device
377255  * @plane: base plane
256
+ * @cursor: cursor plane
378257  * @Return: new crtc object or error
379258  */
380
-struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane);
259
+struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane,
260
+			       struct drm_plane *cursor);
381261 
382262 /**
383263  * dpu_crtc_register_custom_event - api for enabling/disabling crtc event
....@@ -402,22 +282,7 @@
402282 static inline enum dpu_crtc_client_type dpu_crtc_get_client_type(
403283 						struct drm_crtc *crtc)
404284 {
405
-	struct dpu_crtc_state *cstate =
406
-			crtc ? to_dpu_crtc_state(crtc->state) : NULL;
407
-
408
-	if (!cstate)
409
-		return NRT_CLIENT;
410
-
411
-	return RT_CLIENT;
412
-}
413
-
414
-/**
415
- * dpu_crtc_is_enabled - check if dpu crtc is enabled or not
416
- * @crtc: Pointer to crtc
417
- */
418
-static inline bool dpu_crtc_is_enabled(struct drm_crtc *crtc)
419
-{
420
-	return crtc ? crtc->enabled : false;
285
+	return crtc && crtc->state ? RT_CLIENT : NRT_CLIENT;
421286 }
422287 
423288 #endif /* _DPU_CRTC_H_ */