add ax88772_rst

hc

2024-05-10 9999e48639b3cecb08ffb37358bcba3b48161b29

 kernel/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
..
..
@@ -1,5 +1,6 @@
1
1
 /*
2
2
  * Copyright 2017 Advanced Micro Devices, Inc.
3
+ * Copyright 2019 Raptor Engineering, LLC
3
4
  *
4
5
  * Permission is hereby granted, free of charge, to any person obtaining a
5
6
  * copy of this software and associated documentation files (the "Software"),
..
..
@@ -24,19 +25,26 @@
24
25
  */
25
26
 
26
27
 #include "dm_services.h"
28
+#include "dc.h"
27
29
 #include "dcn_calcs.h"
28
30
 #include "dcn_calc_auto.h"
29
-#include "dc.h"
30
31
 #include "dal_asic_id.h"
31
-
32
32
 #include "resource.h"
33
33
 #include "dcn10/dcn10_resource.h"
34
34
 #include "dcn10/dcn10_hubbub.h"
35
+#include "dml/dml1_display_rq_dlg_calc.h"
35
36
 
36
37
 #include "dcn_calc_math.h"
37
38
 
38
39
 #define DC_LOGGER \
39
40
 	dc->ctx->logger
41
+
42
+#define WM_SET_COUNT 4
43
+#define WM_A 0
44
+#define WM_B 1
45
+#define WM_C 2
46
+#define WM_D 3
47
+
40
48
 /*
41
49
  * NOTE:
42
50
  *   This file is gcc-parseable HW gospel, coming straight from HW engineers.
..
..
@@ -46,7 +54,9 @@
46
54
  * remain as-is as it provides us with a guarantee from HW that it is correct.
47
55
  */
48
56
 
49
-/* Defaults from spreadsheet rev#247 */
57
+/* Defaults from spreadsheet rev#247.
58
+ * RV2 delta: dram_clock_change_latency, max_num_dpp
59
+ */
50
60
 const struct dcn_soc_bounding_box dcn10_soc_defaults = {
51
61
 		/* latencies */
52
62
 		.sr_exit_time = 17, /*us*/
..
..
@@ -240,15 +250,69 @@
240
250
 	}
241
251
 }
242
252
 
253
+enum source_macro_tile_size swizzle_mode_to_macro_tile_size(enum swizzle_mode_values sw_mode)
254
+{
255
+	switch (sw_mode) {
256
+	/* for 4/8/16 high tiles */
257
+	case DC_SW_LINEAR:
258
+		return dm_4k_tile;
259
+	case DC_SW_4KB_S:
260
+	case DC_SW_4KB_S_X:
261
+		return dm_4k_tile;
262
+	case DC_SW_64KB_S:
263
+	case DC_SW_64KB_S_X:
264
+	case DC_SW_64KB_S_T:
265
+		return dm_64k_tile;
266
+	case DC_SW_VAR_S:
267
+	case DC_SW_VAR_S_X:
268
+		return dm_256k_tile;
269
+
270
+	/* For 64bpp 2 high tiles */
271
+	case DC_SW_4KB_D:
272
+	case DC_SW_4KB_D_X:
273
+		return dm_4k_tile;
274
+	case DC_SW_64KB_D:
275
+	case DC_SW_64KB_D_X:
276
+	case DC_SW_64KB_D_T:
277
+		return dm_64k_tile;
278
+	case DC_SW_VAR_D:
279
+	case DC_SW_VAR_D_X:
280
+		return dm_256k_tile;
281
+
282
+	case DC_SW_4KB_R:
283
+	case DC_SW_4KB_R_X:
284
+		return dm_4k_tile;
285
+	case DC_SW_64KB_R:
286
+	case DC_SW_64KB_R_X:
287
+		return dm_64k_tile;
288
+	case DC_SW_VAR_R:
289
+	case DC_SW_VAR_R_X:
290
+		return dm_256k_tile;
291
+
292
+	/* Unsupported swizzle modes for dcn */
293
+	case DC_SW_256B_S:
294
+	default:
295
+		ASSERT(0); /* Not supported */
296
+		return 0;
297
+	}
298
+}
299
+
243
300
 static void pipe_ctx_to_e2e_pipe_params (
244
301
 		const struct pipe_ctx *pipe,
245
302
 		struct _vcs_dpi_display_pipe_params_st *input)
246
303
 {
247
304
 	input->src.is_hsplit = false;
248
-	if (pipe->top_pipe != NULL && pipe->top_pipe->plane_state == pipe->plane_state)
305
+
306
+	/* stereo can never be split */
307
+	if (pipe->plane_state->stereo_format == PLANE_STEREO_FORMAT_SIDE_BY_SIDE ||
308
+	    pipe->plane_state->stereo_format == PLANE_STEREO_FORMAT_TOP_AND_BOTTOM) {
309
+		/* reset the split group if it was already considered split. */
310
+		input->src.hsplit_grp = pipe->pipe_idx;
311
+	} else if (pipe->top_pipe != NULL && pipe->top_pipe->plane_state == pipe->plane_state) {
249
312
 		input->src.is_hsplit = true;
250
-	else if (pipe->bottom_pipe != NULL && pipe->bottom_pipe->plane_state == pipe->plane_state)
313
+	} else if (pipe->bottom_pipe != NULL && pipe->bottom_pipe->plane_state == pipe->plane_state) {
251
314
 		input->src.is_hsplit = true;
315
+	}
252
316
 
253
317
 	if (pipe->plane_res.dpp->ctx->dc->debug.optimized_watermark) {
254
318
 		/*
..
..
@@ -269,7 +333,7 @@
269
333
 			dcc_support_pixel_format(pipe->plane_state->format, &bpe) ? 1 : 0;
270
334
 	}
271
335
 	input->src.dcc_rate            = 1;
272
-	input->src.meta_pitch          = pipe->plane_state->dcc.grph.meta_pitch;
336
+	input->src.meta_pitch          = pipe->plane_state->dcc.meta_pitch;
273
337
 	input->src.source_scan         = dm_horz;
274
338
 	input->src.sw_mode             = pipe->plane_state->tiling_info.gfx9.swizzle;
275
339
 
..
..
@@ -280,53 +344,7 @@
280
344
 	input->src.cur0_src_width      = 128; /* TODO: Cursor calcs, not curently stored */
281
345
 	input->src.cur0_bpp            = 32;
282
346
 
283
-	switch (pipe->plane_state->tiling_info.gfx9.swizzle) {
284
-	/* for 4/8/16 high tiles */
285
-	case DC_SW_LINEAR:
286
-		input->src.is_display_sw = 1;
287
-		input->src.macro_tile_size = dm_4k_tile;
288
-		break;
289
-	case DC_SW_4KB_S:
290
-	case DC_SW_4KB_S_X:
291
-		input->src.is_display_sw = 0;
292
-		input->src.macro_tile_size = dm_4k_tile;
293
-		break;
294
-	case DC_SW_64KB_S:
295
-	case DC_SW_64KB_S_X:
296
-	case DC_SW_64KB_S_T:
297
-		input->src.is_display_sw = 0;
298
-		input->src.macro_tile_size = dm_64k_tile;
299
-		break;
300
-	case DC_SW_VAR_S:
301
-	case DC_SW_VAR_S_X:
302
-		input->src.is_display_sw = 0;
303
-		input->src.macro_tile_size = dm_256k_tile;
304
-		break;
305
-
306
-	/* For 64bpp 2 high tiles */
307
-	case DC_SW_4KB_D:
308
-	case DC_SW_4KB_D_X:
309
-		input->src.is_display_sw = 1;
310
-		input->src.macro_tile_size = dm_4k_tile;
311
-		break;
312
-	case DC_SW_64KB_D:
313
-	case DC_SW_64KB_D_X:
314
-	case DC_SW_64KB_D_T:
315
-		input->src.is_display_sw = 1;
316
-		input->src.macro_tile_size = dm_64k_tile;
317
-		break;
318
-	case DC_SW_VAR_D:
319
-	case DC_SW_VAR_D_X:
320
-		input->src.is_display_sw = 1;
321
-		input->src.macro_tile_size = dm_256k_tile;
322
-		break;
323
-
324
-	/* Unsupported swizzle modes for dcn */
325
-	case DC_SW_256B_S:
326
-	default:
327
-		ASSERT(0); /* Not supported */
328
-		break;
329
-	}
347
+	input->src.macro_tile_size = swizzle_mode_to_macro_tile_size(pipe->plane_state->tiling_info.gfx9.swizzle);
330
348
 
331
349
 	switch (pipe->plane_state->rotation) {
332
350
 	case ROTATION_ANGLE_0:
..
..
@@ -363,6 +381,13 @@
363
381
 		input->src.viewport_width_c    = input->src.viewport_width;
364
382
 		input->src.viewport_height_c   = input->src.viewport_height;
365
383
 		break;
384
+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
385
+	case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:
386
+		input->src.source_format = dm_rgbe_alpha;
387
+		input->src.viewport_width_c    = input->src.viewport_width;
388
+		input->src.viewport_height_c   = input->src.viewport_height;
389
+		break;
390
+#endif
366
391
 	default:
367
392
 		input->src.source_format = dm_444_32;
368
393
 		input->src.viewport_width_c    = input->src.viewport_width;
..
..
@@ -416,7 +441,7 @@
416
441
 			- pipe->stream->timing.v_addressable
417
442
 			- pipe->stream->timing.v_border_bottom
418
443
 			- pipe->stream->timing.v_border_top;
419
-	input->dest.pixel_rate_mhz = pipe->stream->timing.pix_clk_khz/1000.0;
444
+	input->dest.pixel_rate_mhz = pipe->stream->timing.pix_clk_100hz/10000.0;
420
445
 	input->dest.vstartup_start = pipe->pipe_dlg_param.vstartup_start;
421
446
 	input->dest.vupdate_offset = pipe->pipe_dlg_param.vupdate_offset;
422
447
 	input->dest.vupdate_offset = pipe->pipe_dlg_param.vupdate_offset;
..
..
@@ -434,9 +459,9 @@
434
459
 	struct _vcs_dpi_display_dlg_regs_st *dlg_regs = &pipe->dlg_regs;
435
460
 	struct _vcs_dpi_display_ttu_regs_st *ttu_regs = &pipe->ttu_regs;
436
461
 	struct _vcs_dpi_display_rq_regs_st *rq_regs = &pipe->rq_regs;
437
-	struct _vcs_dpi_display_rq_params_st rq_param = {0};
438
-	struct _vcs_dpi_display_dlg_sys_params_st dlg_sys_param = {0};
439
-	struct _vcs_dpi_display_e2e_pipe_params_st input = { { { 0 } } };
462
+	struct _vcs_dpi_display_rq_params_st *rq_param = &pipe->dml_rq_param;
463
+	struct _vcs_dpi_display_dlg_sys_params_st *dlg_sys_param = &pipe->dml_dlg_sys_param;
464
+	struct _vcs_dpi_display_e2e_pipe_params_st *input = &pipe->dml_input;
440
465
 	float total_active_bw = 0;
441
466
 	float total_prefetch_bw = 0;
442
467
 	int total_flip_bytes = 0;
..
..
@@ -445,45 +470,48 @@
445
470
 	memset(dlg_regs, 0, sizeof(*dlg_regs));
446
471
 	memset(ttu_regs, 0, sizeof(*ttu_regs));
447
472
 	memset(rq_regs, 0, sizeof(*rq_regs));
473
+	memset(rq_param, 0, sizeof(*rq_param));
474
+	memset(dlg_sys_param, 0, sizeof(*dlg_sys_param));
475
+	memset(input, 0, sizeof(*input));
448
476
 
449
477
 	for (i = 0; i < number_of_planes; i++) {
450
478
 		total_active_bw += v->read_bandwidth[i];
451
479
 		total_prefetch_bw += v->prefetch_bandwidth[i];
452
480
 		total_flip_bytes += v->total_immediate_flip_bytes[i];
453
481
 	}
454
-	dlg_sys_param.total_flip_bw = v->return_bw - dcn_bw_max2(total_active_bw, total_prefetch_bw);
455
-	if (dlg_sys_param.total_flip_bw < 0.0)
456
-		dlg_sys_param.total_flip_bw = 0;
482
+	dlg_sys_param->total_flip_bw = v->return_bw - dcn_bw_max2(total_active_bw, total_prefetch_bw);
483
+	if (dlg_sys_param->total_flip_bw < 0.0)
484
+		dlg_sys_param->total_flip_bw = 0;
457
485
 
458
-	dlg_sys_param.t_mclk_wm_us = v->dram_clock_change_watermark;
459
-	dlg_sys_param.t_sr_wm_us = v->stutter_enter_plus_exit_watermark;
460
-	dlg_sys_param.t_urg_wm_us = v->urgent_watermark;
461
-	dlg_sys_param.t_extra_us = v->urgent_extra_latency;
462
-	dlg_sys_param.deepsleep_dcfclk_mhz = v->dcf_clk_deep_sleep;
463
-	dlg_sys_param.total_flip_bytes = total_flip_bytes;
486
+	dlg_sys_param->t_mclk_wm_us = v->dram_clock_change_watermark;
487
+	dlg_sys_param->t_sr_wm_us = v->stutter_enter_plus_exit_watermark;
488
+	dlg_sys_param->t_urg_wm_us = v->urgent_watermark;
489
+	dlg_sys_param->t_extra_us = v->urgent_extra_latency;
490
+	dlg_sys_param->deepsleep_dcfclk_mhz = v->dcf_clk_deep_sleep;
491
+	dlg_sys_param->total_flip_bytes = total_flip_bytes;
464
492
 
465
-	pipe_ctx_to_e2e_pipe_params(pipe, &input.pipe);
466
-	input.clks_cfg.dcfclk_mhz = v->dcfclk;
467
-	input.clks_cfg.dispclk_mhz = v->dispclk;
468
-	input.clks_cfg.dppclk_mhz = v->dppclk;
469
-	input.clks_cfg.refclk_mhz = dc->res_pool->ref_clock_inKhz / 1000.0;
470
-	input.clks_cfg.socclk_mhz = v->socclk;
471
-	input.clks_cfg.voltage = v->voltage_level;
493
+	pipe_ctx_to_e2e_pipe_params(pipe, &input->pipe);
494
+	input->clks_cfg.dcfclk_mhz = v->dcfclk;
495
+	input->clks_cfg.dispclk_mhz = v->dispclk;
496
+	input->clks_cfg.dppclk_mhz = v->dppclk;
497
+	input->clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
498
+	input->clks_cfg.socclk_mhz = v->socclk;
499
+	input->clks_cfg.voltage = v->voltage_level;
472
500
 //	dc->dml.logger = pool->base.logger;
473
-	input.dout.output_format = (v->output_format[in_idx] == dcn_bw_420) ? dm_420 : dm_444;
474
-	input.dout.output_type  = (v->output[in_idx] == dcn_bw_hdmi) ? dm_hdmi : dm_dp;
501
+	input->dout.output_format = (v->output_format[in_idx] == dcn_bw_420) ? dm_420 : dm_444;
502
+	input->dout.output_type  = (v->output[in_idx] == dcn_bw_hdmi) ? dm_hdmi : dm_dp;
475
503
 	//input[in_idx].dout.output_standard;
476
504
 
477
505
 	/*todo: soc->sr_enter_plus_exit_time??*/
478
-	dlg_sys_param.t_srx_delay_us = dc->dcn_ip->dcfclk_cstate_latency / v->dcf_clk_deep_sleep;
506
+	dlg_sys_param->t_srx_delay_us = dc->dcn_ip->dcfclk_cstate_latency / v->dcf_clk_deep_sleep;
479
507
 
480
-	dml1_rq_dlg_get_rq_params(dml, &rq_param, input.pipe.src);
508
+	dml1_rq_dlg_get_rq_params(dml, rq_param, input.pipe.src);
481
509
 	dml1_extract_rq_regs(dml, rq_regs, rq_param);
482
510
 	dml1_rq_dlg_get_dlg_params(
483
511
 			dml,
484
512
 			dlg_regs,
485
513
 			ttu_regs,
486
-			rq_param.dlg,
514
+			rq_param->dlg,
487
515
 			dlg_sys_param,
488
516
 			input,
489
517
 			true,
..
..
@@ -536,28 +564,28 @@
536
564
 		v->fabric_and_dram_bandwidth = v->fabric_and_dram_bandwidth_vnom0p8;
537
565
 		dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v);
538
566
 
539
-		context->bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns =
567
+		context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns =
540
568
 			v->stutter_exit_watermark * 1000;
541
-		context->bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns =
569
+		context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns =
542
570
 				v->stutter_enter_plus_exit_watermark * 1000;
543
-		context->bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns =
571
+		context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns =
544
572
 				v->dram_clock_change_watermark * 1000;
545
-		context->bw.dcn.watermarks.b.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
546
-		context->bw.dcn.watermarks.b.urgent_ns = v->urgent_watermark * 1000;
573
+		context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
574
+		context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = v->urgent_watermark * 1000;
547
575
 
548
576
 		v->dcfclk_per_state[1] = v->dcfclkv_nom0p8;
549
577
 		v->dcfclk_per_state[0] = v->dcfclkv_nom0p8;
550
578
 		v->dcfclk = v->dcfclkv_nom0p8;
551
579
 		dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v);
552
580
 
553
-		context->bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns =
581
+		context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns =
554
582
 			v->stutter_exit_watermark * 1000;
555
-		context->bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns =
583
+		context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns =
556
584
 				v->stutter_enter_plus_exit_watermark * 1000;
557
-		context->bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns =
585
+		context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns =
558
586
 				v->dram_clock_change_watermark * 1000;
559
-		context->bw.dcn.watermarks.c.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
560
-		context->bw.dcn.watermarks.c.urgent_ns = v->urgent_watermark * 1000;
587
+		context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
588
+		context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = v->urgent_watermark * 1000;
561
589
 	}
562
590
 
563
591
 	if (v->voltage_level < 3) {
..
..
@@ -571,14 +599,14 @@
571
599
 		v->dcfclk = v->dcfclkv_max0p9;
572
600
 		dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v);
573
601
 
574
-		context->bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns =
602
+		context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns =
575
603
 			v->stutter_exit_watermark * 1000;
576
-		context->bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns =
604
+		context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns =
577
605
 				v->stutter_enter_plus_exit_watermark * 1000;
578
-		context->bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns =
606
+		context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns =
579
607
 				v->dram_clock_change_watermark * 1000;
580
-		context->bw.dcn.watermarks.d.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
581
-		context->bw.dcn.watermarks.d.urgent_ns = v->urgent_watermark * 1000;
608
+		context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
609
+		context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = v->urgent_watermark * 1000;
582
610
 	}
583
611
 
584
612
 	v->fabric_and_dram_bandwidth_per_state[2] = v->fabric_and_dram_bandwidth_vnom0p8;
..
..
@@ -591,20 +619,20 @@
591
619
 	v->dcfclk = v->dcfclk_per_state[v->voltage_level];
592
620
 	dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v);
593
621
 
594
-	context->bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns =
622
+	context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns =
595
623
 		v->stutter_exit_watermark * 1000;
596
-	context->bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns =
624
+	context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns =
597
625
 			v->stutter_enter_plus_exit_watermark * 1000;
598
-	context->bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns =
626
+	context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns =
599
627
 			v->dram_clock_change_watermark * 1000;
600
-	context->bw.dcn.watermarks.a.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
601
-	context->bw.dcn.watermarks.a.urgent_ns = v->urgent_watermark * 1000;
628
+	context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
629
+	context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = v->urgent_watermark * 1000;
602
630
 	if (v->voltage_level >= 2) {
603
-		context->bw.dcn.watermarks.b = context->bw.dcn.watermarks.a;
604
-		context->bw.dcn.watermarks.c = context->bw.dcn.watermarks.a;
631
+		context->bw_ctx.bw.dcn.watermarks.b = context->bw_ctx.bw.dcn.watermarks.a;
632
+		context->bw_ctx.bw.dcn.watermarks.c = context->bw_ctx.bw.dcn.watermarks.a;
605
633
 	}
606
634
 	if (v->voltage_level >= 3)
607
-		context->bw.dcn.watermarks.d = context->bw.dcn.watermarks.a;
635
+		context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a;
608
636
 }
609
637
 #endif
610
638
 
..
..
@@ -612,7 +640,7 @@
612
640
 {
613
641
 	bool updated = false;
614
642
 
615
-	kernel_fpu_begin();
643
+	DC_FP_START();
616
644
 	if ((int)(dc->dcn_soc->sr_exit_time * 1000) != dc->debug.sr_exit_time_ns
617
645
 			&& dc->debug.sr_exit_time_ns) {
618
646
 		updated = true;
..
..
@@ -648,7 +676,7 @@
648
676
 		dc->dcn_soc->dram_clock_change_latency =
649
677
 				dc->debug.dram_clock_change_latency_ns / 1000.0;
650
678
 	}
651
-	kernel_fpu_end();
679
+	DC_FP_END();
652
680
 
653
681
 	return updated;
654
682
 }
..
..
@@ -663,9 +691,9 @@
663
691
 }
664
692
 
665
693
 static void hack_force_pipe_split(struct dcn_bw_internal_vars *v,
666
-		unsigned int pixel_rate_khz)
694
+		unsigned int pixel_rate_100hz)
667
695
 {
668
-	float pixel_rate_mhz = pixel_rate_khz / 1000;
696
+	float pixel_rate_mhz = pixel_rate_100hz / 10000;
669
697
 
670
698
 	/*
671
699
 	 * force enabling pipe split by lower dpp clock for DPM0 to just
..
..
@@ -679,6 +707,26 @@
679
707
 		struct dc_debug_options *dbg,
680
708
 		struct dc_state *context)
681
709
 {
710
+	int i;
711
+
712
+	for (i = 0; i < MAX_PIPES; i++) {
713
+		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
714
+
715
+		/**
716
+		 * Workaround for avoiding pipe-split in cases where we'd split
717
+		 * planes that are too small, resulting in splits that aren't
718
+		 * valid for the scaler.
719
+		 */
720
+		if (pipe->plane_state &&
721
+		    (pipe->plane_state->dst_rect.width <= 16 ||
722
+		     pipe->plane_state->dst_rect.height <= 16 ||
723
+		     pipe->plane_state->src_rect.width <= 16 ||
724
+		     pipe->plane_state->src_rect.height <= 16)) {
725
+			hack_disable_optional_pipe_split(v);
726
+			return;
727
+		}
728
+	}
729
+
682
730
 	if (dbg->pipe_split_policy == MPC_SPLIT_AVOID)
683
731
 		hack_disable_optional_pipe_split(v);
684
732
 
..
..
@@ -688,26 +736,60 @@
688
736
 
689
737
 	if (context->stream_count == 1 &&
690
738
 			dbg->force_single_disp_pipe_split)
691
-		hack_force_pipe_split(v, context->streams[0]->timing.pix_clk_khz);
739
+		hack_force_pipe_split(v, context->streams[0]->timing.pix_clk_100hz);
740
+}
741
+
742
+unsigned int get_highest_allowed_voltage_level(uint32_t hw_internal_rev, uint32_t pci_revision_id)
743
+{
744
+	/* for low power RV2 variants, the highest voltage level we want is 0 */
745
+	if (ASICREV_IS_RAVEN2(hw_internal_rev))
746
+		switch (pci_revision_id) {
747
+		case PRID_DALI_DE:
748
+		case PRID_DALI_DF:
749
+		case PRID_DALI_E3:
750
+		case PRID_DALI_E4:
751
+		case PRID_POLLOCK_94:
752
+		case PRID_POLLOCK_95:
753
+		case PRID_POLLOCK_E9:
754
+		case PRID_POLLOCK_EA:
755
+		case PRID_POLLOCK_EB:
756
+			return 0;
757
+		default:
758
+			break;
759
+		}
760
+
761
+	/* we are ok with all levels */
762
+	return 4;
692
763
 }
693
764
 
694
765
 bool dcn_validate_bandwidth(
695
766
 		struct dc *dc,
696
-		struct dc_state *context)
767
+		struct dc_state *context,
768
+		bool fast_validate)
697
769
 {
770
+	/*
771
+	 * we want a breakdown of the various stages of validation, which the
772
+	 * perf_trace macro doesn't support
773
+	 */
774
+	BW_VAL_TRACE_SETUP();
775
+
698
776
 	const struct resource_pool *pool = dc->res_pool;
699
777
 	struct dcn_bw_internal_vars *v = &context->dcn_bw_vars;
700
-	int i, input_idx;
778
+	int i, input_idx, k;
701
779
 	int vesa_sync_start, asic_blank_end, asic_blank_start;
702
780
 	bool bw_limit_pass;
703
781
 	float bw_limit;
704
782
 
705
783
 	PERFORMANCE_TRACE_START();
784
+
785
+	BW_VAL_TRACE_COUNT();
786
+
706
787
 	if (dcn_bw_apply_registry_override(dc))
707
788
 		dcn_bw_sync_calcs_and_dml(dc);
708
789
 
709
790
 	memset(v, 0, sizeof(*v));
710
-	kernel_fpu_begin();
791
+	DC_FP_START();
792
+
711
793
 	v->sr_exit_time = dc->dcn_soc->sr_exit_time;
712
794
 	v->sr_enter_plus_exit_time = dc->dcn_soc->sr_enter_plus_exit_time;
713
795
 	v->urgent_latency = dc->dcn_soc->urgent_latency;
..
..
@@ -845,8 +927,9 @@
845
927
 		v->v_sync_plus_back_porch[input_idx] = pipe->stream->timing.v_total
846
928
 				- v->vactive[input_idx]
847
929
 				- pipe->stream->timing.v_front_porch;
848
-		v->pixel_clock[input_idx] = pipe->stream->timing.pix_clk_khz / 1000.0f;
849
-
930
+		v->pixel_clock[input_idx] = pipe->stream->timing.pix_clk_100hz/10000.0;
931
+		if (pipe->stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
932
+			v->pixel_clock[input_idx] *= 2;
850
933
 		if (!pipe->plane_state) {
851
934
 			v->dcc_enable[input_idx] = dcn_bw_yes;
852
935
 			v->source_pixel_format[input_idx] = dcn_bw_rgb_sub_32;
..
..
@@ -854,8 +937,19 @@
854
937
 			v->lb_bit_per_pixel[input_idx] = 30;
855
938
 			v->viewport_width[input_idx] = pipe->stream->timing.h_addressable;
856
939
 			v->viewport_height[input_idx] = pipe->stream->timing.v_addressable;
857
-			v->scaler_rec_out_width[input_idx] = pipe->stream->timing.h_addressable;
858
-			v->scaler_recout_height[input_idx] = pipe->stream->timing.v_addressable;
940
+			/*
941
+			 * for cases where we have no plane, we want to validate up to 1080p
942
+			 * source size because here we are only interested in if the output
943
+			 * timing is supported or not. if we cannot support native resolution
944
+			 * of the high res display, we still want to support lower res up scale
945
+			 * to native
946
+			 */
947
+			if (v->viewport_width[input_idx] > 1920)
948
+				v->viewport_width[input_idx] = 1920;
949
+			if (v->viewport_height[input_idx] > 1080)
950
+				v->viewport_height[input_idx] = 1080;
951
+			v->scaler_rec_out_width[input_idx] = v->viewport_width[input_idx];
952
+			v->scaler_recout_height[input_idx] = v->viewport_height[input_idx];
859
953
 			v->override_hta_ps[input_idx] = 1;
860
954
 			v->override_vta_ps[input_idx] = 1;
861
955
 			v->override_hta_pschroma[input_idx] = 1;
..
..
@@ -953,7 +1047,7 @@
953
1047
 		v->dcc_rate[input_idx] = 1; /*TODO: Worst case? does this change?*/
954
1048
 		v->output_format[input_idx] = pipe->stream->timing.pixel_encoding ==
955
1049
 				PIXEL_ENCODING_YCBCR420 ? dcn_bw_420 : dcn_bw_444;
956
-		v->output[input_idx] = pipe->stream->sink->sink_signal ==
1050
+		v->output[input_idx] = pipe->stream->signal ==
957
1051
 				SIGNAL_TYPE_HDMI_TYPE_A ? dcn_bw_hdmi : dcn_bw_dp;
958
1052
 		v->output_deep_color[input_idx] = dcn_bw_encoder_8bpc;
959
1053
 		if (v->output[input_idx] == dcn_bw_hdmi) {
..
..
@@ -999,13 +1093,53 @@
999
1093
 				dc->debug.sr_enter_plus_exit_time_dpm0_ns / 1000.0f;
1000
1094
 		if (dc->debug.sr_exit_time_dpm0_ns)
1001
1095
 			v->sr_exit_time =  dc->debug.sr_exit_time_dpm0_ns / 1000.0f;
1002
-		dc->dml.soc.sr_enter_plus_exit_time_us = v->sr_enter_plus_exit_time;
1003
-		dc->dml.soc.sr_exit_time_us = v->sr_exit_time;
1096
+		context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = v->sr_enter_plus_exit_time;
1097
+		context->bw_ctx.dml.soc.sr_exit_time_us = v->sr_exit_time;
1004
1098
 		mode_support_and_system_configuration(v);
1005
1099
 	}
1006
1100
 
1007
-	if (v->voltage_level != 5) {
1101
+	display_pipe_configuration(v);
1102
+
1103
+	for (k = 0; k <= v->number_of_active_planes - 1; k++) {
1104
+		if (v->source_scan[k] == dcn_bw_hor)
1105
+			v->swath_width_y[k] = v->viewport_width[k] / v->dpp_per_plane[k];
1106
+		else
1107
+			v->swath_width_y[k] = v->viewport_height[k] / v->dpp_per_plane[k];
1108
+	}
1109
+	for (k = 0; k <= v->number_of_active_planes - 1; k++) {
1110
+		if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64) {
1111
+			v->byte_per_pixel_dety[k] = 8.0;
1112
+			v->byte_per_pixel_detc[k] = 0.0;
1113
+		} else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_32) {
1114
+			v->byte_per_pixel_dety[k] = 4.0;
1115
+			v->byte_per_pixel_detc[k] = 0.0;
1116
+		} else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_16) {
1117
+			v->byte_per_pixel_dety[k] = 2.0;
1118
+			v->byte_per_pixel_detc[k] = 0.0;
1119
+		} else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) {
1120
+			v->byte_per_pixel_dety[k] = 1.0;
1121
+			v->byte_per_pixel_detc[k] = 2.0;
1122
+		} else {
1123
+			v->byte_per_pixel_dety[k] = 4.0f / 3.0f;
1124
+			v->byte_per_pixel_detc[k] = 8.0f / 3.0f;
1125
+		}
1126
+	}
1127
+
1128
+	v->total_data_read_bandwidth = 0.0;
1129
+	for (k = 0; k <= v->number_of_active_planes - 1; k++) {
1130
+		v->read_bandwidth_plane_luma[k] = v->swath_width_y[k] * v->dpp_per_plane[k] *
1131
+				dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / (v->htotal[k] / v->pixel_clock[k]) * v->v_ratio[k];
1132
+		v->read_bandwidth_plane_chroma[k] = v->swath_width_y[k] / 2.0 * v->dpp_per_plane[k] *
1133
+				dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / (v->htotal[k] / v->pixel_clock[k]) * v->v_ratio[k] / 2.0;
1134
+		v->total_data_read_bandwidth = v->total_data_read_bandwidth +
1135
+				v->read_bandwidth_plane_luma[k] + v->read_bandwidth_plane_chroma[k];
1136
+	}
1137
+
1138
+	BW_VAL_TRACE_END_VOLTAGE_LEVEL();
1139
+
1140
+	if (v->voltage_level != number_of_states_plus_one && !fast_validate) {
1008
1141
 		float bw_consumed = v->total_bandwidth_consumed_gbyte_per_second;
1142
+
1009
1143
 		if (bw_consumed < v->fabric_and_dram_bandwidth_vmin0p65)
1010
1144
 			bw_consumed = v->fabric_and_dram_bandwidth_vmin0p65;
1011
1145
 		else if (bw_consumed < v->fabric_and_dram_bandwidth_vmid0p72)
..
..
@@ -1026,57 +1160,59 @@
1026
1160
 		 */
1027
1161
 		dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v);
1028
1162
 
1029
-		context->bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns =
1163
+		context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns =
1030
1164
 			v->stutter_exit_watermark * 1000;
1031
-		context->bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns =
1165
+		context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns =
1032
1166
 				v->stutter_enter_plus_exit_watermark * 1000;
1033
-		context->bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns =
1167
+		context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns =
1034
1168
 				v->dram_clock_change_watermark * 1000;
1035
-		context->bw.dcn.watermarks.a.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
1036
-		context->bw.dcn.watermarks.a.urgent_ns = v->urgent_watermark * 1000;
1037
-		context->bw.dcn.watermarks.b = context->bw.dcn.watermarks.a;
1038
-		context->bw.dcn.watermarks.c = context->bw.dcn.watermarks.a;
1039
-		context->bw.dcn.watermarks.d = context->bw.dcn.watermarks.a;
1169
+		context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
1170
+		context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = v->urgent_watermark * 1000;
1171
+		context->bw_ctx.bw.dcn.watermarks.b = context->bw_ctx.bw.dcn.watermarks.a;
1172
+		context->bw_ctx.bw.dcn.watermarks.c = context->bw_ctx.bw.dcn.watermarks.a;
1173
+		context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a;
1040
1174
 
1041
-		context->bw.dcn.clk.fclk_khz = (int)(bw_consumed * 1000000 /
1175
+		context->bw_ctx.bw.dcn.clk.fclk_khz = (int)(bw_consumed * 1000000 /
1042
1176
 				(ddr4_dram_factor_single_Channel * v->number_of_channels));
1043
-		if (bw_consumed == v->fabric_and_dram_bandwidth_vmin0p65) {
1044
-			context->bw.dcn.clk.fclk_khz = (int)(bw_consumed * 1000000 / 32);
1045
-		}
1177
+		if (bw_consumed == v->fabric_and_dram_bandwidth_vmin0p65)
1178
+			context->bw_ctx.bw.dcn.clk.fclk_khz = (int)(bw_consumed * 1000000 / 32);
1046
1179
 
1047
-		context->bw.dcn.clk.dcfclk_deep_sleep_khz = (int)(v->dcf_clk_deep_sleep * 1000);
1048
-		context->bw.dcn.clk.dcfclk_khz = (int)(v->dcfclk * 1000);
1180
+		context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = (int)(v->dcf_clk_deep_sleep * 1000);
1181
+		context->bw_ctx.bw.dcn.clk.dcfclk_khz = (int)(v->dcfclk * 1000);
1049
1182
 
1050
-		context->bw.dcn.clk.dispclk_khz = (int)(v->dispclk * 1000);
1183
+		context->bw_ctx.bw.dcn.clk.dispclk_khz = (int)(v->dispclk * 1000);
1051
1184
 		if (dc->debug.max_disp_clk == true)
1052
-			context->bw.dcn.clk.dispclk_khz = (int)(dc->dcn_soc->max_dispclk_vmax0p9 * 1000);
1185
+			context->bw_ctx.bw.dcn.clk.dispclk_khz = (int)(dc->dcn_soc->max_dispclk_vmax0p9 * 1000);
1053
1186
 
1054
-		if (context->bw.dcn.clk.dispclk_khz <
1187
+		if (context->bw_ctx.bw.dcn.clk.dispclk_khz <
1055
1188
 				dc->debug.min_disp_clk_khz) {
1056
-			context->bw.dcn.clk.dispclk_khz =
1189
+			context->bw_ctx.bw.dcn.clk.dispclk_khz =
1057
1190
 					dc->debug.min_disp_clk_khz;
1058
1191
 		}
1059
1192
 
1060
-		context->bw.dcn.clk.dppclk_khz = context->bw.dcn.clk.dispclk_khz / v->dispclk_dppclk_ratio;
1061
-		context->bw.dcn.clk.phyclk_khz = v->phyclk_per_state[v->voltage_level];
1193
+		context->bw_ctx.bw.dcn.clk.dppclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz /
1194
+				v->dispclk_dppclk_ratio;
1195
+		context->bw_ctx.bw.dcn.clk.phyclk_khz = v->phyclk_per_state[v->voltage_level];
1062
1196
 		switch (v->voltage_level) {
1063
1197
 		case 0:
1064
-			context->bw.dcn.clk.max_supported_dppclk_khz =
1198
+			context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz =
1065
1199
 					(int)(dc->dcn_soc->max_dppclk_vmin0p65 * 1000);
1066
1200
 			break;
1067
1201
 		case 1:
1068
-			context->bw.dcn.clk.max_supported_dppclk_khz =
1202
+			context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz =
1069
1203
 					(int)(dc->dcn_soc->max_dppclk_vmid0p72 * 1000);
1070
1204
 			break;
1071
1205
 		case 2:
1072
-			context->bw.dcn.clk.max_supported_dppclk_khz =
1206
+			context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz =
1073
1207
 					(int)(dc->dcn_soc->max_dppclk_vnom0p8 * 1000);
1074
1208
 			break;
1075
1209
 		default:
1076
-			context->bw.dcn.clk.max_supported_dppclk_khz =
1210
+			context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz =
1077
1211
 					(int)(dc->dcn_soc->max_dppclk_vmax0p9 * 1000);
1078
1212
 			break;
1079
1213
 		}
1214
+
1215
+		BW_VAL_TRACE_END_WATERMARKS();
1080
1216
 
1081
1217
 		for (i = 0, input_idx = 0; i < pool->pipe_count; i++) {
1082
1218
 			struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
..
..
@@ -1088,9 +1224,9 @@
1088
1224
 			if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state)
1089
1225
 				continue;
1090
1226
 
1091
-			pipe->pipe_dlg_param.vupdate_width = v->v_update_width[input_idx][v->dpp_per_plane[input_idx] == 2 ? 1 : 0];
1092
-			pipe->pipe_dlg_param.vupdate_offset = v->v_update_offset[input_idx][v->dpp_per_plane[input_idx] == 2 ? 1 : 0];
1093
-			pipe->pipe_dlg_param.vready_offset = v->v_ready_offset[input_idx][v->dpp_per_plane[input_idx] == 2 ? 1 : 0];
1227
+			pipe->pipe_dlg_param.vupdate_width = v->v_update_width_pix[input_idx];
1228
+			pipe->pipe_dlg_param.vupdate_offset = v->v_update_offset_pix[input_idx];
1229
+			pipe->pipe_dlg_param.vready_offset = v->v_ready_offset_pix[input_idx];
1094
1230
 			pipe->pipe_dlg_param.vstartup_start = v->v_startup[input_idx];
1095
1231
 
1096
1232
 			pipe->pipe_dlg_param.htotal = pipe->stream->timing.h_total;
..
..
@@ -1129,9 +1265,9 @@
1129
1265
 					 TIMING_3D_FORMAT_SIDE_BY_SIDE))) {
1130
1266
 					if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {
1131
1267
 						/* update previously split pipe */
1132
-						hsplit_pipe->pipe_dlg_param.vupdate_width = v->v_update_width[input_idx][v->dpp_per_plane[input_idx] == 2 ? 1 : 0];
1133
-						hsplit_pipe->pipe_dlg_param.vupdate_offset = v->v_update_offset[input_idx][v->dpp_per_plane[input_idx] == 2 ? 1 : 0];
1134
-						hsplit_pipe->pipe_dlg_param.vready_offset = v->v_ready_offset[input_idx][v->dpp_per_plane[input_idx] == 2 ? 1 : 0];
1268
+						hsplit_pipe->pipe_dlg_param.vupdate_width = v->v_update_width_pix[input_idx];
1269
+						hsplit_pipe->pipe_dlg_param.vupdate_offset = v->v_update_offset_pix[input_idx];
1270
+						hsplit_pipe->pipe_dlg_param.vready_offset = v->v_ready_offset_pix[input_idx];
1135
1271
 						hsplit_pipe->pipe_dlg_param.vstartup_start = v->v_startup[input_idx];
1136
1272
 
1137
1273
 						hsplit_pipe->pipe_dlg_param.htotal = pipe->stream->timing.h_total;
..
..
@@ -1140,11 +1276,9 @@
1140
1276
 						hsplit_pipe->pipe_dlg_param.vblank_end = pipe->pipe_dlg_param.vblank_end;
1141
1277
 					} else {
1142
1278
 						/* pipe not split previously needs split */
1143
-						hsplit_pipe = find_idle_secondary_pipe(&context->res_ctx, pool);
1279
+						hsplit_pipe = find_idle_secondary_pipe(&context->res_ctx, pool, pipe);
1144
1280
 						ASSERT(hsplit_pipe);
1145
-						split_stream_across_pipes(
1146
-							&context->res_ctx, pool,
1147
-							pipe, hsplit_pipe);
1281
+						split_stream_across_pipes(&context->res_ctx, pool, pipe, hsplit_pipe);
1148
1282
 					}
1149
1283
 
1150
1284
 					dcn_bw_calc_rq_dlg_ttu(dc, v, hsplit_pipe, input_idx);
..
..
@@ -1168,13 +1302,16 @@
1168
1302
 
1169
1303
 			input_idx++;
1170
1304
 		}
1305
+	} else if (v->voltage_level == number_of_states_plus_one) {
1306
+		BW_VAL_TRACE_SKIP(fail);
1307
+	} else if (fast_validate) {
1308
+		BW_VAL_TRACE_SKIP(fast);
1171
1309
 	}
1172
1310
 
1173
1311
 	if (v->voltage_level == 0) {
1174
-
1175
-		dc->dml.soc.sr_enter_plus_exit_time_us =
1312
+		context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us =
1176
1313
 				dc->dcn_soc->sr_enter_plus_exit_time;
1177
-		dc->dml.soc.sr_exit_time_us = dc->dcn_soc->sr_exit_time;
1314
+		context->bw_ctx.dml.soc.sr_exit_time_us = dc->dcn_soc->sr_exit_time;
1178
1315
 	}
1179
1316
 
1180
1317
 	/*
..
..
@@ -1184,11 +1321,14 @@
1184
1321
 	bw_limit = dc->dcn_soc->percent_disp_bw_limit * v->fabric_and_dram_bandwidth_vmax0p9;
1185
1322
 	bw_limit_pass = (v->total_data_read_bandwidth / 1000.0) < bw_limit;
1186
1323
 
1187
-	kernel_fpu_end();
1324
+	DC_FP_END();
1188
1325
 
1189
1326
 	PERFORMANCE_TRACE_END();
1327
+	BW_VAL_TRACE_FINISH();
1190
1328
 
1191
-	if (bw_limit_pass && v->voltage_level != 5)
1329
+	if (bw_limit_pass && v->voltage_level <= get_highest_allowed_voltage_level(
1330
+							dc->ctx->asic_id.hw_internal_rev,
1331
+							dc->ctx->asic_id.pci_revision_id))
1192
1332
 		return true;
1193
1333
 	else
1194
1334
 		return false;
..
..
@@ -1352,7 +1492,7 @@
1352
1492
 	res = dm_pp_get_clock_levels_by_type_with_voltage(
1353
1493
 			ctx, DM_PP_CLOCK_TYPE_FCLK, &fclks);
1354
1494
 
1355
-	kernel_fpu_begin();
1495
+	DC_FP_START();
1356
1496
 
1357
1497
 	if (res)
1358
1498
 		res = verify_clock_values(&fclks);
..
..
@@ -1383,12 +1523,12 @@
1383
1523
 	} else
1384
1524
 		BREAK_TO_DEBUGGER();
1385
1525
 
1386
-	kernel_fpu_end();
1526
+	DC_FP_END();
1387
1527
 
1388
1528
 	res = dm_pp_get_clock_levels_by_type_with_voltage(
1389
1529
 			ctx, DM_PP_CLOCK_TYPE_DCFCLK, &dcfclks);
1390
1530
 
1391
-	kernel_fpu_begin();
1531
+	DC_FP_START();
1392
1532
 
1393
1533
 	if (res)
1394
1534
 		res = verify_clock_values(&dcfclks);
..
..
@@ -1401,24 +1541,26 @@
1401
1541
 	} else
1402
1542
 		BREAK_TO_DEBUGGER();
1403
1543
 
1404
-	kernel_fpu_end();
1544
+	DC_FP_END();
1405
1545
 }
1406
1546
 
1407
1547
 void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc)
1408
1548
 {
1409
-	struct pp_smu_funcs_rv *pp = dc->res_pool->pp_smu;
1549
+	struct pp_smu_funcs_rv *pp = NULL;
1410
1550
 	struct pp_smu_wm_range_sets ranges = {0};
1411
1551
 	int min_fclk_khz, min_dcfclk_khz, socclk_khz;
1412
1552
 	const int overdrive = 5000000; /* 5 GHz to cover Overdrive */
1413
1553
 
1414
-	if (!pp->set_wm_ranges)
1554
+	if (dc->res_pool->pp_smu)
1555
+		pp = &dc->res_pool->pp_smu->rv_funcs;
1556
+	if (!pp || !pp->set_wm_ranges)
1415
1557
 		return;
1416
1558
 
1417
-	kernel_fpu_begin();
1559
+	DC_FP_START();
1418
1560
 	min_fclk_khz = dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 * 1000000 / 32;
1419
1561
 	min_dcfclk_khz = dc->dcn_soc->dcfclkv_min0p65 * 1000;
1420
1562
 	socclk_khz = dc->dcn_soc->socclk * 1000;
1421
-	kernel_fpu_end();
1563
+	DC_FP_END();
1422
1564
 
1423
1565
 	/* Now notify PPLib/SMU about which Watermarks sets they should select
1424
1566
 	 * depending on DPM state they are in. And update BW MGR GFX Engine and
..
..
@@ -1431,27 +1573,27 @@
1431
1573
 	ranges.num_reader_wm_sets = WM_SET_COUNT;
1432
1574
 	ranges.num_writer_wm_sets = WM_SET_COUNT;
1433
1575
 	ranges.reader_wm_sets[0].wm_inst = WM_A;
1434
-	ranges.reader_wm_sets[0].min_drain_clk_khz = min_dcfclk_khz;
1435
-	ranges.reader_wm_sets[0].max_drain_clk_khz = overdrive;
1436
-	ranges.reader_wm_sets[0].min_fill_clk_khz = min_fclk_khz;
1437
-	ranges.reader_wm_sets[0].max_fill_clk_khz = overdrive;
1576
+	ranges.reader_wm_sets[0].min_drain_clk_mhz = min_dcfclk_khz / 1000;
1577
+	ranges.reader_wm_sets[0].max_drain_clk_mhz = overdrive / 1000;
1578
+	ranges.reader_wm_sets[0].min_fill_clk_mhz = min_fclk_khz / 1000;
1579
+	ranges.reader_wm_sets[0].max_fill_clk_mhz = overdrive / 1000;
1438
1580
 	ranges.writer_wm_sets[0].wm_inst = WM_A;
1439
-	ranges.writer_wm_sets[0].min_fill_clk_khz = socclk_khz;
1440
-	ranges.writer_wm_sets[0].max_fill_clk_khz = overdrive;
1441
-	ranges.writer_wm_sets[0].min_drain_clk_khz = min_fclk_khz;
1442
-	ranges.writer_wm_sets[0].max_drain_clk_khz = overdrive;
1581
+	ranges.writer_wm_sets[0].min_fill_clk_mhz = socclk_khz / 1000;
1582
+	ranges.writer_wm_sets[0].max_fill_clk_mhz = overdrive / 1000;
1583
+	ranges.writer_wm_sets[0].min_drain_clk_mhz = min_fclk_khz / 1000;
1584
+	ranges.writer_wm_sets[0].max_drain_clk_mhz = overdrive / 1000;
1443
1585
 
1444
1586
 	if (dc->debug.pplib_wm_report_mode == WM_REPORT_OVERRIDE) {
1445
1587
 		ranges.reader_wm_sets[0].wm_inst = WM_A;
1446
-		ranges.reader_wm_sets[0].min_drain_clk_khz = 300000;
1447
-		ranges.reader_wm_sets[0].max_drain_clk_khz = 5000000;
1448
-		ranges.reader_wm_sets[0].min_fill_clk_khz = 800000;
1449
-		ranges.reader_wm_sets[0].max_fill_clk_khz = 5000000;
1588
+		ranges.reader_wm_sets[0].min_drain_clk_mhz = 300;
1589
+		ranges.reader_wm_sets[0].max_drain_clk_mhz = 5000;
1590
+		ranges.reader_wm_sets[0].min_fill_clk_mhz = 800;
1591
+		ranges.reader_wm_sets[0].max_fill_clk_mhz = 5000;
1450
1592
 		ranges.writer_wm_sets[0].wm_inst = WM_A;
1451
-		ranges.writer_wm_sets[0].min_fill_clk_khz = 200000;
1452
-		ranges.writer_wm_sets[0].max_fill_clk_khz = 5000000;
1453
-		ranges.writer_wm_sets[0].min_drain_clk_khz = 800000;
1454
-		ranges.writer_wm_sets[0].max_drain_clk_khz = 5000000;
1593
+		ranges.writer_wm_sets[0].min_fill_clk_mhz = 200;
1594
+		ranges.writer_wm_sets[0].max_fill_clk_mhz = 5000;
1595
+		ranges.writer_wm_sets[0].min_drain_clk_mhz = 800;
1596
+		ranges.writer_wm_sets[0].max_drain_clk_mhz = 5000;
1455
1597
 	}
1456
1598
 
1457
1599
 	ranges.reader_wm_sets[1] = ranges.writer_wm_sets[0];
..
..
@@ -1469,7 +1611,7 @@
1469
1611
 
1470
1612
 void dcn_bw_sync_calcs_and_dml(struct dc *dc)
1471
1613
 {
1472
-	kernel_fpu_begin();
1614
+	DC_FP_START();
1473
1615
 	DC_LOG_BANDWIDTH_CALCS("sr_exit_time: %f ns\n"
1474
1616
 			"sr_enter_plus_exit_time: %f ns\n"
1475
1617
 			"urgent_latency: %f ns\n"
..
..
@@ -1658,5 +1800,5 @@
1658
1800
 	dc->dml.ip.bug_forcing_LC_req_same_size_fixed =
1659
1801
 		dc->dcn_ip->bug_forcing_luma_and_chroma_request_to_same_size_fixed == dcn_bw_yes;
1660
1802
 	dc->dml.ip.dcfclk_cstate_latency = dc->dcn_ip->dcfclk_cstate_latency;
1661
-	kernel_fpu_end();
1803
+	DC_FP_END();
1662
1804
 }