add ax88772_rst

hc

2024-05-10 9999e48639b3cecb08ffb37358bcba3b48161b29

 kernel/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
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@@ -34,7 +34,10 @@
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 #include <linux/kref.h>
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 #include <linux/slab.h>
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 #include <linux/firmware.h>
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-#include <drm/drmP.h>
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+#include <linux/pm_runtime.h>
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+
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+#include <drm/drm_debugfs.h>
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+
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 #include "amdgpu.h"
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 #include "amdgpu_trace.h"
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@@ -152,7 +155,7 @@
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 		       seq);
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 	amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr,
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 			       seq, flags | AMDGPU_FENCE_FLAG_INT);
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-
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+	pm_runtime_get_noresume(adev_to_drm(adev)->dev);
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 	ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask];
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 	if (unlikely(rcu_dereference_protected(*ptr, 1))) {
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 		struct dma_fence *old;
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@@ -189,14 +192,22 @@
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  * Used For polling fence.
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  * Returns 0 on success, -ENOMEM on failure.
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  */
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-int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s)
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+int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s,
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+			      uint32_t timeout)
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 {
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 	uint32_t seq;
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+	signed long r;
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 	if (!s)
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 		return -EINVAL;
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 	seq = ++ring->fence_drv.sync_seq;
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+	r = amdgpu_fence_wait_polling(ring,
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+				      seq - ring->fence_drv.num_fences_mask,
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+				      timeout);
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+	if (r < 1)
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+		return -ETIMEDOUT;
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+
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 	amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr,
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 			       seq, 0);
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@@ -226,10 +237,13 @@
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  * Checks the current fence value and calculates the last
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  * signalled fence value. Wakes the fence queue if the
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  * sequence number has increased.
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+ *
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+ * Returns true if fence was processed
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  */
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-void amdgpu_fence_process(struct amdgpu_ring *ring)
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+bool amdgpu_fence_process(struct amdgpu_ring *ring)
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 {
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 	struct amdgpu_fence_driver *drv = &ring->fence_drv;
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+	struct amdgpu_device *adev = ring->adev;
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 	uint32_t seq, last_seq;
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 	int r;
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@@ -239,11 +253,12 @@
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 	} while (atomic_cmpxchg(&drv->last_seq, last_seq, seq) != last_seq);
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-	if (seq != ring->fence_drv.sync_seq)
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+	if (del_timer(&ring->fence_drv.fallback_timer) &&
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+	    seq != ring->fence_drv.sync_seq)
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 		amdgpu_fence_schedule_fallback(ring);
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 	if (unlikely(seq == last_seq))
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-		return;
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+		return false;
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 	last_seq &= drv->num_fences_mask;
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 	seq &= drv->num_fences_mask;
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@@ -269,7 +284,11 @@
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 			BUG();
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 		dma_fence_put(fence);
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+		pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
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+		pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
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 	} while (last_seq != seq);
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+
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+	return true;
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 }
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 /**
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@@ -284,7 +303,8 @@
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 	struct amdgpu_ring *ring = from_timer(ring, t,
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 					      fence_drv.fallback_timer);
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-	amdgpu_fence_process(ring);
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+	if (amdgpu_fence_process(ring))
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+		DRM_WARN("Fence fallback timer expired on ring %s\n", ring->name);
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 }
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 /**
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@@ -404,9 +424,8 @@
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 	ring->fence_drv.irq_type = irq_type;
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 	ring->fence_drv.initialized = true;
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-	dev_dbg(adev->dev, "fence driver on ring %d use gpu addr 0x%016llx, "
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-		"cpu addr 0x%p\n", ring->idx,
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-		ring->fence_drv.gpu_addr, ring->fence_drv.cpu_addr);
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+	DRM_DEV_DEBUG(adev->dev, "fence driver on ring %s use gpu addr 0x%016llx\n",
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+		      ring->name, ring->fence_drv.gpu_addr);
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 	return 0;
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 }
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@@ -423,11 +442,14 @@
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 int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,
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 				  unsigned num_hw_submission)
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 {
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+	struct amdgpu_device *adev = ring->adev;
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 	long timeout;
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 	int r;
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-	/* Check that num_hw_submission is a power of two */
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-	if ((num_hw_submission & (num_hw_submission - 1)) != 0)
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+	if (!adev)
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+		return -EINVAL;
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+
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+	if (!is_power_of_2(num_hw_submission))
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 		return -EINVAL;
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 	ring->fence_drv.cpu_addr = NULL;
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@@ -445,14 +467,22 @@
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 	if (!ring->fence_drv.fences)
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 		return -ENOMEM;
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-	/* No need to setup the GPU scheduler for KIQ ring */
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-	if (ring->funcs->type != AMDGPU_RING_TYPE_KIQ) {
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-		/* for non-sriov case, no timeout enforce on compute ring */
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-		if ((ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE)
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-				&& !amdgpu_sriov_vf(ring->adev))
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-			timeout = MAX_SCHEDULE_TIMEOUT;
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-		else
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-			timeout = msecs_to_jiffies(amdgpu_lockup_timeout);
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+	/* No need to setup the GPU scheduler for rings that don't need it */
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+	if (!ring->no_scheduler) {
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+		switch (ring->funcs->type) {
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+		case AMDGPU_RING_TYPE_GFX:
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+			timeout = adev->gfx_timeout;
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+			break;
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+		case AMDGPU_RING_TYPE_COMPUTE:
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+			timeout = adev->compute_timeout;
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+			break;
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+		case AMDGPU_RING_TYPE_SDMA:
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+			timeout = adev->sdma_timeout;
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+			break;
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+		default:
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+			timeout = adev->video_timeout;
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+			break;
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+		}
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 		r = drm_sched_init(&ring->sched, &amdgpu_sched_ops,
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 				   num_hw_submission, amdgpu_job_hang_limit,
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@@ -481,9 +511,6 @@
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  */
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 int amdgpu_fence_driver_init(struct amdgpu_device *adev)
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 {
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-	if (amdgpu_debugfs_fence_init(adev))
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-		dev_err(adev->dev, "fence debugfs file creation failed\n");
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-
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 	return 0;
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 }
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@@ -505,6 +532,8 @@
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 		if (!ring || !ring->fence_drv.initialized)
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 			continue;
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+		if (!ring->no_scheduler)
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+			drm_sched_fini(&ring->sched);
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 		r = amdgpu_fence_wait_empty(ring);
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 		if (r) {
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 			/* no need to trigger GPU reset as we are unloading */
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@@ -513,7 +542,7 @@
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 		if (ring->fence_drv.irq_src)
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 			amdgpu_irq_put(adev, ring->fence_drv.irq_src,
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 				       ring->fence_drv.irq_type);
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-		drm_sched_fini(&ring->sched);
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+
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 		del_timer_sync(&ring->fence_drv.fallback_timer);
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 		for (j = 0; j <= ring->fence_drv.num_fences_mask; ++j)
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 			dma_fence_put(ring->fence_drv.fences[j]);
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@@ -672,7 +701,7 @@
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 {
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 	struct drm_info_node *node = (struct drm_info_node *)m->private;
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 	struct drm_device *dev = node->minor->dev;
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-	struct amdgpu_device *adev = dev->dev_private;
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+	struct amdgpu_device *adev = drm_to_adev(dev);
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 	int i;
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 	for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
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@@ -683,22 +712,30 @@
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 		amdgpu_fence_process(ring);
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 		seq_printf(m, "--- ring %d (%s) ---\n", i, ring->name);
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-		seq_printf(m, "Last signaled fence 0x%08x\n",
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+		seq_printf(m, "Last signaled fence          0x%08x\n",
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 			   atomic_read(&ring->fence_drv.last_seq));
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-		seq_printf(m, "Last emitted        0x%08x\n",
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+		seq_printf(m, "Last emitted                 0x%08x\n",
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 			   ring->fence_drv.sync_seq);
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+
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+		if (ring->funcs->type == AMDGPU_RING_TYPE_GFX ||
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+		    ring->funcs->type == AMDGPU_RING_TYPE_SDMA) {
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+			seq_printf(m, "Last signaled trailing fence 0x%08x\n",
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+				   le32_to_cpu(*ring->trail_fence_cpu_addr));
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+			seq_printf(m, "Last emitted                 0x%08x\n",
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+				   ring->trail_seq);
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+		}
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 		if (ring->funcs->type != AMDGPU_RING_TYPE_GFX)
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 			continue;
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 		/* set in CP_VMID_PREEMPT and preemption occurred */
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-		seq_printf(m, "Last preempted      0x%08x\n",
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+		seq_printf(m, "Last preempted               0x%08x\n",
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 			   le32_to_cpu(*(ring->fence_drv.cpu_addr + 2)));
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 		/* set in CP_VMID_RESET and reset occurred */
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-		seq_printf(m, "Last reset          0x%08x\n",
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+		seq_printf(m, "Last reset                   0x%08x\n",
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 			   le32_to_cpu(*(ring->fence_drv.cpu_addr + 4)));
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 		/* Both preemption and reset occurred */
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-		seq_printf(m, "Last both           0x%08x\n",
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+		seq_printf(m, "Last both                    0x%08x\n",
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 			   le32_to_cpu(*(ring->fence_drv.cpu_addr + 6)));
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 	}
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 	return 0;
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@@ -713,10 +750,20 @@
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 {
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 	struct drm_info_node *node = (struct drm_info_node *) m->private;
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 	struct drm_device *dev = node->minor->dev;
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-	struct amdgpu_device *adev = dev->dev_private;
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+	struct amdgpu_device *adev = drm_to_adev(dev);
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+	int r;
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+
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+	r = pm_runtime_get_sync(dev->dev);
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+	if (r < 0) {
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+		pm_runtime_put_autosuspend(dev->dev);
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+		return 0;
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+	}
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 	seq_printf(m, "gpu recover\n");
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-	amdgpu_device_gpu_recover(adev, NULL, true);
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+	amdgpu_device_gpu_recover(adev, NULL);
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+
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+	pm_runtime_mark_last_busy(dev->dev);
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+	pm_runtime_put_autosuspend(dev->dev);
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 	return 0;
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 }
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@@ -735,8 +782,10 @@
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 {
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 #if defined(CONFIG_DEBUG_FS)
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 	if (amdgpu_sriov_vf(adev))
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-		return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_fence_list_sriov, 1);
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-	return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_fence_list, 2);
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+		return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_fence_list_sriov,
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+						ARRAY_SIZE(amdgpu_debugfs_fence_list_sriov));
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+	return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_fence_list,
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+					ARRAY_SIZE(amdgpu_debugfs_fence_list));
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 #else
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 	return 0;
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 #endif