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hc
2024-05-10 9999e48639b3cecb08ffb37358bcba3b48161b29 
 kernel/drivers/crypto/inside-secure/safexcel.h
....@@ -12,17 +12,44 @@
1212 #include <crypto/algapi.h>
1313 #include <crypto/internal/hash.h>
1414 #include <crypto/sha.h>
15
+#include <crypto/sha3.h>
1516 #include <crypto/skcipher.h>
17
+#include <linux/types.h>
1618 
17
-#define EIP197_HIA_VERSION_LE			0xca35
18
-#define EIP197_HIA_VERSION_BE			0x35ca
19
+#define EIP197_HIA_VERSION_BE			0xca35
20
+#define EIP197_HIA_VERSION_LE			0x35ca
21
+#define EIP97_VERSION_LE			0x9e61
22
+#define EIP196_VERSION_LE			0x3bc4
23
+#define EIP197_VERSION_LE			0x3ac5
24
+#define EIP96_VERSION_LE			0x9f60
25
+#define EIP201_VERSION_LE			0x36c9
26
+#define EIP206_VERSION_LE			0x31ce
27
+#define EIP207_VERSION_LE			0x30cf
28
+#define EIP197_REG_LO16(reg)			(reg & 0xffff)
29
+#define EIP197_REG_HI16(reg)			((reg >> 16) & 0xffff)
30
+#define EIP197_VERSION_MASK(reg)		((reg >> 16) & 0xfff)
31
+#define EIP197_VERSION_SWAP(reg)		(((reg & 0xf0) << 4) | \
32
+						((reg >> 4) & 0xf0) | \
33
+						((reg >> 12) & 0xf))
34
+
35
+/* EIP197 HIA OPTIONS ENCODING */
36
+#define EIP197_HIA_OPT_HAS_PE_ARB		BIT(29)
37
+
38
+/* EIP206 OPTIONS ENCODING */
39
+#define EIP206_OPT_ICE_TYPE(n)			((n>>8)&3)
40
+#define EIP206_OPT_OCE_TYPE(n)			((n>>10)&3)
41
+
42
+/* EIP197 OPTIONS ENCODING */
43
+#define EIP197_OPT_HAS_TRC			BIT(31)
1944 
2045 /* Static configuration */
2146 #define EIP197_DEFAULT_RING_SIZE		400
22
-#define EIP197_MAX_TOKENS			8
47
+#define EIP197_EMB_TOKENS			4 /* Pad CD to 16 dwords */
48
+#define EIP197_MAX_TOKENS			16
2349 #define EIP197_MAX_RINGS			4
24
-#define EIP197_FETCH_COUNT			1
50
+#define EIP197_FETCH_DEPTH			2
2551 #define EIP197_MAX_BATCH_SZ			64
52
+#define EIP197_MAX_RING_AIC			14
2653 
2754 #define EIP197_GFP_FLAGS(base)	((base).flags & CRYPTO_TFM_REQ_MAY_SLEEP ? \
2855 				 GFP_KERNEL : GFP_ATOMIC)
....@@ -38,6 +65,27 @@
3865 	char __##name##_desc[size] CRYPTO_MINALIGN_ATTR; \
3966 	struct type##_request *name = (void *)__##name##_desc
4067 
68
+/* Xilinx dev board base offsets */
69
+#define EIP197_XLX_GPIO_BASE		0x200000
70
+#define EIP197_XLX_IRQ_BLOCK_ID_ADDR	0x2000
71
+#define EIP197_XLX_IRQ_BLOCK_ID_VALUE	0x1fc2
72
+#define EIP197_XLX_USER_INT_ENB_MSK	0x2004
73
+#define EIP197_XLX_USER_INT_ENB_SET	0x2008
74
+#define EIP197_XLX_USER_INT_ENB_CLEAR	0x200c
75
+#define EIP197_XLX_USER_INT_BLOCK	0x2040
76
+#define EIP197_XLX_USER_INT_PEND	0x2048
77
+#define EIP197_XLX_USER_VECT_LUT0_ADDR	0x2080
78
+#define EIP197_XLX_USER_VECT_LUT0_IDENT	0x03020100
79
+#define EIP197_XLX_USER_VECT_LUT1_ADDR	0x2084
80
+#define EIP197_XLX_USER_VECT_LUT1_IDENT	0x07060504
81
+#define EIP197_XLX_USER_VECT_LUT2_ADDR	0x2088
82
+#define EIP197_XLX_USER_VECT_LUT2_IDENT	0x0b0a0908
83
+#define EIP197_XLX_USER_VECT_LUT3_ADDR	0x208c
84
+#define EIP197_XLX_USER_VECT_LUT3_IDENT	0x0f0e0d0c
85
+
86
+/* Helper defines for probe function */
87
+#define EIP197_IRQ_NUMBER(i, is_pci)	(i + is_pci)
88
+
4189 /* Register base offsets */
4290 #define EIP197_HIA_AIC(priv)		((priv)->base + (priv)->offsets.hia_aic)
4391 #define EIP197_HIA_AIC_G(priv)		((priv)->base + (priv)->offsets.hia_aic_g)
....@@ -49,6 +97,7 @@
4997 #define EIP197_HIA_DSE_THR(priv)	((priv)->base + (priv)->offsets.hia_dse_thr)
5098 #define EIP197_HIA_GEN_CFG(priv)	((priv)->base + (priv)->offsets.hia_gen_cfg)
5199 #define EIP197_PE(priv)			((priv)->base + (priv)->offsets.pe)
100
+#define EIP197_GLOBAL(priv)		((priv)->base + (priv)->offsets.global)
52101 
53102 /* EIP197 base offsets */
54103 #define EIP197_HIA_AIC_BASE		0x90000
....@@ -61,6 +110,7 @@
61110 #define EIP197_HIA_DSE_THR_BASE		0x8d040
62111 #define EIP197_HIA_GEN_CFG_BASE		0xf0000
63112 #define EIP197_PE_BASE			0xa0000
113
+#define EIP197_GLOBAL_BASE		0xf0000
64114 
65115 /* EIP97 base offsets */
66116 #define EIP97_HIA_AIC_BASE		0x0
....@@ -73,6 +123,7 @@
73123 #define EIP97_HIA_DSE_THR_BASE		0xf600
74124 #define EIP97_HIA_GEN_CFG_BASE		0x10000
75125 #define EIP97_PE_BASE			0x10000
126
+#define EIP97_GLOBAL_BASE		0x10000
76127 
77128 /* CDR/RDR register offsets */
78129 #define EIP197_HIA_xDR_OFF(priv, r)		(EIP197_HIA_AIC_xDR(priv) + (r) * 0x1000)
....@@ -105,6 +156,7 @@
105156 #define EIP197_HIA_AIC_R_ENABLED_STAT(r)	(0xe010 - EIP197_HIA_AIC_R_OFF(r))
106157 #define EIP197_HIA_AIC_R_ACK(r)			(0xe010 - EIP197_HIA_AIC_R_OFF(r))
107158 #define EIP197_HIA_AIC_R_ENABLE_CLR(r)		(0xe014 - EIP197_HIA_AIC_R_OFF(r))
159
+#define EIP197_HIA_AIC_R_VERSION(r)		(0xe01c - EIP197_HIA_AIC_R_OFF(r))
108160 #define EIP197_HIA_AIC_G_ENABLE_CTRL		0xf808
109161 #define EIP197_HIA_AIC_G_ENABLED_STAT		0xf810
110162 #define EIP197_HIA_AIC_G_ACK			0xf810
....@@ -115,15 +167,30 @@
115167 #define EIP197_PE_IN_TBUF_THRES(n)		(0x0100 + (0x2000 * (n)))
116168 #define EIP197_PE_ICE_SCRATCH_RAM(n)		(0x0800 + (0x2000 * (n)))
117169 #define EIP197_PE_ICE_PUE_CTRL(n)		(0x0c80 + (0x2000 * (n)))
170
+#define EIP197_PE_ICE_PUTF_CTRL(n)		(0x0d00 + (0x2000 * (n)))
118171 #define EIP197_PE_ICE_SCRATCH_CTRL(n)		(0x0d04 + (0x2000 * (n)))
119172 #define EIP197_PE_ICE_FPP_CTRL(n)		(0x0d80 + (0x2000 * (n)))
173
+#define EIP197_PE_ICE_PPTF_CTRL(n)		(0x0e00 + (0x2000 * (n)))
120174 #define EIP197_PE_ICE_RAM_CTRL(n)		(0x0ff0 + (0x2000 * (n)))
175
+#define EIP197_PE_ICE_VERSION(n)		(0x0ffc + (0x2000 * (n)))
176
+#define EIP197_PE_EIP96_TOKEN_CTRL(n)		(0x1000 + (0x2000 * (n)))
121177 #define EIP197_PE_EIP96_FUNCTION_EN(n)		(0x1004 + (0x2000 * (n)))
122178 #define EIP197_PE_EIP96_CONTEXT_CTRL(n)		(0x1008 + (0x2000 * (n)))
123179 #define EIP197_PE_EIP96_CONTEXT_STAT(n)		(0x100c + (0x2000 * (n)))
180
+#define EIP197_PE_EIP96_TOKEN_CTRL2(n)		(0x102c + (0x2000 * (n)))
181
+#define EIP197_PE_EIP96_FUNCTION2_EN(n)		(0x1030 + (0x2000 * (n)))
182
+#define EIP197_PE_EIP96_OPTIONS(n)		(0x13f8 + (0x2000 * (n)))
183
+#define EIP197_PE_EIP96_VERSION(n)		(0x13fc + (0x2000 * (n)))
184
+#define EIP197_PE_OCE_VERSION(n)		(0x1bfc + (0x2000 * (n)))
124185 #define EIP197_PE_OUT_DBUF_THRES(n)		(0x1c00 + (0x2000 * (n)))
125186 #define EIP197_PE_OUT_TBUF_THRES(n)		(0x1d00 + (0x2000 * (n)))
187
+#define EIP197_PE_PSE_VERSION(n)		(0x1efc + (0x2000 * (n)))
188
+#define EIP197_PE_DEBUG(n)			(0x1ff4 + (0x2000 * (n)))
189
+#define EIP197_PE_OPTIONS(n)			(0x1ff8 + (0x2000 * (n)))
190
+#define EIP197_PE_VERSION(n)			(0x1ffc + (0x2000 * (n)))
126191 #define EIP197_MST_CTRL				0xfff4
192
+#define EIP197_OPTIONS				0xfff8
193
+#define EIP197_VERSION				0xfffc
127194 
128195 /* EIP197-specific registers, no indirection */
129196 #define EIP197_CLASSIFICATION_RAMS		0xe0000
....@@ -138,10 +205,18 @@
138205 #define EIP197_TRC_ECCADMINSTAT			0xf0838
139206 #define EIP197_TRC_ECCDATASTAT			0xf083c
140207 #define EIP197_TRC_ECCDATA			0xf0840
208
+#define EIP197_STRC_CONFIG			0xf43f0
209
+#define EIP197_FLUE_CACHEBASE_LO(n)		(0xf6000 + (32 * (n)))
210
+#define EIP197_FLUE_CACHEBASE_HI(n)		(0xf6004 + (32 * (n)))
211
+#define EIP197_FLUE_CONFIG(n)			(0xf6010 + (32 * (n)))
212
+#define EIP197_FLUE_OFFSETS			0xf6808
213
+#define EIP197_FLUE_ARC4_OFFSET			0xf680c
214
+#define EIP197_FLUE_IFC_LUT(n)			(0xf6820 + (4 * (n)))
141215 #define EIP197_CS_RAM_CTRL			0xf7ff0
142216 
143217 /* EIP197_HIA_xDR_DESC_SIZE */
144218 #define EIP197_xDR_DESC_MODE_64BIT		BIT(31)
219
+#define EIP197_CDR_DESC_MODE_ADCP		BIT(30)
145220 
146221 /* EIP197_HIA_xDR_DMA_CFG */
147222 #define EIP197_HIA_xDR_WR_RES_BUF		BIT(22)
....@@ -167,7 +242,6 @@
167242 /* EIP197_HIA_xDR_PROC_COUNT */
168243 #define EIP197_xDR_PROC_xD_PKT_OFFSET		24
169244 #define EIP197_xDR_PROC_xD_PKT_MASK		GENMASK(6, 0)
170
-#define EIP197_xDR_PROC_xD_COUNT(n)		((n) << 2)
171245 #define EIP197_xDR_PROC_xD_PKT(n)		((n) << 24)
172246 #define EIP197_xDR_PROC_CLR_COUNT		BIT(31)
173247 
....@@ -182,9 +256,24 @@
182256 #define EIP197_HIA_RA_PE_CTRL_EN		BIT(30)
183257 
184258 /* EIP197_HIA_OPTIONS */
259
+#define EIP197_N_RINGS_OFFSET			0
260
+#define EIP197_N_RINGS_MASK			GENMASK(3, 0)
185261 #define EIP197_N_PES_OFFSET			4
186262 #define EIP197_N_PES_MASK			GENMASK(4, 0)
187263 #define EIP97_N_PES_MASK			GENMASK(2, 0)
264
+#define EIP197_HWDATAW_OFFSET			25
265
+#define EIP197_HWDATAW_MASK			GENMASK(3, 0)
266
+#define EIP97_HWDATAW_MASK			GENMASK(2, 0)
267
+#define EIP197_CFSIZE_OFFSET			9
268
+#define EIP197_CFSIZE_ADJUST			4
269
+#define EIP97_CFSIZE_OFFSET			8
270
+#define EIP197_CFSIZE_MASK			GENMASK(2, 0)
271
+#define EIP97_CFSIZE_MASK			GENMASK(3, 0)
272
+#define EIP197_RFSIZE_OFFSET			12
273
+#define EIP197_RFSIZE_ADJUST			4
274
+#define EIP97_RFSIZE_OFFSET			12
275
+#define EIP197_RFSIZE_MASK			GENMASK(2, 0)
276
+#define EIP97_RFSIZE_MASK			GENMASK(3, 0)
188277 
189278 /* EIP197_HIA_AIC_R_ENABLE_CTRL */
190279 #define EIP197_CDR_IRQ(n)			BIT((n) * 2)
....@@ -198,13 +287,18 @@
198287 #define EIP197_HIA_DxE_CFG_MIN_CTRL_SIZE(n)	((n) << 16)
199288 #define EIP197_HIA_DxE_CFG_CTRL_CACHE_CTRL(n)	(((n) & 0x7) << 20)
200289 #define EIP197_HIA_DxE_CFG_MAX_CTRL_SIZE(n)	((n) << 24)
201
-#define EIP197_HIA_DFE_CFG_DIS_DEBUG		(BIT(31) | BIT(29))
290
+#define EIP197_HIA_DFE_CFG_DIS_DEBUG		GENMASK(31, 29)
202291 #define EIP197_HIA_DSE_CFG_EN_SINGLE_WR		BIT(29)
203
-#define EIP197_HIA_DSE_CFG_DIS_DEBUG		BIT(31)
292
+#define EIP197_HIA_DSE_CFG_DIS_DEBUG		GENMASK(31, 30)
204293 
205294 /* EIP197_HIA_DFE/DSE_THR_CTRL */
206295 #define EIP197_DxE_THR_CTRL_EN			BIT(30)
207296 #define EIP197_DxE_THR_CTRL_RESET_PE		BIT(31)
297
+
298
+/* EIP197_PE_ICE_PUE/FPP_CTRL */
299
+#define EIP197_PE_ICE_UENG_START_OFFSET(n)	((n) << 16)
300
+#define EIP197_PE_ICE_UENG_INIT_ALIGN_MASK	0x7ff0
301
+#define EIP197_PE_ICE_UENG_DEBUG_RESET		BIT(3)
208302 
209303 /* EIP197_HIA_AIC_G_ENABLED_STAT */
210304 #define EIP197_G_IRQ_DFE(n)			BIT((n) << 1)
....@@ -222,6 +316,7 @@
222316 #define EIP197_MST_CTRL_TX_MAX_CMD(n)		(((n) & 0xf) << 20)
223317 #define EIP197_MST_CTRL_BYTE_SWAP		BIT(24)
224318 #define EIP197_MST_CTRL_NO_BYTE_SWAP		BIT(25)
319
+#define EIP197_MST_CTRL_BYTE_SWAP_BITS          GENMASK(25, 24)
225320 
226321 /* EIP197_PE_IN_DBUF/TBUF_THRES */
227322 #define EIP197_PE_IN_xBUF_THRES_MIN(n)		((n) << 8)
....@@ -249,46 +344,37 @@
249344 #define EIP197_PE_ICE_RAM_CTRL_PUE_PROG_EN	BIT(0)
250345 #define EIP197_PE_ICE_RAM_CTRL_FPP_PROG_EN	BIT(1)
251346 
347
+/* EIP197_PE_EIP96_TOKEN_CTRL */
348
+#define EIP197_PE_EIP96_TOKEN_CTRL_CTX_UPDATES		BIT(16)
349
+#define EIP197_PE_EIP96_TOKEN_CTRL_NO_TOKEN_WAIT	BIT(17)
350
+#define EIP197_PE_EIP96_TOKEN_CTRL_ENABLE_TIMEOUT	BIT(22)
351
+
252352 /* EIP197_PE_EIP96_FUNCTION_EN */
253
-#define EIP197_FUNCTION_RSVD			(BIT(6) | BIT(15) | BIT(20) | BIT(23))
254
-#define EIP197_PROTOCOL_HASH_ONLY		BIT(0)
255
-#define EIP197_PROTOCOL_ENCRYPT_ONLY		BIT(1)
256
-#define EIP197_PROTOCOL_HASH_ENCRYPT		BIT(2)
257
-#define EIP197_PROTOCOL_HASH_DECRYPT		BIT(3)
258
-#define EIP197_PROTOCOL_ENCRYPT_HASH		BIT(4)
259
-#define EIP197_PROTOCOL_DECRYPT_HASH		BIT(5)
260
-#define EIP197_ALG_ARC4				BIT(7)
261
-#define EIP197_ALG_AES_ECB			BIT(8)
262
-#define EIP197_ALG_AES_CBC			BIT(9)
263
-#define EIP197_ALG_AES_CTR_ICM			BIT(10)
264
-#define EIP197_ALG_AES_OFB			BIT(11)
265
-#define EIP197_ALG_AES_CFB			BIT(12)
266
-#define EIP197_ALG_DES_ECB			BIT(13)
267
-#define EIP197_ALG_DES_CBC			BIT(14)
268
-#define EIP197_ALG_DES_OFB			BIT(16)
269
-#define EIP197_ALG_DES_CFB			BIT(17)
270
-#define EIP197_ALG_3DES_ECB			BIT(18)
271
-#define EIP197_ALG_3DES_CBC			BIT(19)
272
-#define EIP197_ALG_3DES_OFB			BIT(21)
273
-#define EIP197_ALG_3DES_CFB			BIT(22)
274
-#define EIP197_ALG_MD5				BIT(24)
275
-#define EIP197_ALG_HMAC_MD5			BIT(25)
276
-#define EIP197_ALG_SHA1				BIT(26)
277
-#define EIP197_ALG_HMAC_SHA1			BIT(27)
278
-#define EIP197_ALG_SHA2				BIT(28)
279
-#define EIP197_ALG_HMAC_SHA2			BIT(29)
280
-#define EIP197_ALG_AES_XCBC_MAC			BIT(30)
281
-#define EIP197_ALG_GCM_HASH			BIT(31)
353
+#define EIP197_FUNCTION_ALL			0xffffffff
282354 
283355 /* EIP197_PE_EIP96_CONTEXT_CTRL */
284356 #define EIP197_CONTEXT_SIZE(n)			(n)
285357 #define EIP197_ADDRESS_MODE			BIT(8)
286358 #define EIP197_CONTROL_MODE			BIT(9)
287359 
360
+/* EIP197_PE_EIP96_TOKEN_CTRL2 */
361
+#define EIP197_PE_EIP96_TOKEN_CTRL2_CTX_DONE	BIT(3)
362
+
363
+/* EIP197_PE_DEBUG */
364
+#define EIP197_DEBUG_OCE_BYPASS			BIT(1)
365
+
366
+/* EIP197_STRC_CONFIG */
367
+#define EIP197_STRC_CONFIG_INIT			BIT(31)
368
+#define EIP197_STRC_CONFIG_LARGE_REC(s)		(s<<8)
369
+#define EIP197_STRC_CONFIG_SMALL_REC(s)		(s<<0)
370
+
371
+/* EIP197_FLUE_CONFIG */
372
+#define EIP197_FLUE_CONFIG_MAGIC		0xc7000004
373
+
288374 /* Context Control */
289375 struct safexcel_context_record {
290
-	u32 control0;
291
-	u32 control1;
376
+	__le32 control0;
377
+	__le32 control1;
292378 
293379 	__le32 data[40];
294380 } __packed;
....@@ -313,27 +399,60 @@
313399 #define CONTEXT_CONTROL_CRYPTO_ALG_AES128	(0x5 << 17)
314400 #define CONTEXT_CONTROL_CRYPTO_ALG_AES192	(0x6 << 17)
315401 #define CONTEXT_CONTROL_CRYPTO_ALG_AES256	(0x7 << 17)
402
+#define CONTEXT_CONTROL_CRYPTO_ALG_CHACHA20	(0x8 << 17)
403
+#define CONTEXT_CONTROL_CRYPTO_ALG_SM4		(0xd << 17)
404
+#define CONTEXT_CONTROL_DIGEST_INITIAL		(0x0 << 21)
316405 #define CONTEXT_CONTROL_DIGEST_PRECOMPUTED	(0x1 << 21)
406
+#define CONTEXT_CONTROL_DIGEST_XCM		(0x2 << 21)
317407 #define CONTEXT_CONTROL_DIGEST_HMAC		(0x3 << 21)
318408 #define CONTEXT_CONTROL_CRYPTO_ALG_MD5		(0x0 << 23)
409
+#define CONTEXT_CONTROL_CRYPTO_ALG_CRC32	(0x0 << 23)
319410 #define CONTEXT_CONTROL_CRYPTO_ALG_SHA1		(0x2 << 23)
320411 #define CONTEXT_CONTROL_CRYPTO_ALG_SHA224	(0x4 << 23)
321412 #define CONTEXT_CONTROL_CRYPTO_ALG_SHA256	(0x3 << 23)
322413 #define CONTEXT_CONTROL_CRYPTO_ALG_SHA384	(0x6 << 23)
323414 #define CONTEXT_CONTROL_CRYPTO_ALG_SHA512	(0x5 << 23)
415
+#define CONTEXT_CONTROL_CRYPTO_ALG_GHASH	(0x4 << 23)
416
+#define CONTEXT_CONTROL_CRYPTO_ALG_XCBC128	(0x1 << 23)
417
+#define CONTEXT_CONTROL_CRYPTO_ALG_XCBC192	(0x2 << 23)
418
+#define CONTEXT_CONTROL_CRYPTO_ALG_XCBC256	(0x3 << 23)
419
+#define CONTEXT_CONTROL_CRYPTO_ALG_SM3		(0x7 << 23)
420
+#define CONTEXT_CONTROL_CRYPTO_ALG_SHA3_256	(0xb << 23)
421
+#define CONTEXT_CONTROL_CRYPTO_ALG_SHA3_224	(0xc << 23)
422
+#define CONTEXT_CONTROL_CRYPTO_ALG_SHA3_512	(0xd << 23)
423
+#define CONTEXT_CONTROL_CRYPTO_ALG_SHA3_384	(0xe << 23)
424
+#define CONTEXT_CONTROL_CRYPTO_ALG_POLY1305	(0xf << 23)
324425 #define CONTEXT_CONTROL_INV_FR			(0x5 << 24)
325426 #define CONTEXT_CONTROL_INV_TR			(0x6 << 24)
326427 
327428 /* control1 */
328429 #define CONTEXT_CONTROL_CRYPTO_MODE_ECB		(0 << 0)
329430 #define CONTEXT_CONTROL_CRYPTO_MODE_CBC		(1 << 0)
431
+#define CONTEXT_CONTROL_CHACHA20_MODE_256_32	(2 << 0)
432
+#define CONTEXT_CONTROL_CRYPTO_MODE_OFB		(4 << 0)
433
+#define CONTEXT_CONTROL_CRYPTO_MODE_CFB		(5 << 0)
434
+#define CONTEXT_CONTROL_CRYPTO_MODE_CTR_LOAD	(6 << 0)
435
+#define CONTEXT_CONTROL_CRYPTO_MODE_XTS		(7 << 0)
436
+#define CONTEXT_CONTROL_CRYPTO_MODE_XCM		((6 << 0) | BIT(17))
437
+#define CONTEXT_CONTROL_CHACHA20_MODE_CALC_OTK	(12 << 0)
330438 #define CONTEXT_CONTROL_IV0			BIT(5)
331439 #define CONTEXT_CONTROL_IV1			BIT(6)
332440 #define CONTEXT_CONTROL_IV2			BIT(7)
333441 #define CONTEXT_CONTROL_IV3			BIT(8)
334442 #define CONTEXT_CONTROL_DIGEST_CNT		BIT(9)
335443 #define CONTEXT_CONTROL_COUNTER_MODE		BIT(10)
444
+#define CONTEXT_CONTROL_CRYPTO_STORE		BIT(12)
336445 #define CONTEXT_CONTROL_HASH_STORE		BIT(19)
446
+
447
+#define EIP197_XCM_MODE_GCM			1
448
+#define EIP197_XCM_MODE_CCM			2
449
+
450
+#define EIP197_AEAD_TYPE_IPSEC_ESP		2
451
+#define EIP197_AEAD_TYPE_IPSEC_ESP_GMAC		3
452
+#define EIP197_AEAD_IPSEC_IV_SIZE		8
453
+#define EIP197_AEAD_IPSEC_NONCE_SIZE		4
454
+#define EIP197_AEAD_IPSEC_COUNTER_SIZE		4
455
+#define EIP197_AEAD_IPSEC_CCM_NONCE_SIZE	3
337456 
338457 /* The hash counter given to the engine in the context has a granularity of
339458  * 64 bits.
....@@ -345,6 +464,8 @@
345464 #define EIP197_TRC_ENABLE_1			BIT(5)
346465 #define EIP197_TRC_ENABLE_2			BIT(6)
347466 #define EIP197_TRC_ENABLE_MASK			GENMASK(6, 4)
467
+#define EIP197_CS_BANKSEL_MASK			GENMASK(14, 12)
468
+#define EIP197_CS_BANKSEL_OFS			12
348469 
349470 /* EIP197_TRC_PARAMS */
350471 #define EIP197_TRC_PARAMS_SW_RESET		BIT(0)
....@@ -362,19 +483,13 @@
362483 #define EIP197_TRC_PARAMS2_RC_SZ_SMALL(n)	((n) << 18)
363484 
364485 /* Cache helpers */
365
-#define EIP197B_CS_RC_MAX			52
366
-#define EIP197D_CS_RC_MAX			96
486
+#define EIP197_MIN_DSIZE			1024
487
+#define EIP197_MIN_ASIZE			8
488
+#define EIP197_CS_TRC_REC_WC			64
367489 #define EIP197_CS_RC_SIZE			(4 * sizeof(u32))
368490 #define EIP197_CS_RC_NEXT(x)			(x)
369491 #define EIP197_CS_RC_PREV(x)			((x) << 10)
370492 #define EIP197_RC_NULL				0x3ff
371
-#define EIP197B_CS_TRC_REC_WC			59
372
-#define EIP197D_CS_TRC_REC_WC			64
373
-#define EIP197B_CS_TRC_LG_REC_WC		73
374
-#define EIP197D_CS_TRC_LG_REC_WC		80
375
-#define EIP197B_CS_HT_WC			64
376
-#define EIP197D_CS_HT_WC			256
377
-
378493 
379494 /* Result data */
380495 struct result_data_desc {
....@@ -394,7 +509,7 @@
394509 	u16 application_id;
395510 	u16 rsvd1;
396511 
397
-	u32 rsvd2;
512
+	u32 rsvd2[5];
398513 } __packed;
399514 
400515 
....@@ -412,9 +527,16 @@
412527 
413528 	u32 data_lo;
414529 	u32 data_hi;
415
-
416
-	struct result_data_desc result_data;
417530 } __packed;
531
+
532
+/*
533
+ * The EIP(1)97 only needs to fetch the descriptor part of
534
+ * the result descriptor, not the result token part!
535
+ */
536
+#define EIP197_RD64_FETCH_SIZE		(sizeof(struct safexcel_result_desc) /\
537
+					 sizeof(u32))
538
+#define EIP197_RD64_RESULT_SIZE		(sizeof(struct result_data_desc) /\
539
+					 sizeof(u32))
418540 
419541 struct safexcel_token {
420542 	u32 packet_length:17;
....@@ -425,26 +547,37 @@
425547 
426548 #define EIP197_TOKEN_HASH_RESULT_VERIFY		BIT(16)
427549 
550
+#define EIP197_TOKEN_CTX_OFFSET(x)		(x)
551
+#define EIP197_TOKEN_DIRECTION_EXTERNAL		BIT(11)
552
+#define EIP197_TOKEN_EXEC_IF_SUCCESSFUL		(0x1 << 12)
553
+
428554 #define EIP197_TOKEN_STAT_LAST_HASH		BIT(0)
429555 #define EIP197_TOKEN_STAT_LAST_PACKET		BIT(1)
430556 #define EIP197_TOKEN_OPCODE_DIRECTION		0x0
431557 #define EIP197_TOKEN_OPCODE_INSERT		0x2
432558 #define EIP197_TOKEN_OPCODE_NOOP		EIP197_TOKEN_OPCODE_INSERT
433559 #define EIP197_TOKEN_OPCODE_RETRIEVE		0x4
560
+#define EIP197_TOKEN_OPCODE_INSERT_REMRES	0xa
434561 #define EIP197_TOKEN_OPCODE_VERIFY		0xd
562
+#define EIP197_TOKEN_OPCODE_CTX_ACCESS		0xe
435563 #define EIP197_TOKEN_OPCODE_BYPASS		GENMASK(3, 0)
436564 
437565 static inline void eip197_noop_token(struct safexcel_token *token)
438566 {
439567 	token->opcode = EIP197_TOKEN_OPCODE_NOOP;
440568 	token->packet_length = BIT(2);
569
+	token->stat = 0;
570
+	token->instructions = 0;
441571 }
442572 
443573 /* Instructions */
444574 #define EIP197_TOKEN_INS_INSERT_HASH_DIGEST	0x1c
575
+#define EIP197_TOKEN_INS_ORIGIN_IV0		0x14
576
+#define EIP197_TOKEN_INS_ORIGIN_TOKEN		0x1b
577
+#define EIP197_TOKEN_INS_ORIGIN_LEN(x)		((x) << 5)
445578 #define EIP197_TOKEN_INS_TYPE_OUTPUT		BIT(5)
446579 #define EIP197_TOKEN_INS_TYPE_HASH		BIT(6)
447
-#define EIP197_TOKEN_INS_TYPE_CRYTO		BIT(7)
580
+#define EIP197_TOKEN_INS_TYPE_CRYPTO		BIT(7)
448581 #define EIP197_TOKEN_INS_LAST			BIT(8)
449582 
450583 /* Processing Engine Control Data  */
....@@ -456,23 +589,26 @@
456589 	u16 application_id;
457590 	u16 rsvd;
458591 
459
-	u8 refresh:2;
460
-	u32 context_lo:30;
592
+	u32 context_lo;
461593 	u32 context_hi;
462594 
463595 	u32 control0;
464596 	u32 control1;
465597 
466
-	u32 token[EIP197_MAX_TOKENS];
598
+	u32 token[EIP197_EMB_TOKENS];
467599 } __packed;
468600 
469601 #define EIP197_OPTION_MAGIC_VALUE	BIT(0)
470602 #define EIP197_OPTION_64BIT_CTX		BIT(1)
603
+#define EIP197_OPTION_RC_AUTO		(0x2 << 3)
471604 #define EIP197_OPTION_CTX_CTRL_IN_CMD	BIT(8)
472605 #define EIP197_OPTION_2_TOKEN_IV_CMD	GENMASK(11, 10)
473606 #define EIP197_OPTION_4_TOKEN_IV_CMD	GENMASK(11, 9)
474607 
608
+#define EIP197_TYPE_BCLA		0x0
475609 #define EIP197_TYPE_EXTENDED		0x3
610
+#define EIP197_CONTEXT_SMALL		0x2
611
+#define EIP197_CONTEXT_SIZE_MASK	0x3
476612 
477613 /* Basic Command Descriptor format */
478614 struct safexcel_command_desc {
....@@ -480,19 +616,30 @@
480616 	u8 rsvd0:5;
481617 	u8 last_seg:1;
482618 	u8 first_seg:1;
483
-	u16 additional_cdata_size:8;
619
+	u8 additional_cdata_size:8;
484620 
485621 	u32 rsvd1;
486622 
487623 	u32 data_lo;
488624 	u32 data_hi;
489625 
626
+	u32 atok_lo;
627
+	u32 atok_hi;
628
+
490629 	struct safexcel_control_data_desc control_data;
491630 } __packed;
631
+
632
+#define EIP197_CD64_FETCH_SIZE		(sizeof(struct safexcel_command_desc) /\
633
+					sizeof(u32))
492634 
493635 /*
494636  * Internal structures & functions
495637  */
638
+
639
+#define EIP197_FW_TERMINAL_NOPS		2
640
+#define EIP197_FW_START_POLLCNT		16
641
+#define EIP197_FW_PUE_READY		0x14
642
+#define EIP197_FW_FPP_READY		0x18
496643 
497644 enum eip197_fw {
498645 	FW_IFPP = 0,
....@@ -502,15 +649,20 @@
502649 
503650 struct safexcel_desc_ring {
504651 	void *base;
652
+	void *shbase;
505653 	void *base_end;
654
+	void *shbase_end;
506655 	dma_addr_t base_dma;
656
+	dma_addr_t shbase_dma;
507657 
508658 	/* write and read pointers */
509659 	void *write;
660
+	void *shwrite;
510661 	void *read;
511662 
512663 	/* descriptor element offset */
513
-	unsigned offset;
664
+	unsigned int offset;
665
+	unsigned int shoffset;
514666 };
515667 
516668 enum safexcel_alg_type {
....@@ -525,9 +677,11 @@
525677 
526678 	u32 cd_size;
527679 	u32 cd_offset;
680
+	u32 cdsh_offset;
528681 
529682 	u32 rd_size;
530683 	u32 rd_offset;
684
+	u32 res_offset;
531685 };
532686 
533687 struct safexcel_work_data {
....@@ -564,12 +718,53 @@
564718 	 */
565719 	struct crypto_async_request *req;
566720 	struct crypto_async_request *backlog;
721
+
722
+	/* irq of this ring */
723
+	int irq;
567724 };
568725 
726
+/* EIP integration context flags */
569727 enum safexcel_eip_version {
570
-	EIP97IES = BIT(0),
571
-	EIP197B  = BIT(1),
572
-	EIP197D  = BIT(2),
728
+	/* Platform (EIP integration context) specifier */
729
+	EIP97IES_MRVL,
730
+	EIP197B_MRVL,
731
+	EIP197D_MRVL,
732
+	EIP197_DEVBRD
733
+};
734
+
735
+/* Priority we use for advertising our algorithms */
736
+#define SAFEXCEL_CRA_PRIORITY		300
737
+
738
+/* SM3 digest result for zero length message */
739
+#define EIP197_SM3_ZEROM_HASH	"\x1A\xB2\x1D\x83\x55\xCF\xA1\x7F" \
740
+				"\x8E\x61\x19\x48\x31\xE8\x1A\x8F" \
741
+				"\x22\xBE\xC8\xC7\x28\xFE\xFB\x74" \
742
+				"\x7E\xD0\x35\xEB\x50\x82\xAA\x2B"
743
+
744
+/* EIP algorithm presence flags */
745
+enum safexcel_eip_algorithms {
746
+	SAFEXCEL_ALG_BC0      = BIT(5),
747
+	SAFEXCEL_ALG_SM4      = BIT(6),
748
+	SAFEXCEL_ALG_SM3      = BIT(7),
749
+	SAFEXCEL_ALG_CHACHA20 = BIT(8),
750
+	SAFEXCEL_ALG_POLY1305 = BIT(9),
751
+	SAFEXCEL_SEQMASK_256   = BIT(10),
752
+	SAFEXCEL_SEQMASK_384   = BIT(11),
753
+	SAFEXCEL_ALG_AES      = BIT(12),
754
+	SAFEXCEL_ALG_AES_XFB  = BIT(13),
755
+	SAFEXCEL_ALG_DES      = BIT(15),
756
+	SAFEXCEL_ALG_DES_XFB  = BIT(16),
757
+	SAFEXCEL_ALG_ARC4     = BIT(18),
758
+	SAFEXCEL_ALG_AES_XTS  = BIT(20),
759
+	SAFEXCEL_ALG_WIRELESS = BIT(21),
760
+	SAFEXCEL_ALG_MD5      = BIT(22),
761
+	SAFEXCEL_ALG_SHA1     = BIT(23),
762
+	SAFEXCEL_ALG_SHA2_256 = BIT(25),
763
+	SAFEXCEL_ALG_SHA2_512 = BIT(26),
764
+	SAFEXCEL_ALG_XCBC_MAC = BIT(27),
765
+	SAFEXCEL_ALG_CBC_MAC_ALL = BIT(29),
766
+	SAFEXCEL_ALG_GHASH    = BIT(30),
767
+	SAFEXCEL_ALG_SHA3     = BIT(31),
573768 };
574769 
575770 struct safexcel_register_offsets {
....@@ -583,10 +778,33 @@
583778 	u32 hia_dse_thr;
584779 	u32 hia_gen_cfg;
585780 	u32 pe;
781
+	u32 global;
586782 };
587783 
588784 enum safexcel_flags {
589
-	EIP197_TRC_CACHE = BIT(0),
785
+	EIP197_TRC_CACHE	= BIT(0),
786
+	SAFEXCEL_HW_EIP197	= BIT(1),
787
+	EIP197_PE_ARB		= BIT(2),
788
+	EIP197_ICE		= BIT(3),
789
+	EIP197_SIMPLE_TRC	= BIT(4),
790
+	EIP197_OCE		= BIT(5),
791
+};
792
+
793
+struct safexcel_hwconfig {
794
+	enum safexcel_eip_algorithms algo_flags;
795
+	int hwver;
796
+	int hiaver;
797
+	int ppver;
798
+	int icever;
799
+	int pever;
800
+	int ocever;
801
+	int psever;
802
+	int hwdataw;
803
+	int hwcfsize;
804
+	int hwrfsize;
805
+	int hwnumpes;
806
+	int hwnumrings;
807
+	int hwnumraic;
590808 };
591809 
592810 struct safexcel_crypto_priv {
....@@ -598,6 +816,7 @@
598816 
599817 	enum safexcel_eip_version version;
600818 	struct safexcel_register_offsets offsets;
819
+	struct safexcel_hwconfig hwconfig;
601820 	u32 flags;
602821 
603822 	/* context DMA pool */
....@@ -615,21 +834,31 @@
615834 			     struct crypto_async_request *req, bool *complete,
616835 			     int *ret);
617836 	struct safexcel_context_record *ctxr;
837
+	struct safexcel_crypto_priv *priv;
618838 	dma_addr_t ctxr_dma;
839
+
840
+	union {
841
+		__le32 le[SHA3_512_BLOCK_SIZE / 4];
842
+		__be32 be[SHA3_512_BLOCK_SIZE / 4];
843
+		u32 word[SHA3_512_BLOCK_SIZE / 4];
844
+		u8 byte[SHA3_512_BLOCK_SIZE];
845
+	} ipad, opad;
619846 
620847 	int ring;
621848 	bool needs_inv;
622849 	bool exit_inv;
623850 };
624851 
852
+#define HASH_CACHE_SIZE			SHA512_BLOCK_SIZE
853
+
625854 struct safexcel_ahash_export_state {
626
-	u64 len[2];
627
-	u64 processed[2];
855
+	u64 len;
856
+	u64 processed;
628857 
629858 	u32 digest;
630859 
631860 	u32 state[SHA512_DIGEST_SIZE / sizeof(u32)];
632
-	u8 cache[SHA512_BLOCK_SIZE];
861
+	u8 cache[HASH_CACHE_SIZE];
633862 };
634863 
635864 /*
....@@ -640,7 +869,7 @@
640869 struct safexcel_alg_template {
641870 	struct safexcel_crypto_priv *priv;
642871 	enum safexcel_alg_type type;
643
-	u32 engines;
872
+	enum safexcel_eip_algorithms algo_mask;
644873 	union {
645874 		struct skcipher_alg skcipher;
646875 		struct aead_alg aead;
....@@ -655,7 +884,7 @@
655884 
656885 void safexcel_dequeue(struct safexcel_crypto_priv *priv, int ring);
657886 int safexcel_rdesc_check_errors(struct safexcel_crypto_priv *priv,
658
-				struct safexcel_result_desc *rdesc);
887
+				void *rdp);
659888 void safexcel_complete(struct safexcel_crypto_priv *priv, int ring);
660889 int safexcel_invalidate_cache(struct crypto_async_request *async,
661890 			      struct safexcel_crypto_priv *priv,
....@@ -674,7 +903,8 @@
674903 						 bool first, bool last,
675904 						 dma_addr_t data, u32 len,
676905 						 u32 full_data_len,
677
-						 dma_addr_t context);
906
+						 dma_addr_t context,
907
+						 struct safexcel_token **atoken);
678908 struct safexcel_result_desc *safexcel_add_rdesc(struct safexcel_crypto_priv *priv,
679909 						 int ring_id,
680910 						bool first, bool last,
....@@ -691,8 +921,9 @@
691921 inline struct crypto_async_request *
692922 safexcel_rdr_req_get(struct safexcel_crypto_priv *priv, int ring);
693923 void safexcel_inv_complete(struct crypto_async_request *req, int error);
694
-int safexcel_hmac_setkey(const char *alg, const u8 *key, unsigned int keylen,
695
-			 void *istate, void *ostate);
924
+int safexcel_hmac_setkey(struct safexcel_context *base, const u8 *key,
925
+			 unsigned int keylen, const char *alg,
926
+			 unsigned int state_sz);
696927 
697928 /* available algorithms */
698929 extern struct safexcel_alg_template safexcel_alg_ecb_des;
....@@ -701,6 +932,9 @@
701932 extern struct safexcel_alg_template safexcel_alg_cbc_des3_ede;
702933 extern struct safexcel_alg_template safexcel_alg_ecb_aes;
703934 extern struct safexcel_alg_template safexcel_alg_cbc_aes;
935
+extern struct safexcel_alg_template safexcel_alg_cfb_aes;
936
+extern struct safexcel_alg_template safexcel_alg_ofb_aes;
937
+extern struct safexcel_alg_template safexcel_alg_ctr_aes;
704938 extern struct safexcel_alg_template safexcel_alg_md5;
705939 extern struct safexcel_alg_template safexcel_alg_sha1;
706940 extern struct safexcel_alg_template safexcel_alg_sha224;
....@@ -718,5 +952,52 @@
718952 extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha256_cbc_aes;
719953 extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha384_cbc_aes;
720954 extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha512_cbc_aes;
955
+extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha1_cbc_des3_ede;
956
+extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha1_ctr_aes;
957
+extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha224_ctr_aes;
958
+extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha256_ctr_aes;
959
+extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha384_ctr_aes;
960
+extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha512_ctr_aes;
961
+extern struct safexcel_alg_template safexcel_alg_xts_aes;
962
+extern struct safexcel_alg_template safexcel_alg_gcm;
963
+extern struct safexcel_alg_template safexcel_alg_ccm;
964
+extern struct safexcel_alg_template safexcel_alg_crc32;
965
+extern struct safexcel_alg_template safexcel_alg_cbcmac;
966
+extern struct safexcel_alg_template safexcel_alg_xcbcmac;
967
+extern struct safexcel_alg_template safexcel_alg_cmac;
968
+extern struct safexcel_alg_template safexcel_alg_chacha20;
969
+extern struct safexcel_alg_template safexcel_alg_chachapoly;
970
+extern struct safexcel_alg_template safexcel_alg_chachapoly_esp;
971
+extern struct safexcel_alg_template safexcel_alg_sm3;
972
+extern struct safexcel_alg_template safexcel_alg_hmac_sm3;
973
+extern struct safexcel_alg_template safexcel_alg_ecb_sm4;
974
+extern struct safexcel_alg_template safexcel_alg_cbc_sm4;
975
+extern struct safexcel_alg_template safexcel_alg_ofb_sm4;
976
+extern struct safexcel_alg_template safexcel_alg_cfb_sm4;
977
+extern struct safexcel_alg_template safexcel_alg_ctr_sm4;
978
+extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha1_cbc_sm4;
979
+extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sm3_cbc_sm4;
980
+extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha1_ctr_sm4;
981
+extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sm3_ctr_sm4;
982
+extern struct safexcel_alg_template safexcel_alg_sha3_224;
983
+extern struct safexcel_alg_template safexcel_alg_sha3_256;
984
+extern struct safexcel_alg_template safexcel_alg_sha3_384;
985
+extern struct safexcel_alg_template safexcel_alg_sha3_512;
986
+extern struct safexcel_alg_template safexcel_alg_hmac_sha3_224;
987
+extern struct safexcel_alg_template safexcel_alg_hmac_sha3_256;
988
+extern struct safexcel_alg_template safexcel_alg_hmac_sha3_384;
989
+extern struct safexcel_alg_template safexcel_alg_hmac_sha3_512;
990
+extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha1_cbc_des;
991
+extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha256_cbc_des3_ede;
992
+extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha224_cbc_des3_ede;
993
+extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha512_cbc_des3_ede;
994
+extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha384_cbc_des3_ede;
995
+extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha256_cbc_des;
996
+extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha224_cbc_des;
997
+extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha512_cbc_des;
998
+extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha384_cbc_des;
999
+extern struct safexcel_alg_template safexcel_alg_rfc4106_gcm;
1000
+extern struct safexcel_alg_template safexcel_alg_rfc4543_gcm;
1001
+extern struct safexcel_alg_template safexcel_alg_rfc4309_ccm;
7211002 
7221003 #endif