add ax88772_rst

hc

2024-05-10 9999e48639b3cecb08ffb37358bcba3b48161b29

 kernel/arch/riscv/include/asm/mmio.h
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@@ -101,9 +101,9 @@
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  * Relaxed I/O memory access primitives. These follow the Device memory
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  * ordering rules but do not guarantee any ordering relative to Normal memory
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  * accesses.  These are defined to order the indicated access (either a read or
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- * write) with all other I/O memory accesses. Since the platform specification
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- * defines that all I/O regions are strongly ordered on channel 2, no explicit
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- * fences are required to enforce this ordering.
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+ * write) with all other I/O memory accesses to the same peripheral. Since the
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+ * platform specification defines that all I/O regions are strongly ordered on
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+ * channel 0, no explicit fences are required to enforce this ordering.
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  */
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 /* FIXME: These are now the same as asm-generic */
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 #define __io_rbr()		do {} while (0)
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@@ -125,14 +125,14 @@
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 #endif
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 /*
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- * I/O memory access primitives. Reads are ordered relative to any
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- * following Normal memory access. Writes are ordered relative to any prior
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- * Normal memory access.  The memory barriers here are necessary as RISC-V
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+ * I/O memory access primitives.  Reads are ordered relative to any following
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+ * Normal memory read and delay() loop.  Writes are ordered relative to any
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+ * prior Normal memory write.  The memory barriers here are necessary as RISC-V
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  * doesn't define any ordering between the memory space and the I/O space.
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  */
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 #define __io_br()	do {} while (0)
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-#define __io_ar(v)	__asm__ __volatile__ ("fence i,r" : : : "memory")
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-#define __io_bw()	__asm__ __volatile__ ("fence w,o" : : : "memory")
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+#define __io_ar(v)	({ __asm__ __volatile__ ("fence i,ir" : : : "memory"); })
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+#define __io_bw()	({ __asm__ __volatile__ ("fence w,o" : : : "memory"); })
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 #define __io_aw()	mmiowb_set_pending()
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 #define readb(c)	({ u8  __v; __io_br(); __v = readb_cpu(c); __io_ar(__v); __v; })