add ax88772_rst

hc

2024-05-10 9999e48639b3cecb08ffb37358bcba3b48161b29

 kernel/arch/riscv/include/asm/io.h
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@@ -1,3 +1,4 @@
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+/* SPDX-License-Identifier: GPL-2.0-only */
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 /*
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  * {read,write}{b,w,l,q} based on arch/arm64/include/asm/io.h
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  *   which was based on arch/arm/include/io.h
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@@ -5,180 +6,29 @@
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  * Copyright (C) 1996-2000 Russell King
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  * Copyright (C) 2012 ARM Ltd.
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  * Copyright (C) 2014 Regents of the University of California
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- *
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- *   This program is free software; you can redistribute it and/or
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- *   modify it under the terms of the GNU General Public License
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- *   as published by the Free Software Foundation, version 2.
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- *
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- *   This program is distributed in the hope that it will be useful,
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- *   but WITHOUT ANY WARRANTY; without even the implied warranty of
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- *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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- *   GNU General Public License for more details.
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  */
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10
 
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 #ifndef _ASM_RISCV_IO_H
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 #define _ASM_RISCV_IO_H
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 #include <linux/types.h>
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-
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-extern void __iomem *ioremap(phys_addr_t offset, unsigned long size);
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+#include <linux/pgtable.h>
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+#include <asm/mmiowb.h>
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+#include <asm/early_ioremap.h>
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 /*
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- * The RISC-V ISA doesn't yet specify how to query or modify PMAs, so we can't
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- * change the properties of memory regions.  This should be fixed by the
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- * upcoming platform spec.
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+ * MMIO access functions are separated out to break dependency cycles
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+ * when using {read,write}* fns in low-level headers
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  */
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-#define ioremap_nocache(addr, size) ioremap((addr), (size))
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-#define ioremap_wc(addr, size) ioremap((addr), (size))
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-#define ioremap_wt(addr, size) ioremap((addr), (size))
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-
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-extern void iounmap(volatile void __iomem *addr);
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-
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-/* Generic IO read/write.  These perform native-endian accesses. */
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-#define __raw_writeb __raw_writeb
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-static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
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-{
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-	asm volatile("sb %0, 0(%1)" : : "r" (val), "r" (addr));
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-}
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-
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-#define __raw_writew __raw_writew
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-static inline void __raw_writew(u16 val, volatile void __iomem *addr)
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-{
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-	asm volatile("sh %0, 0(%1)" : : "r" (val), "r" (addr));
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-}
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-
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-#define __raw_writel __raw_writel
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-static inline void __raw_writel(u32 val, volatile void __iomem *addr)
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-{
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-	asm volatile("sw %0, 0(%1)" : : "r" (val), "r" (addr));
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-}
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-
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-#ifdef CONFIG_64BIT
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-#define __raw_writeq __raw_writeq
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-static inline void __raw_writeq(u64 val, volatile void __iomem *addr)
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-{
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-	asm volatile("sd %0, 0(%1)" : : "r" (val), "r" (addr));
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-}
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-#endif
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-
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-#define __raw_readb __raw_readb
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-static inline u8 __raw_readb(const volatile void __iomem *addr)
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-{
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-	u8 val;
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-
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-	asm volatile("lb %0, 0(%1)" : "=r" (val) : "r" (addr));
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-	return val;
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-}
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-
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-#define __raw_readw __raw_readw
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-static inline u16 __raw_readw(const volatile void __iomem *addr)
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-{
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-	u16 val;
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-
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-	asm volatile("lh %0, 0(%1)" : "=r" (val) : "r" (addr));
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-	return val;
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-}
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-
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-#define __raw_readl __raw_readl
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-static inline u32 __raw_readl(const volatile void __iomem *addr)
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-{
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-	u32 val;
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-
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-	asm volatile("lw %0, 0(%1)" : "=r" (val) : "r" (addr));
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-	return val;
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-}
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-
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-#ifdef CONFIG_64BIT
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-#define __raw_readq __raw_readq
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-static inline u64 __raw_readq(const volatile void __iomem *addr)
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-{
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-	u64 val;
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-
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-	asm volatile("ld %0, 0(%1)" : "=r" (val) : "r" (addr));
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-	return val;
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-}
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-#endif
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+#include <asm/mmio.h>
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 /*
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- * FIXME: I'm flip-flopping on whether or not we should keep this or enforce
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- * the ordering with I/O on spinlocks like PowerPC does.  The worry is that
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- * drivers won't get this correct, but I also don't want to introduce a fence
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- * into the lock code that otherwise only uses AMOs (and is essentially defined
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- * by the ISA to be correct).   For now I'm leaving this here: "o,w" is
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- * sufficient to ensure that all writes to the device have completed before the
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- * write to the spinlock is allowed to commit.  I surmised this from reading
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- * "ACQUIRES VS I/O ACCESSES" in memory-barriers.txt.
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+ *  I/O port access constants.
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  */
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-#define mmiowb()	__asm__ __volatile__ ("fence o,w" : : : "memory");
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-
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-/*
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- * Unordered I/O memory access primitives.  These are even more relaxed than
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- * the relaxed versions, as they don't even order accesses between successive
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- * operations to the I/O regions.
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- */
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-#define readb_cpu(c)		({ u8  __r = __raw_readb(c); __r; })
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-#define readw_cpu(c)		({ u16 __r = le16_to_cpu((__force __le16)__raw_readw(c)); __r; })
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-#define readl_cpu(c)		({ u32 __r = le32_to_cpu((__force __le32)__raw_readl(c)); __r; })
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-
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-#define writeb_cpu(v,c)		((void)__raw_writeb((v),(c)))
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-#define writew_cpu(v,c)		((void)__raw_writew((__force u16)cpu_to_le16(v),(c)))
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-#define writel_cpu(v,c)		((void)__raw_writel((__force u32)cpu_to_le32(v),(c)))
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-
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-#ifdef CONFIG_64BIT
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-#define readq_cpu(c)		({ u64 __r = le64_to_cpu((__force __le64)__raw_readq(c)); __r; })
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-#define writeq_cpu(v,c)		((void)__raw_writeq((__force u64)cpu_to_le64(v),(c)))
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-#endif
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-
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-/*
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- * Relaxed I/O memory access primitives. These follow the Device memory
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- * ordering rules but do not guarantee any ordering relative to Normal memory
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- * accesses.  These are defined to order the indicated access (either a read or
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- * write) with all other I/O memory accesses. Since the platform specification
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- * defines that all I/O regions are strongly ordered on channel 2, no explicit
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- * fences are required to enforce this ordering.
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- */
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-/* FIXME: These are now the same as asm-generic */
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-#define __io_rbr()		do {} while (0)
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-#define __io_rar()		do {} while (0)
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-#define __io_rbw()		do {} while (0)
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-#define __io_raw()		do {} while (0)
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-
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-#define readb_relaxed(c)	({ u8  __v; __io_rbr(); __v = readb_cpu(c); __io_rar(); __v; })
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-#define readw_relaxed(c)	({ u16 __v; __io_rbr(); __v = readw_cpu(c); __io_rar(); __v; })
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-#define readl_relaxed(c)	({ u32 __v; __io_rbr(); __v = readl_cpu(c); __io_rar(); __v; })
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-
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-#define writeb_relaxed(v,c)	({ __io_rbw(); writeb_cpu((v),(c)); __io_raw(); })
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-#define writew_relaxed(v,c)	({ __io_rbw(); writew_cpu((v),(c)); __io_raw(); })
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-#define writel_relaxed(v,c)	({ __io_rbw(); writel_cpu((v),(c)); __io_raw(); })
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-
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-#ifdef CONFIG_64BIT
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-#define readq_relaxed(c)	({ u64 __v; __io_rbr(); __v = readq_cpu(c); __io_rar(); __v; })
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-#define writeq_relaxed(v,c)	({ __io_rbw(); writeq_cpu((v),(c)); __io_raw(); })
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-#endif
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-
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-/*
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- * I/O memory access primitives. Reads are ordered relative to any
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- * following Normal memory access. Writes are ordered relative to any prior
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- * Normal memory access.  The memory barriers here are necessary as RISC-V
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- * doesn't define any ordering between the memory space and the I/O space.
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- */
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-#define __io_br()	do {} while (0)
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-#define __io_ar()	__asm__ __volatile__ ("fence i,r" : : : "memory");
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-#define __io_bw()	__asm__ __volatile__ ("fence w,o" : : : "memory");
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-#define __io_aw()	do {} while (0)
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-
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-#define readb(c)	({ u8  __v; __io_br(); __v = readb_cpu(c); __io_ar(); __v; })
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-#define readw(c)	({ u16 __v; __io_br(); __v = readw_cpu(c); __io_ar(); __v; })
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-#define readl(c)	({ u32 __v; __io_br(); __v = readl_cpu(c); __io_ar(); __v; })
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-
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-#define writeb(v,c)	({ __io_bw(); writeb_cpu((v),(c)); __io_aw(); })
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-#define writew(v,c)	({ __io_bw(); writew_cpu((v),(c)); __io_aw(); })
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-#define writel(v,c)	({ __io_bw(); writel_cpu((v),(c)); __io_aw(); })
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-
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-#ifdef CONFIG_64BIT
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-#define readq(c)	({ u64 __v; __io_br(); __v = readq_cpu(c); __io_ar(); __v; })
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-#define writeq(v,c)	({ __io_bw(); writeq_cpu((v),(c)); __io_aw(); })
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-#endif
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+#ifdef CONFIG_MMU
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+#define IO_SPACE_LIMIT		(PCI_IO_SIZE - 1)
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+#define PCI_IOBASE		((void __iomem *)PCI_IO_START)
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+#endif /* CONFIG_MMU */
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 /*
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  * Emulation routines for the port-mapped IO space used by some PCI drivers.
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@@ -198,20 +48,20 @@
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  * writes.
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  */
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 #define __io_pbr()	__asm__ __volatile__ ("fence io,i"  : : : "memory");
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-#define __io_par()	__asm__ __volatile__ ("fence i,ior" : : : "memory");
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+#define __io_par(v)	__asm__ __volatile__ ("fence i,ior" : : : "memory");
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 #define __io_pbw()	__asm__ __volatile__ ("fence iow,o" : : : "memory");
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 #define __io_paw()	__asm__ __volatile__ ("fence o,io"  : : : "memory");
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-#define inb(c)		({ u8  __v; __io_pbr(); __v = readb_cpu((void*)(PCI_IOBASE + (c))); __io_par(); __v; })
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-#define inw(c)		({ u16 __v; __io_pbr(); __v = readw_cpu((void*)(PCI_IOBASE + (c))); __io_par(); __v; })
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-#define inl(c)		({ u32 __v; __io_pbr(); __v = readl_cpu((void*)(PCI_IOBASE + (c))); __io_par(); __v; })
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+#define inb(c)		({ u8  __v; __io_pbr(); __v = readb_cpu((void*)(PCI_IOBASE + (c))); __io_par(__v); __v; })
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+#define inw(c)		({ u16 __v; __io_pbr(); __v = readw_cpu((void*)(PCI_IOBASE + (c))); __io_par(__v); __v; })
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+#define inl(c)		({ u32 __v; __io_pbr(); __v = readl_cpu((void*)(PCI_IOBASE + (c))); __io_par(__v); __v; })
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 #define outb(v,c)	({ __io_pbw(); writeb_cpu((v),(void*)(PCI_IOBASE + (c))); __io_paw(); })
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 #define outw(v,c)	({ __io_pbw(); writew_cpu((v),(void*)(PCI_IOBASE + (c))); __io_paw(); })
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 #define outl(v,c)	({ __io_pbw(); writel_cpu((v),(void*)(PCI_IOBASE + (c))); __io_paw(); })
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 #ifdef CONFIG_64BIT
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-#define inq(c)		({ u64 __v; __io_pbr(); __v = readq_cpu((void*)(c)); __io_par(); __v; })
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+#define inq(c)		({ u64 __v; __io_pbr(); __v = readq_cpu((void*)(c)); __io_par(__v); __v; })
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 #define outq(v,c)	({ __io_pbw(); writeq_cpu((v),(void*)(c)); __io_paw(); })
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 #endif
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..
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@@ -254,19 +104,19 @@
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 		afence;								\
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 	}
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-__io_reads_ins(reads,  u8, b, __io_br(), __io_ar())
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-__io_reads_ins(reads, u16, w, __io_br(), __io_ar())
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-__io_reads_ins(reads, u32, l, __io_br(), __io_ar())
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+__io_reads_ins(reads,  u8, b, __io_br(), __io_ar(addr))
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+__io_reads_ins(reads, u16, w, __io_br(), __io_ar(addr))
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+__io_reads_ins(reads, u32, l, __io_br(), __io_ar(addr))
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 #define readsb(addr, buffer, count) __readsb(addr, buffer, count)
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 #define readsw(addr, buffer, count) __readsw(addr, buffer, count)
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 #define readsl(addr, buffer, count) __readsl(addr, buffer, count)
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-__io_reads_ins(ins,  u8, b, __io_pbr(), __io_par())
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-__io_reads_ins(ins, u16, w, __io_pbr(), __io_par())
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-__io_reads_ins(ins, u32, l, __io_pbr(), __io_par())
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-#define insb(addr, buffer, count) __insb((void __iomem *)(long)addr, buffer, count)
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-#define insw(addr, buffer, count) __insw((void __iomem *)(long)addr, buffer, count)
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-#define insl(addr, buffer, count) __insl((void __iomem *)(long)addr, buffer, count)
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+__io_reads_ins(ins,  u8, b, __io_pbr(), __io_par(addr))
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+__io_reads_ins(ins, u16, w, __io_pbr(), __io_par(addr))
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+__io_reads_ins(ins, u32, l, __io_pbr(), __io_par(addr))
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+#define insb(addr, buffer, count) __insb(PCI_IOBASE + (addr), buffer, count)
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+#define insw(addr, buffer, count) __insw(PCI_IOBASE + (addr), buffer, count)
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+#define insl(addr, buffer, count) __insl(PCI_IOBASE + (addr), buffer, count)
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 __io_writes_outs(writes,  u8, b, __io_bw(), __io_aw())
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 __io_writes_outs(writes, u16, w, __io_bw(), __io_aw())
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@@ -278,22 +128,22 @@
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 __io_writes_outs(outs,  u8, b, __io_pbw(), __io_paw())
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 __io_writes_outs(outs, u16, w, __io_pbw(), __io_paw())
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 __io_writes_outs(outs, u32, l, __io_pbw(), __io_paw())
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-#define outsb(addr, buffer, count) __outsb((void __iomem *)(long)addr, buffer, count)
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-#define outsw(addr, buffer, count) __outsw((void __iomem *)(long)addr, buffer, count)
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-#define outsl(addr, buffer, count) __outsl((void __iomem *)(long)addr, buffer, count)
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+#define outsb(addr, buffer, count) __outsb(PCI_IOBASE + (addr), buffer, count)
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+#define outsw(addr, buffer, count) __outsw(PCI_IOBASE + (addr), buffer, count)
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+#define outsl(addr, buffer, count) __outsl(PCI_IOBASE + (addr), buffer, count)
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134
 
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 #ifdef CONFIG_64BIT
286
-__io_reads_ins(reads, u64, q, __io_br(), __io_ar())
136
+__io_reads_ins(reads, u64, q, __io_br(), __io_ar(addr))
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 #define readsq(addr, buffer, count) __readsq(addr, buffer, count)
288
138
 
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-__io_reads_ins(ins, u64, q, __io_pbr(), __io_par())
290
-#define insq(addr, buffer, count) __insq((void __iomem *)addr, buffer, count)
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+__io_reads_ins(ins, u64, q, __io_pbr(), __io_par(addr))
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+#define insq(addr, buffer, count) __insq(PCI_IOBASE + (addr), buffer, count)
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141
 
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 __io_writes_outs(writes, u64, q, __io_bw(), __io_aw())
293
143
 #define writesq(addr, buffer, count) __writesq(addr, buffer, count)
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144
 
295
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 __io_writes_outs(outs, u64, q, __io_pbr(), __io_paw())
296
-#define outsq(addr, buffer, count) __outsq((void __iomem *)addr, buffer, count)
146
+#define outsq(addr, buffer, count) __outsq(PCI_IOBASE + (addr), buffer, count)
297
147
 #endif
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148
 
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 #include <asm-generic/io.h>