add ax88772_rst

hc

2024-05-10 9999e48639b3cecb08ffb37358bcba3b48161b29

 kernel/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi
..
..
@@ -90,84 +90,84 @@
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 		cpu0: PowerPC,e6500@0 {
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 			device_type = "cpu";
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 			reg = <0 1>;
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-			clocks = <&mux0>;
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+			clocks = <&clockgen 1 0>;
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 			next-level-cache = <&L2_1>;
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 			fsl,portid-mapping = <0x80000000>;
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 		};
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 		cpu1: PowerPC,e6500@2 {
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 			device_type = "cpu";
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 			reg = <2 3>;
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-			clocks = <&mux0>;
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+			clocks = <&clockgen 1 0>;
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 			next-level-cache = <&L2_1>;
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 			fsl,portid-mapping = <0x80000000>;
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 		};
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 		cpu2: PowerPC,e6500@4 {
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 			device_type = "cpu";
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 			reg = <4 5>;
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-			clocks = <&mux0>;
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+			clocks = <&clockgen 1 0>;
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 			next-level-cache = <&L2_1>;
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 			fsl,portid-mapping = <0x80000000>;
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 		};
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 		cpu3: PowerPC,e6500@6 {
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 			device_type = "cpu";
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 			reg = <6 7>;
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-			clocks = <&mux0>;
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+			clocks = <&clockgen 1 0>;
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 			next-level-cache = <&L2_1>;
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 			fsl,portid-mapping = <0x80000000>;
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 		};
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 		cpu4: PowerPC,e6500@8 {
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 			device_type = "cpu";
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 			reg = <8 9>;
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-			clocks = <&mux1>;
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+			clocks = <&clockgen 1 1>;
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 			next-level-cache = <&L2_2>;
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 			fsl,portid-mapping = <0x40000000>;
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 		};
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 		cpu5: PowerPC,e6500@10 {
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 			device_type = "cpu";
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 			reg = <10 11>;
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-			clocks = <&mux1>;
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+			clocks = <&clockgen 1 1>;
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 			next-level-cache = <&L2_2>;
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 			fsl,portid-mapping = <0x40000000>;
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 		};
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 		cpu6: PowerPC,e6500@12 {
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 			device_type = "cpu";
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 			reg = <12 13>;
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-			clocks = <&mux1>;
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+			clocks = <&clockgen 1 1>;
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 			next-level-cache = <&L2_2>;
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 			fsl,portid-mapping = <0x40000000>;
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 		};
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 		cpu7: PowerPC,e6500@14 {
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 			device_type = "cpu";
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 			reg = <14 15>;
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-			clocks = <&mux1>;
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+			clocks = <&clockgen 1 1>;
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 			next-level-cache = <&L2_2>;
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 			fsl,portid-mapping = <0x40000000>;
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 		};
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 		cpu8: PowerPC,e6500@16 {
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 			device_type = "cpu";
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 			reg = <16 17>;
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-			clocks = <&mux2>;
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+			clocks = <&clockgen 1 2>;
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 			next-level-cache = <&L2_3>;
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 			fsl,portid-mapping = <0x20000000>;
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 		};
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 		cpu9: PowerPC,e6500@18 {
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 			device_type = "cpu";
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 			reg = <18 19>;
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-			clocks = <&mux2>;
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+			clocks = <&clockgen 1 2>;
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 			next-level-cache = <&L2_3>;
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 			fsl,portid-mapping = <0x20000000>;
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 		};
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 		cpu10: PowerPC,e6500@20 {
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 			device_type = "cpu";
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 			reg = <20 21>;
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-			clocks = <&mux2>;
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+			clocks = <&clockgen 1 2>;
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 			next-level-cache = <&L2_3>;
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 			fsl,portid-mapping = <0x20000000>;
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 		};
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 		cpu11: PowerPC,e6500@22 {
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 			device_type = "cpu";
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 			reg = <22 23>;
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-			clocks = <&mux2>;
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+			clocks = <&clockgen 1 2>;
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 			next-level-cache = <&L2_3>;
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 			fsl,portid-mapping = <0x20000000>;
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 		};