forked from ~ljy/RK356X_SDK_RELEASE

hc
2024-05-10 9999e48639b3cecb08ffb37358bcba3b48161b29
kernel/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
....@@ -374,76 +374,6 @@
374374 /include/ "qoriq-clockgen1.dtsi"
375375 global-utilities@e1000 {
376376 compatible = "fsl,p4080-clockgen", "fsl,qoriq-clockgen-1.0";
377
-
378
- pll2: pll2@840 {
379
- #clock-cells = <1>;
380
- reg = <0x840 0x4>;
381
- compatible = "fsl,qoriq-core-pll-1.0";
382
- clocks = <&sysclk>;
383
- clock-output-names = "pll2", "pll2-div2";
384
- };
385
-
386
- pll3: pll3@860 {
387
- #clock-cells = <1>;
388
- reg = <0x860 0x4>;
389
- compatible = "fsl,qoriq-core-pll-1.0";
390
- clocks = <&sysclk>;
391
- clock-output-names = "pll3", "pll3-div2";
392
- };
393
-
394
- mux2: mux2@40 {
395
- #clock-cells = <0>;
396
- reg = <0x40 0x4>;
397
- compatible = "fsl,qoriq-core-mux-1.0";
398
- clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
399
- clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
400
- clock-output-names = "cmux2";
401
- };
402
-
403
- mux3: mux3@60 {
404
- #clock-cells = <0>;
405
- reg = <0x60 0x4>;
406
- compatible = "fsl,qoriq-core-mux-1.0";
407
- clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
408
- clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
409
- clock-output-names = "cmux3";
410
- };
411
-
412
- mux4: mux4@80 {
413
- #clock-cells = <0>;
414
- reg = <0x80 0x4>;
415
- compatible = "fsl,qoriq-core-mux-1.0";
416
- clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>;
417
- clock-names = "pll2", "pll2-div2", "pll3", "pll3-div2";
418
- clock-output-names = "cmux4";
419
- };
420
-
421
- mux5: mux5@a0 {
422
- #clock-cells = <0>;
423
- reg = <0xa0 0x4>;
424
- compatible = "fsl,qoriq-core-mux-1.0";
425
- clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>;
426
- clock-names = "pll2", "pll2-div2", "pll3", "pll3-div2";
427
- clock-output-names = "cmux5";
428
- };
429
-
430
- mux6: mux6@c0 {
431
- #clock-cells = <0>;
432
- reg = <0xc0 0x4>;
433
- compatible = "fsl,qoriq-core-mux-1.0";
434
- clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>;
435
- clock-names = "pll2", "pll2-div2", "pll3", "pll3-div2";
436
- clock-output-names = "cmux6";
437
- };
438
-
439
- mux7: mux7@e0 {
440
- #clock-cells = <0>;
441
- reg = <0xe0 0x4>;
442
- compatible = "fsl,qoriq-core-mux-1.0";
443
- clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>;
444
- clock-names = "pll2", "pll2-div2", "pll3", "pll3-div2";
445
- clock-output-names = "cmux7";
446
- };
447377 };
448378
449379 rcpm: global-utilities@e2000 {