add ax88772_rst

hc

2024-05-10 9999e48639b3cecb08ffb37358bcba3b48161b29

 kernel/arch/mips/include/asm/tlb.h
..
..
@@ -5,23 +5,6 @@
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 #include <asm/cpu-features.h>
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 #include <asm/mipsregs.h>
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-/*
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- * MIPS doesn't need any special per-pte or per-vma handling, except
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- * we need to flush cache for area to be unmapped.
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- */
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-#define tlb_start_vma(tlb, vma)					\
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-	do {							\
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-		if (!tlb->fullmm)				\
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-			flush_cache_range(vma, vma->vm_start, vma->vm_end); \
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-	}  while (0)
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-#define tlb_end_vma(tlb, vma) do { } while (0)
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-#define __tlb_remove_tlb_entry(tlb, ptep, address) do { } while (0)
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-
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-/*
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- * .. because we flush the whole mm when it fills up.
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- */
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-#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm)
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-
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 #define _UNIQUE_ENTRYHI(base, idx)					\
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 		(((base) + ((idx) << (PAGE_SHIFT + 1))) |		\
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 		 (cpu_has_tlbinv ? MIPS_ENTRYHI_EHINV : 0))