add ax88772_rst

hc

2024-05-10 9999e48639b3cecb08ffb37358bcba3b48161b29

 kernel/arch/mips/include/asm/timex.h
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@@ -40,9 +40,9 @@
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 typedef unsigned int cycles_t;
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 /*
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- * On R4000/R4400 before version 5.0 an erratum exists such that if the
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- * cycle counter is read in the exact moment that it is matching the
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- * compare register, no interrupt will be generated.
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+ * On R4000/R4400 an erratum exists such that if the cycle counter is
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+ * read in the exact moment that it is matching the compare register,
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+ * no interrupt will be generated.
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  *
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  * There is a suggested workaround and also the erratum can't strike if
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  * the compare interrupt isn't being used as the clock source device.
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@@ -63,7 +63,7 @@
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 	if (!__builtin_constant_p(cpu_has_counter))
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 		asm volatile("" : "=m" (cpu_data[0].options));
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 	if (likely(cpu_has_counter &&
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-		   prid >= (PRID_IMP_R4000 | PRID_REV_ENCODE_44(5, 0))))
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+		   prid > (PRID_IMP_R4000 | PRID_REV_ENCODE_44(15, 15))))
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 		return 1;
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 	else
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 		return 0;
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@@ -76,25 +76,24 @@
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 	else
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 		return 0;	/* no usable counter */
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 }
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+#define get_cycles get_cycles
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 /*
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  * Like get_cycles - but where c0_count is not available we desperately
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  * use c0_random in an attempt to get at least a little bit of entropy.
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- *
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- * R6000 and R6000A neither have a count register nor a random register.
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- * That leaves no entropy source in the CPU itself.
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  */
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 static inline unsigned long random_get_entropy(void)
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 {
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-	unsigned int prid = read_c0_prid();
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-	unsigned int imp = prid & PRID_IMP_MASK;
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+	unsigned int c0_random;
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-	if (can_use_mips_counter(prid))
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+	if (can_use_mips_counter(read_c0_prid()))
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 		return read_c0_count();
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-	else if (likely(imp != PRID_IMP_R6000 && imp != PRID_IMP_R6000A))
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-		return read_c0_random();
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+
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+	if (cpu_has_3kex)
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+		c0_random = (read_c0_random() >> 8) & 0x3f;
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 	else
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-		return 0;	/* no usable register */
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+		c0_random = read_c0_random() & 0x3f;
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+	return (random_get_entropy_fallback() << 6) | (0x3f - c0_random);
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 }
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 #define random_get_entropy random_get_entropy
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