.. | .. |
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3 | 3 | * Copyright (C) 1999, 2000 Ralf Baechle |
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4 | 4 | * Copyright (C) 1999, 2000 Silicon Graphics, Inc. |
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5 | 5 | */ |
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6 | | -#ifndef _IOC3_H |
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7 | | -#define _IOC3_H |
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| 6 | +#ifndef MIPS_SN_IOC3_H |
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| 7 | +#define MIPS_SN_IOC3_H |
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8 | 8 | |
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9 | 9 | #include <linux/types.h> |
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10 | 10 | |
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11 | | -/* SUPERIO uart register map */ |
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12 | | -typedef volatile struct ioc3_uartregs { |
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13 | | - union { |
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14 | | - volatile u8 rbr; /* read only, DLAB == 0 */ |
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15 | | - volatile u8 thr; /* write only, DLAB == 0 */ |
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16 | | - volatile u8 dll; /* DLAB == 1 */ |
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17 | | - } u1; |
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18 | | - union { |
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19 | | - volatile u8 ier; /* DLAB == 0 */ |
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20 | | - volatile u8 dlm; /* DLAB == 1 */ |
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21 | | - } u2; |
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22 | | - union { |
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23 | | - volatile u8 iir; /* read only */ |
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24 | | - volatile u8 fcr; /* write only */ |
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25 | | - } u3; |
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26 | | - volatile u8 iu_lcr; |
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27 | | - volatile u8 iu_mcr; |
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28 | | - volatile u8 iu_lsr; |
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29 | | - volatile u8 iu_msr; |
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30 | | - volatile u8 iu_scr; |
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31 | | -} ioc3_uregs_t; |
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| 11 | +/* serial port register map */ |
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| 12 | +struct ioc3_serialregs { |
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| 13 | + u32 sscr; |
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| 14 | + u32 stpir; |
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| 15 | + u32 stcir; |
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| 16 | + u32 srpir; |
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| 17 | + u32 srcir; |
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| 18 | + u32 srtr; |
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| 19 | + u32 shadow; |
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| 20 | +}; |
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32 | 21 | |
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33 | | -#define iu_rbr u1.rbr |
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34 | | -#define iu_thr u1.thr |
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35 | | -#define iu_dll u1.dll |
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36 | | -#define iu_ier u2.ier |
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37 | | -#define iu_dlm u2.dlm |
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38 | | -#define iu_iir u3.iir |
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39 | | -#define iu_fcr u3.fcr |
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| 22 | +/* SUPERIO uart register map */ |
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| 23 | +struct ioc3_uartregs { |
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| 24 | + u8 iu_lcr; |
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| 25 | + union { |
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| 26 | + u8 iu_iir; /* read only */ |
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| 27 | + u8 iu_fcr; /* write only */ |
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| 28 | + }; |
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| 29 | + union { |
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| 30 | + u8 iu_ier; /* DLAB == 0 */ |
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| 31 | + u8 iu_dlm; /* DLAB == 1 */ |
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| 32 | + }; |
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| 33 | + union { |
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| 34 | + u8 iu_rbr; /* read only, DLAB == 0 */ |
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| 35 | + u8 iu_thr; /* write only, DLAB == 0 */ |
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| 36 | + u8 iu_dll; /* DLAB == 1 */ |
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| 37 | + }; |
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| 38 | + u8 iu_scr; |
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| 39 | + u8 iu_msr; |
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| 40 | + u8 iu_lsr; |
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| 41 | + u8 iu_mcr; |
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| 42 | +}; |
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40 | 43 | |
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41 | 44 | struct ioc3_sioregs { |
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42 | | - volatile u8 fill[0x141]; /* starts at 0x141 */ |
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| 45 | + u8 fill[0x141]; /* starts at 0x141 */ |
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43 | 46 | |
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44 | | - volatile u8 uartc; |
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45 | | - volatile u8 kbdcg; |
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| 47 | + u8 kbdcg; |
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| 48 | + u8 uartc; |
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46 | 49 | |
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47 | | - volatile u8 fill0[0x150 - 0x142 - 1]; |
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| 50 | + u8 fill0[0x151 - 0x142 - 1]; |
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48 | 51 | |
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49 | | - volatile u8 pp_data; |
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50 | | - volatile u8 pp_dsr; |
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51 | | - volatile u8 pp_dcr; |
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| 52 | + u8 pp_dcr; |
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| 53 | + u8 pp_dsr; |
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| 54 | + u8 pp_data; |
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52 | 55 | |
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53 | | - volatile u8 fill1[0x158 - 0x152 - 1]; |
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| 56 | + u8 fill1[0x159 - 0x153 - 1]; |
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54 | 57 | |
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55 | | - volatile u8 pp_fifa; |
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56 | | - volatile u8 pp_cfgb; |
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57 | | - volatile u8 pp_ecr; |
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| 58 | + u8 pp_ecr; |
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| 59 | + u8 pp_cfgb; |
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| 60 | + u8 pp_fifa; |
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58 | 61 | |
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59 | | - volatile u8 fill2[0x168 - 0x15a - 1]; |
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| 62 | + u8 fill2[0x16a - 0x15b - 1]; |
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60 | 63 | |
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61 | | - volatile u8 rtcad; |
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62 | | - volatile u8 rtcdat; |
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| 64 | + u8 rtcdat; |
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| 65 | + u8 rtcad; |
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63 | 66 | |
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64 | | - volatile u8 fill3[0x170 - 0x169 - 1]; |
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| 67 | + u8 fill3[0x170 - 0x16b - 1]; |
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65 | 68 | |
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66 | 69 | struct ioc3_uartregs uartb; /* 0x20170 */ |
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67 | 70 | struct ioc3_uartregs uarta; /* 0x20178 */ |
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68 | 71 | }; |
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69 | 72 | |
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| 73 | +struct ioc3_ethregs { |
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| 74 | + u32 emcr; /* 0x000f0 */ |
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| 75 | + u32 eisr; /* 0x000f4 */ |
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| 76 | + u32 eier; /* 0x000f8 */ |
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| 77 | + u32 ercsr; /* 0x000fc */ |
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| 78 | + u32 erbr_h; /* 0x00100 */ |
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| 79 | + u32 erbr_l; /* 0x00104 */ |
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| 80 | + u32 erbar; /* 0x00108 */ |
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| 81 | + u32 ercir; /* 0x0010c */ |
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| 82 | + u32 erpir; /* 0x00110 */ |
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| 83 | + u32 ertr; /* 0x00114 */ |
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| 84 | + u32 etcsr; /* 0x00118 */ |
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| 85 | + u32 ersr; /* 0x0011c */ |
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| 86 | + u32 etcdc; /* 0x00120 */ |
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| 87 | + u32 ebir; /* 0x00124 */ |
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| 88 | + u32 etbr_h; /* 0x00128 */ |
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| 89 | + u32 etbr_l; /* 0x0012c */ |
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| 90 | + u32 etcir; /* 0x00130 */ |
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| 91 | + u32 etpir; /* 0x00134 */ |
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| 92 | + u32 emar_h; /* 0x00138 */ |
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| 93 | + u32 emar_l; /* 0x0013c */ |
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| 94 | + u32 ehar_h; /* 0x00140 */ |
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| 95 | + u32 ehar_l; /* 0x00144 */ |
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| 96 | + u32 micr; /* 0x00148 */ |
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| 97 | + u32 midr_r; /* 0x0014c */ |
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| 98 | + u32 midr_w; /* 0x00150 */ |
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| 99 | +}; |
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| 100 | + |
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| 101 | +struct ioc3_serioregs { |
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| 102 | + u32 km_csr; /* 0x0009c */ |
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| 103 | + u32 k_rd; /* 0x000a0 */ |
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| 104 | + u32 m_rd; /* 0x000a4 */ |
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| 105 | + u32 k_wd; /* 0x000a8 */ |
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| 106 | + u32 m_wd; /* 0x000ac */ |
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| 107 | +}; |
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| 108 | + |
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70 | 109 | /* Register layout of IOC3 in configuration space. */ |
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71 | 110 | struct ioc3 { |
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72 | | - volatile u32 pad0[7]; /* 0x00000 */ |
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73 | | - volatile u32 sio_ir; /* 0x0001c */ |
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74 | | - volatile u32 sio_ies; /* 0x00020 */ |
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75 | | - volatile u32 sio_iec; /* 0x00024 */ |
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76 | | - volatile u32 sio_cr; /* 0x00028 */ |
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77 | | - volatile u32 int_out; /* 0x0002c */ |
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78 | | - volatile u32 mcr; /* 0x00030 */ |
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| 111 | + /* PCI Config Space registers */ |
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| 112 | + u32 pci_id; /* 0x00000 */ |
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| 113 | + u32 pci_scr; /* 0x00004 */ |
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| 114 | + u32 pci_rev; /* 0x00008 */ |
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| 115 | + u32 pci_lat; /* 0x0000c */ |
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| 116 | + u32 pci_addr; /* 0x00010 */ |
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| 117 | + u32 pci_err_addr_l; /* 0x00014 */ |
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| 118 | + u32 pci_err_addr_h; /* 0x00018 */ |
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| 119 | + |
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| 120 | + u32 sio_ir; /* 0x0001c */ |
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| 121 | + u32 sio_ies; /* 0x00020 */ |
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| 122 | + u32 sio_iec; /* 0x00024 */ |
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| 123 | + u32 sio_cr; /* 0x00028 */ |
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| 124 | + u32 int_out; /* 0x0002c */ |
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| 125 | + u32 mcr; /* 0x00030 */ |
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79 | 126 | |
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80 | 127 | /* General Purpose I/O registers */ |
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81 | | - volatile u32 gpcr_s; /* 0x00034 */ |
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82 | | - volatile u32 gpcr_c; /* 0x00038 */ |
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83 | | - volatile u32 gpdr; /* 0x0003c */ |
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84 | | - volatile u32 gppr_0; /* 0x00040 */ |
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85 | | - volatile u32 gppr_1; /* 0x00044 */ |
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86 | | - volatile u32 gppr_2; /* 0x00048 */ |
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87 | | - volatile u32 gppr_3; /* 0x0004c */ |
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88 | | - volatile u32 gppr_4; /* 0x00050 */ |
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89 | | - volatile u32 gppr_5; /* 0x00054 */ |
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90 | | - volatile u32 gppr_6; /* 0x00058 */ |
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91 | | - volatile u32 gppr_7; /* 0x0005c */ |
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92 | | - volatile u32 gppr_8; /* 0x00060 */ |
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93 | | - volatile u32 gppr_9; /* 0x00064 */ |
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94 | | - volatile u32 gppr_10; /* 0x00068 */ |
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95 | | - volatile u32 gppr_11; /* 0x0006c */ |
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96 | | - volatile u32 gppr_12; /* 0x00070 */ |
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97 | | - volatile u32 gppr_13; /* 0x00074 */ |
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98 | | - volatile u32 gppr_14; /* 0x00078 */ |
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99 | | - volatile u32 gppr_15; /* 0x0007c */ |
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| 128 | + u32 gpcr_s; /* 0x00034 */ |
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| 129 | + u32 gpcr_c; /* 0x00038 */ |
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| 130 | + u32 gpdr; /* 0x0003c */ |
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| 131 | + u32 gppr[16]; /* 0x00040 */ |
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100 | 132 | |
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101 | 133 | /* Parallel Port Registers */ |
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102 | | - volatile u32 ppbr_h_a; /* 0x00080 */ |
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103 | | - volatile u32 ppbr_l_a; /* 0x00084 */ |
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104 | | - volatile u32 ppcr_a; /* 0x00088 */ |
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105 | | - volatile u32 ppcr; /* 0x0008c */ |
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106 | | - volatile u32 ppbr_h_b; /* 0x00090 */ |
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107 | | - volatile u32 ppbr_l_b; /* 0x00094 */ |
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108 | | - volatile u32 ppcr_b; /* 0x00098 */ |
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| 134 | + u32 ppbr_h_a; /* 0x00080 */ |
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| 135 | + u32 ppbr_l_a; /* 0x00084 */ |
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| 136 | + u32 ppcr_a; /* 0x00088 */ |
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| 137 | + u32 ppcr; /* 0x0008c */ |
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| 138 | + u32 ppbr_h_b; /* 0x00090 */ |
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| 139 | + u32 ppbr_l_b; /* 0x00094 */ |
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| 140 | + u32 ppcr_b; /* 0x00098 */ |
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109 | 141 | |
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110 | 142 | /* Keyboard and Mouse Registers */ |
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111 | | - volatile u32 km_csr; /* 0x0009c */ |
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112 | | - volatile u32 k_rd; /* 0x000a0 */ |
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113 | | - volatile u32 m_rd; /* 0x000a4 */ |
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114 | | - volatile u32 k_wd; /* 0x000a8 */ |
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115 | | - volatile u32 m_wd; /* 0x000ac */ |
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| 143 | + struct ioc3_serioregs serio; |
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116 | 144 | |
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117 | 145 | /* Serial Port Registers */ |
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118 | | - volatile u32 sbbr_h; /* 0x000b0 */ |
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119 | | - volatile u32 sbbr_l; /* 0x000b4 */ |
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120 | | - volatile u32 sscr_a; /* 0x000b8 */ |
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121 | | - volatile u32 stpir_a; /* 0x000bc */ |
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122 | | - volatile u32 stcir_a; /* 0x000c0 */ |
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123 | | - volatile u32 srpir_a; /* 0x000c4 */ |
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124 | | - volatile u32 srcir_a; /* 0x000c8 */ |
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125 | | - volatile u32 srtr_a; /* 0x000cc */ |
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126 | | - volatile u32 shadow_a; /* 0x000d0 */ |
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127 | | - volatile u32 sscr_b; /* 0x000d4 */ |
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128 | | - volatile u32 stpir_b; /* 0x000d8 */ |
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129 | | - volatile u32 stcir_b; /* 0x000dc */ |
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130 | | - volatile u32 srpir_b; /* 0x000e0 */ |
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131 | | - volatile u32 srcir_b; /* 0x000e4 */ |
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132 | | - volatile u32 srtr_b; /* 0x000e8 */ |
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133 | | - volatile u32 shadow_b; /* 0x000ec */ |
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| 146 | + u32 sbbr_h; /* 0x000b0 */ |
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| 147 | + u32 sbbr_l; /* 0x000b4 */ |
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| 148 | + struct ioc3_serialregs port_a; |
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| 149 | + struct ioc3_serialregs port_b; |
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134 | 150 | |
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135 | | - /* Ethernet Registers */ |
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136 | | - volatile u32 emcr; /* 0x000f0 */ |
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137 | | - volatile u32 eisr; /* 0x000f4 */ |
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138 | | - volatile u32 eier; /* 0x000f8 */ |
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139 | | - volatile u32 ercsr; /* 0x000fc */ |
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140 | | - volatile u32 erbr_h; /* 0x00100 */ |
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141 | | - volatile u32 erbr_l; /* 0x00104 */ |
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142 | | - volatile u32 erbar; /* 0x00108 */ |
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143 | | - volatile u32 ercir; /* 0x0010c */ |
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144 | | - volatile u32 erpir; /* 0x00110 */ |
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145 | | - volatile u32 ertr; /* 0x00114 */ |
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146 | | - volatile u32 etcsr; /* 0x00118 */ |
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147 | | - volatile u32 ersr; /* 0x0011c */ |
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148 | | - volatile u32 etcdc; /* 0x00120 */ |
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149 | | - volatile u32 ebir; /* 0x00124 */ |
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150 | | - volatile u32 etbr_h; /* 0x00128 */ |
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151 | | - volatile u32 etbr_l; /* 0x0012c */ |
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152 | | - volatile u32 etcir; /* 0x00130 */ |
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153 | | - volatile u32 etpir; /* 0x00134 */ |
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154 | | - volatile u32 emar_h; /* 0x00138 */ |
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155 | | - volatile u32 emar_l; /* 0x0013c */ |
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156 | | - volatile u32 ehar_h; /* 0x00140 */ |
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157 | | - volatile u32 ehar_l; /* 0x00144 */ |
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158 | | - volatile u32 micr; /* 0x00148 */ |
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159 | | - volatile u32 midr_r; /* 0x0014c */ |
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160 | | - volatile u32 midr_w; /* 0x00150 */ |
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161 | | - volatile u32 pad1[(0x20000 - 0x00154) / 4]; |
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| 151 | + /* Ethernet Registers */ |
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| 152 | + struct ioc3_ethregs eth; |
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| 153 | + u32 pad1[(0x20000 - 0x00154) / 4]; |
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162 | 154 | |
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163 | 155 | /* SuperIO Registers XXX */ |
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164 | 156 | struct ioc3_sioregs sregs; /* 0x20000 */ |
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165 | | - volatile u32 pad2[(0x40000 - 0x20180) / 4]; |
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| 157 | + u32 pad2[(0x40000 - 0x20180) / 4]; |
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166 | 158 | |
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167 | 159 | /* SSRAM Diagnostic Access */ |
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168 | | - volatile u32 ssram[(0x80000 - 0x40000) / 4]; |
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| 160 | + u32 ssram[(0x80000 - 0x40000) / 4]; |
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169 | 161 | |
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170 | 162 | /* Bytebus device offsets |
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171 | 163 | 0x80000 - Access to the generic devices selected with DEV0 |
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.. | .. |
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177 | 169 | 0xE0000 - Access to the generic devices selected with DEV3 |
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178 | 170 | 0xFFFFF bytebus DEV_SEL_3 */ |
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179 | 171 | }; |
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| 172 | + |
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| 173 | + |
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| 174 | +#define PCI_LAT 0xc /* Latency Timer */ |
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| 175 | +#define PCI_SCR_DROP_MODE_EN 0x00008000 /* drop pios on parity err */ |
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| 176 | +#define UARTA_BASE 0x178 |
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| 177 | +#define UARTB_BASE 0x170 |
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| 178 | + |
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| 179 | +/* |
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| 180 | + * Bytebus device space |
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| 181 | + */ |
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| 182 | +#define IOC3_BYTEBUS_DEV0 0x80000L |
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| 183 | +#define IOC3_BYTEBUS_DEV1 0xa0000L |
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| 184 | +#define IOC3_BYTEBUS_DEV2 0xc0000L |
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| 185 | +#define IOC3_BYTEBUS_DEV3 0xe0000L |
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180 | 186 | |
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181 | 187 | /* |
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182 | 188 | * Ethernet RX Buffer |
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.. | .. |
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233 | 239 | #define ETXD_B2CNT_MASK 0x7ff00000 |
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234 | 240 | #define ETXD_B2CNT_SHIFT 20 |
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235 | 241 | |
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236 | | -/* |
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237 | | - * Bytebus device space |
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238 | | - */ |
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239 | | -#define IOC3_BYTEBUS_DEV0 0x80000L |
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240 | | -#define IOC3_BYTEBUS_DEV1 0xa0000L |
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241 | | -#define IOC3_BYTEBUS_DEV2 0xc0000L |
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242 | | -#define IOC3_BYTEBUS_DEV3 0xe0000L |
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243 | | - |
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244 | 242 | /* ------------------------------------------------------------------------- */ |
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245 | 243 | |
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246 | 244 | /* Superio Registers (PIO Access) */ |
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247 | 245 | #define IOC3_SIO_BASE 0x20000 |
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248 | 246 | #define IOC3_SIO_UARTC (IOC3_SIO_BASE+0x141) /* UART Config */ |
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249 | 247 | #define IOC3_SIO_KBDCG (IOC3_SIO_BASE+0x142) /* KBD Config */ |
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250 | | -#define IOC3_SIO_PP_BASE (IOC3_SIO_BASE+PP_BASE) /* Parallel Port */ |
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| 248 | +#define IOC3_SIO_PP_BASE (IOC3_SIO_BASE+PP_BASE) /* Parallel Port */ |
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251 | 249 | #define IOC3_SIO_RTC_BASE (IOC3_SIO_BASE+0x168) /* Real Time Clock */ |
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252 | 250 | #define IOC3_SIO_UB_BASE (IOC3_SIO_BASE+UARTB_BASE) /* UART B */ |
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253 | 251 | #define IOC3_SIO_UA_BASE (IOC3_SIO_BASE+UARTA_BASE) /* UART A */ |
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254 | 252 | |
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255 | 253 | /* SSRAM Diagnostic Access */ |
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256 | 254 | #define IOC3_SSRAM IOC3_RAM_OFF /* base of SSRAM diagnostic access */ |
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257 | | -#define IOC3_SSRAM_LEN 0x40000 /* 256kb (address space size, may not be fully populated) */ |
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| 255 | +#define IOC3_SSRAM_LEN 0x40000 /* 256kb (addrspc sz, may not be populated) */ |
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258 | 256 | #define IOC3_SSRAM_DM 0x0000ffff /* data mask */ |
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259 | 257 | #define IOC3_SSRAM_PM 0x00010000 /* parity mask */ |
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260 | 258 | |
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.. | .. |
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294 | 292 | SIO_IR to assert */ |
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295 | 293 | #define KM_CSR_M_TO_EN 0x00080000 /* KM_CSR_M_TO + KM_CSR_M_TO_EN = cause |
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296 | 294 | SIO_IR to assert */ |
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297 | | -#define KM_CSR_K_CLAMP_ONE 0x00100000 /* Pull K_CLK low after rec. one char */ |
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298 | | -#define KM_CSR_M_CLAMP_ONE 0x00200000 /* Pull M_CLK low after rec. one char */ |
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299 | | -#define KM_CSR_K_CLAMP_THREE 0x00400000 /* Pull K_CLK low after rec. three chars */ |
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300 | | -#define KM_CSR_M_CLAMP_THREE 0x00800000 /* Pull M_CLK low after rec. three char */ |
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| 295 | +#define KM_CSR_K_CLAMP_1 0x00100000 /* Pull K_CLK low aft recv 1 char */ |
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| 296 | +#define KM_CSR_M_CLAMP_1 0x00200000 /* Pull M_CLK low aft recv 1 char */ |
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| 297 | +#define KM_CSR_K_CLAMP_3 0x00400000 /* Pull K_CLK low aft recv 3 chars */ |
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| 298 | +#define KM_CSR_M_CLAMP_3 0x00800000 /* Pull M_CLK low aft recv 3 chars */ |
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301 | 299 | |
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302 | 300 | /* bitmasks for IOC3_K_RD and IOC3_M_RD */ |
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303 | 301 | #define KM_RD_DATA_2 0x000000ff /* 3rd char recvd since last read */ |
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.. | .. |
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440 | 438 | SIO_IR_PP_INTB | SIO_IR_PP_MEMERR) |
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441 | 439 | #define SIO_IR_RT (SIO_IR_RT_INT | SIO_IR_GEN_INT1) |
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442 | 440 | |
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443 | | -/* macro to load pending interrupts */ |
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444 | | -#define IOC3_PENDING_INTRS(mem) (PCI_INW(&((mem)->sio_ir)) & \ |
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445 | | - PCI_INW(&((mem)->sio_ies_ro))) |
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446 | | - |
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447 | 441 | /* bitmasks for SIO_CR */ |
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448 | 442 | #define SIO_CR_SIO_RESET 0x00000001 /* reset the SIO */ |
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449 | 443 | #define SIO_CR_SER_A_BASE 0x000000fe /* DMA poll addr port A */ |
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.. | .. |
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500 | 494 | #define GPCR_UARTB_MODESEL 0x40 /* pin is output to port B mode sel */ |
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501 | 495 | #define GPCR_UARTA_MODESEL 0x80 /* pin is output to port A mode sel */ |
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502 | 496 | |
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503 | | -#define GPPR_PHY_RESET_PIN 5 /* GIO pin controlling phy reset */ |
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504 | | -#define GPPR_UARTB_MODESEL_PIN 6 /* GIO pin controlling uart b mode select */ |
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505 | | -#define GPPR_UARTA_MODESEL_PIN 7 /* GIO pin controlling uart a mode select */ |
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| 497 | +#define GPPR_PHY_RESET_PIN 5 /* GIO pin cntrlling phy reset */ |
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| 498 | +#define GPPR_UARTB_MODESEL_PIN 6 /* GIO pin cntrlling uart b mode sel */ |
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| 499 | +#define GPPR_UARTA_MODESEL_PIN 7 /* GIO pin cntrlling uart a mode sel */ |
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506 | 500 | |
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| 501 | +/* ethernet */ |
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507 | 502 | #define EMCR_DUPLEX 0x00000001 |
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508 | 503 | #define EMCR_PROMISC 0x00000002 |
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509 | 504 | #define EMCR_PADEN 0x00000004 |
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.. | .. |
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595 | 590 | |
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596 | 591 | #define MIDR_DATA_MASK 0x0000ffff |
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597 | 592 | |
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598 | | -#define ERXBUF_IPCKSUM_MASK 0x0000ffff |
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599 | | -#define ERXBUF_BYTECNT_MASK 0x07ff0000 |
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600 | | -#define ERXBUF_BYTECNT_SHIFT 16 |
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601 | | -#define ERXBUF_V 0x80000000 |
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| 593 | +/* subsystem IDs supplied by card detection in pci-xtalk-bridge */ |
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| 594 | +#define IOC3_SUBSYS_IP27_BASEIO6G 0xc300 |
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| 595 | +#define IOC3_SUBSYS_IP27_MIO 0xc301 |
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| 596 | +#define IOC3_SUBSYS_IP27_BASEIO 0xc302 |
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| 597 | +#define IOC3_SUBSYS_IP29_SYSBOARD 0xc303 |
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| 598 | +#define IOC3_SUBSYS_IP30_SYSBOARD 0xc304 |
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| 599 | +#define IOC3_SUBSYS_MENET 0xc305 |
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| 600 | +#define IOC3_SUBSYS_MENET4 0xc306 |
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| 601 | +#define IOC3_SUBSYS_IO7 0xc307 |
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| 602 | +#define IOC3_SUBSYS_IO8 0xc308 |
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| 603 | +#define IOC3_SUBSYS_IO9 0xc309 |
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| 604 | +#define IOC3_SUBSYS_IP34_SYSBOARD 0xc30A |
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602 | 605 | |
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603 | | -#define ERXBUF_CRCERR 0x00000001 /* aka RSV15 */ |
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604 | | -#define ERXBUF_FRAMERR 0x00000002 /* aka RSV14 */ |
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605 | | -#define ERXBUF_CODERR 0x00000004 /* aka RSV13 */ |
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606 | | -#define ERXBUF_INVPREAMB 0x00000008 /* aka RSV18 */ |
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607 | | -#define ERXBUF_LOLEN 0x00007000 /* aka RSV2_0 */ |
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608 | | -#define ERXBUF_HILEN 0x03ff0000 /* aka RSV12_3 */ |
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609 | | -#define ERXBUF_MULTICAST 0x04000000 /* aka RSV16 */ |
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610 | | -#define ERXBUF_BROADCAST 0x08000000 /* aka RSV17 */ |
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611 | | -#define ERXBUF_LONGEVENT 0x10000000 /* aka RSV19 */ |
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612 | | -#define ERXBUF_BADPKT 0x20000000 /* aka RSV20 */ |
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613 | | -#define ERXBUF_GOODPKT 0x40000000 /* aka RSV21 */ |
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614 | | -#define ERXBUF_CARRIER 0x80000000 /* aka RSV22 */ |
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615 | | - |
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616 | | -#define ETXD_BYTECNT_MASK 0x000007ff /* total byte count */ |
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617 | | -#define ETXD_INTWHENDONE 0x00001000 /* intr when done */ |
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618 | | -#define ETXD_D0V 0x00010000 /* data 0 valid */ |
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619 | | -#define ETXD_B1V 0x00020000 /* buf 1 valid */ |
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620 | | -#define ETXD_B2V 0x00040000 /* buf 2 valid */ |
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621 | | -#define ETXD_DOCHECKSUM 0x00080000 /* insert ip cksum */ |
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622 | | -#define ETXD_CHKOFF_MASK 0x07f00000 /* cksum byte offset */ |
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623 | | -#define ETXD_CHKOFF_SHIFT 20 |
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624 | | - |
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625 | | -#define ETXD_D0CNT_MASK 0x0000007f |
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626 | | -#define ETXD_B1CNT_MASK 0x0007ff00 |
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627 | | -#define ETXD_B1CNT_SHIFT 8 |
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628 | | -#define ETXD_B2CNT_MASK 0x7ff00000 |
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629 | | -#define ETXD_B2CNT_SHIFT 20 |
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630 | | - |
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631 | | -typedef enum ioc3_subdevs_e { |
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632 | | - ioc3_subdev_ether, |
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633 | | - ioc3_subdev_generic, |
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634 | | - ioc3_subdev_nic, |
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635 | | - ioc3_subdev_kbms, |
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636 | | - ioc3_subdev_ttya, |
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637 | | - ioc3_subdev_ttyb, |
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638 | | - ioc3_subdev_ecpp, |
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639 | | - ioc3_subdev_rt, |
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640 | | - ioc3_nsubdevs |
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641 | | -} ioc3_subdev_t; |
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642 | | - |
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643 | | -/* subdevice disable bits, |
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644 | | - * from the standard INFO_LBL_SUBDEVS |
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645 | | - */ |
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646 | | -#define IOC3_SDB_ETHER (1<<ioc3_subdev_ether) |
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647 | | -#define IOC3_SDB_GENERIC (1<<ioc3_subdev_generic) |
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648 | | -#define IOC3_SDB_NIC (1<<ioc3_subdev_nic) |
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649 | | -#define IOC3_SDB_KBMS (1<<ioc3_subdev_kbms) |
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650 | | -#define IOC3_SDB_TTYA (1<<ioc3_subdev_ttya) |
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651 | | -#define IOC3_SDB_TTYB (1<<ioc3_subdev_ttyb) |
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652 | | -#define IOC3_SDB_ECPP (1<<ioc3_subdev_ecpp) |
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653 | | -#define IOC3_SDB_RT (1<<ioc3_subdev_rt) |
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654 | | - |
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655 | | -#define IOC3_ALL_SUBDEVS ((1<<ioc3_nsubdevs)-1) |
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656 | | - |
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657 | | -#define IOC3_SDB_SERIAL (IOC3_SDB_TTYA|IOC3_SDB_TTYB) |
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658 | | - |
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659 | | -#define IOC3_STD_SUBDEVS IOC3_ALL_SUBDEVS |
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660 | | - |
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661 | | -#define IOC3_INTA_SUBDEVS IOC3_SDB_ETHER |
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662 | | -#define IOC3_INTB_SUBDEVS (IOC3_SDB_GENERIC|IOC3_SDB_KBMS|IOC3_SDB_SERIAL|IOC3_SDB_ECPP|IOC3_SDB_RT) |
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663 | | - |
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664 | | -#endif /* _IOC3_H */ |
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| 606 | +#endif /* MIPS_SN_IOC3_H */ |
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