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hc
2024-05-10 9999e48639b3cecb08ffb37358bcba3b48161b29 
 kernel/arch/mips/include/asm/mipsregs.h
....@@ -86,6 +86,7 @@
8686 #define CP0_XCONTEXT $20
8787 #define CP0_FRAMEMASK $21
8888 #define CP0_DIAGNOSTIC $22
89
+#define CP0_DIAGNOSTIC1 $22, 1
8990 #define CP0_DEBUG $23
9091 #define CP0_DEPC $24
9192 #define CP0_PERFORMANCE $25
....@@ -388,6 +389,13 @@
388389 #define ST0_CU3			0x80000000
389390 #define ST0_XX			0x80000000	/* MIPS IV naming */
390391 
392
+/* in-kernel enabled CUs */
393
+#ifdef CONFIG_CPU_LOONGSON64
394
+#define ST0_KERNEL_CUMASK      (ST0_CU0 | ST0_CU2)
395
+#else
396
+#define ST0_KERNEL_CUMASK      ST0_CU0
397
+#endif
398
+
391399 /*
392400  * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2)
393401  */
....@@ -468,9 +476,13 @@
468476 #define EXCCODE_THREAD		25	/* Thread exceptions (MT) */
469477 #define EXCCODE_DSPDIS		26	/* DSP disabled exception */
470478 #define EXCCODE_GE		27	/* Virtualized guest exception (VZ) */
479
+#define EXCCODE_CACHEERR	30	/* Parity/ECC occured on a core */
471480 
472481 /* Implementation specific trap codes used by MIPS cores */
473482 #define MIPS_EXCCODE_TLBPAR	16	/* TLB parity error exception */
483
+
484
+/* Implementation specific trap codes used by Loongson cores */
485
+#define LOONGSON_EXCCODE_GSEXC	16	/* Loongson-specific exception */
474486 
475487 /*
476488  * Bits in the coprocessor 0 config register.
....@@ -563,6 +575,17 @@
563575 #define MIPS_CONF_MT_FTLB	(_ULCAST_(4) <<  7)
564576 #define MIPS_CONF_AR		(_ULCAST_(7) << 10)
565577 #define MIPS_CONF_AT		(_ULCAST_(3) << 13)
578
+#define MIPS_CONF_BE		(_ULCAST_(1) << 15)
579
+#define MIPS_CONF_BM		(_ULCAST_(1) << 16)
580
+#define MIPS_CONF_MM		(_ULCAST_(3) << 17)
581
+#define MIPS_CONF_MM_SYSAD	(_ULCAST_(1) << 17)
582
+#define MIPS_CONF_MM_FULL	(_ULCAST_(2) << 17)
583
+#define MIPS_CONF_SB		(_ULCAST_(1) << 21)
584
+#define MIPS_CONF_UDI		(_ULCAST_(1) << 22)
585
+#define MIPS_CONF_DSP		(_ULCAST_(1) << 23)
586
+#define MIPS_CONF_ISP		(_ULCAST_(1) << 24)
587
+#define MIPS_CONF_KU		(_ULCAST_(3) << 25)
588
+#define MIPS_CONF_K23		(_ULCAST_(3) << 28)
566589 #define MIPS_CONF_M		(_ULCAST_(1) << 31)
567590 
568591 /*
....@@ -667,19 +690,45 @@
667690 #define MIPS_CONF5_FRE		(_ULCAST_(1) << 8)
668691 #define MIPS_CONF5_UFE		(_ULCAST_(1) << 9)
669692 #define MIPS_CONF5_CA2		(_ULCAST_(1) << 14)
693
+#define MIPS_CONF5_MI		(_ULCAST_(1) << 17)
670694 #define MIPS_CONF5_CRCP		(_ULCAST_(1) << 18)
671695 #define MIPS_CONF5_MSAEN	(_ULCAST_(1) << 27)
672696 #define MIPS_CONF5_EVA		(_ULCAST_(1) << 28)
673697 #define MIPS_CONF5_CV		(_ULCAST_(1) << 29)
674698 #define MIPS_CONF5_K		(_ULCAST_(1) << 30)
675699 
676
-#define MIPS_CONF6_SYND		(_ULCAST_(1) << 13)
700
+/* Config6 feature bits for proAptiv/P5600 */
701
+
702
+/* Jump register cache prediction disable */
703
+#define MTI_CONF6_JRCD		(_ULCAST_(1) << 0)
704
+/* MIPSr6 extensions enable */
705
+#define MTI_CONF6_R6		(_ULCAST_(1) << 2)
706
+/* IFU Performance Control */
707
+#define MTI_CONF6_IFUPERFCTL	(_ULCAST_(3) << 10)
708
+#define MTI_CONF6_SYND		(_ULCAST_(1) << 13)
709
+/* Sleep state performance counter disable */
710
+#define MTI_CONF6_SPCD		(_ULCAST_(1) << 14)
677711 /* proAptiv FTLB on/off bit */
678
-#define MIPS_CONF6_FTLBEN	(_ULCAST_(1) << 15)
679
-/* Loongson-3 FTLB on/off bit */
680
-#define MIPS_CONF6_FTLBDIS	(_ULCAST_(1) << 22)
712
+#define MTI_CONF6_FTLBEN	(_ULCAST_(1) << 15)
713
+/* Disable load/store bonding */
714
+#define MTI_CONF6_DLSB		(_ULCAST_(1) << 21)
681715 /* FTLB probability bits */
682
-#define MIPS_CONF6_FTLBP_SHIFT	(16)
716
+#define MTI_CONF6_FTLBP_SHIFT	(16)
717
+
718
+/* Config6 feature bits for Loongson-3 */
719
+
720
+/* Loongson-3 internal timer bit */
721
+#define LOONGSON_CONF6_INTIMER	(_ULCAST_(1) << 6)
722
+/* Loongson-3 external timer bit */
723
+#define LOONGSON_CONF6_EXTIMER	(_ULCAST_(1) << 7)
724
+/* Loongson-3 SFB on/off bit, STFill in manual */
725
+#define LOONGSON_CONF6_SFBEN	(_ULCAST_(1) << 8)
726
+/* Loongson-3's LL on exclusive cacheline */
727
+#define LOONGSON_CONF6_LLEXC	(_ULCAST_(1) << 16)
728
+/* Loongson-3's SC has a random delay */
729
+#define LOONGSON_CONF6_SCRAND	(_ULCAST_(1) << 17)
730
+/* Loongson-3 FTLB on/off bit, VTLBOnly in manual */
731
+#define LOONGSON_CONF6_FTLBDIS	(_ULCAST_(1) << 22)
683732 
684733 #define MIPS_CONF7_WII		(_ULCAST_(1) << 31)
685734 
....@@ -687,6 +736,9 @@
687736 
688737 #define MIPS_CONF7_IAR		(_ULCAST_(1) << 10)
689738 #define MIPS_CONF7_AR		(_ULCAST_(1) << 16)
739
+
740
+/* Ingenic HPTLB off bits */
741
+#define XBURST_PAGECTRL_HPTLB_DIS 0xa9000000
690742 
691743 /* Ingenic Config7 bits */
692744 #define MIPS_CONF7_BTB_LOOP_EN	(_ULCAST_(1) << 4)
....@@ -753,6 +805,14 @@
753805 #define MIPS_MAAR_ADDR_SHIFT	12
754806 #define MIPS_MAAR_S		(_ULCAST_(1) << 1)
755807 #define MIPS_MAAR_VL		(_ULCAST_(1) << 0)
808
+#ifdef CONFIG_XPA
809
+#define MIPS_MAAR_V		(MIPS_MAAR_VH | MIPS_MAAR_VL)
810
+#else
811
+#define MIPS_MAAR_V		MIPS_MAAR_VL
812
+#endif
813
+#define MIPS_MAARX_VH		(_ULCAST_(1) << 31)
814
+#define MIPS_MAARX_ADDR		0xF
815
+#define MIPS_MAARX_ADDR_SHIFT	32
756816 
757817 /* MAARI bit definitions */
758818 #define MIPS_MAARI_INDEX	(_ULCAST_(0x3f) << 0)
....@@ -989,14 +1049,25 @@
9891049 /* Disable Branch Return Cache */
9901050 #define R10K_DIAG_D_BRC		(_ULCAST_(1) << 22)
9911051 
1052
+/* Flush BTB */
1053
+#define LOONGSON_DIAG_BTB	(_ULCAST_(1) << 1)
9921054 /* Flush ITLB */
9931055 #define LOONGSON_DIAG_ITLB	(_ULCAST_(1) << 2)
9941056 /* Flush DTLB */
9951057 #define LOONGSON_DIAG_DTLB	(_ULCAST_(1) << 3)
1058
+/* Allow some CACHE instructions (CACHE0, 1, 3, 21 and 23) in user mode */
1059
+#define LOONGSON_DIAG_UCAC	(_ULCAST_(1) << 8)
9961060 /* Flush VTLB */
9971061 #define LOONGSON_DIAG_VTLB	(_ULCAST_(1) << 12)
9981062 /* Flush FTLB */
9991063 #define LOONGSON_DIAG_FTLB	(_ULCAST_(1) << 13)
1064
+
1065
+/*
1066
+ * Diag1 (GSCause in Loongson-speak) fields
1067
+ */
1068
+/* Loongson-specific exception code (GSExcCode) */
1069
+#define LOONGSON_DIAG1_EXCCODE_SHIFT	2
1070
+#define LOONGSON_DIAG1_EXCCODE		GENMASK(6, 2)
10001071 
10011072 /* CvmCtl register field definitions */
10021073 #define CVMCTL_IPPCI_SHIFT	7
....@@ -1097,9 +1168,12 @@
10971168 /*
10981169  * Bits 22:20 of the FPU Status Register will be read as 0,
10991170  * and should be written as zero.
1171
+ * MAC2008 was removed in Release 5 so we still treat it as
1172
+ * reserved.
11001173  */
11011174 #define FPU_CSR_RSVD	(_ULCAST_(7) << 20)
11021175 
1176
+#define FPU_CSR_MAC2008	(_ULCAST_(1) << 20)
11031177 #define FPU_CSR_ABS2008	(_ULCAST_(1) << 19)
11041178 #define FPU_CSR_NAN2008	(_ULCAST_(1) << 18)
11051179 
....@@ -1250,6 +1324,13 @@
12501324 		ENC							\
12511325 		".endm")
12521326 
1327
+/* Instructions with 1 register operand & 1 immediate operand */
1328
+#define _ASM_MACRO_1R1I(OP, R1, I2, ENC)				\
1329
+	__asm__(".macro	" #OP " " #R1 ", " #I2 "\n\t"			\
1330
+		"parse_r __" #R1 ", \\" #R1 "\n\t"			\
1331
+		ENC							\
1332
+		".endm")
1333
+
12531334 /* Instructions with 2 register operands */
12541335 #define _ASM_MACRO_2R(OP, R1, R2, ENC)					\
12551336 	__asm__(".macro	" #OP " " #R1 ", " #R2 "\n\t"			\
....@@ -1348,9 +1429,10 @@
13481429 			: "=r" (__res));				\
13491430 	else								\
13501431 		__asm__ vol(						\
1432
+			".set\tpush\n\t"				\
13511433 			".set\tmips32\n\t"				\
13521434 			"mfc0\t%0, " #source ", " #sel "\n\t"		\
1353
-			".set\tmips0\n\t"				\
1435
+			".set\tpop\n\t"					\
13541436 			: "=r" (__res));				\
13551437 	__res;								\
13561438 })
....@@ -1361,15 +1443,17 @@
13611443 		__res = __read_64bit_c0_split(source, sel, vol);	\
13621444 	else if (sel == 0)						\
13631445 		__asm__ vol(						\
1446
+			".set\tpush\n\t"				\
13641447 			".set\tmips3\n\t"				\
13651448 			"dmfc0\t%0, " #source "\n\t"			\
1366
-			".set\tmips0"					\
1449
+			".set\tpop"					\
13671450 			: "=r" (__res));				\
13681451 	else								\
13691452 		__asm__ vol(						\
1453
+			".set\tpush\n\t"				\
13701454 			".set\tmips64\n\t"				\
13711455 			"dmfc0\t%0, " #source ", " #sel "\n\t"		\
1372
-			".set\tmips0"					\
1456
+			".set\tpop"					\
13731457 			: "=r" (__res));				\
13741458 	__res;								\
13751459 })
....@@ -1394,9 +1478,10 @@
13941478 			: : "Jr" ((unsigned int)(value)));		\
13951479 	else								\
13961480 		__asm__ __volatile__(					\
1481
+			".set\tpush\n\t"				\
13971482 			".set\tmips32\n\t"				\
13981483 			"mtc0\t%z0, " #register ", " #sel "\n\t"	\
1399
-			".set\tmips0"					\
1484
+			".set\tpop"					\
14001485 			: : "Jr" ((unsigned int)(value)));		\
14011486 } while (0)
14021487 
....@@ -1406,15 +1491,17 @@
14061491 		__write_64bit_c0_split(register, sel, value);		\
14071492 	else if (sel == 0)						\
14081493 		__asm__ __volatile__(					\
1494
+			".set\tpush\n\t"				\
14091495 			".set\tmips3\n\t"				\
14101496 			"dmtc0\t%z0, " #register "\n\t"			\
1411
-			".set\tmips0"					\
1497
+			".set\tpop"					\
14121498 			: : "Jr" (value));				\
14131499 	else								\
14141500 		__asm__ __volatile__(					\
1501
+			".set\tpush\n\t"				\
14151502 			".set\tmips64\n\t"				\
14161503 			"dmtc0\t%z0, " #register ", " #sel "\n\t"	\
1417
-			".set\tmips0"					\
1504
+			".set\tpop"					\
14181505 			: : "Jr" (value));				\
14191506 } while (0)
14201507 
....@@ -1466,19 +1553,21 @@
14661553 	local_irq_save(__flags);					\
14671554 	if (sel == 0)							\
14681555 		__asm__ vol(						\
1556
+			".set\tpush\n\t"				\
14691557 			".set\tmips64\n\t"				\
14701558 			"dmfc0\t%L0, " #source "\n\t"			\
14711559 			"dsra\t%M0, %L0, 32\n\t"			\
14721560 			"sll\t%L0, %L0, 0\n\t"				\
1473
-			".set\tmips0"					\
1561
+			".set\tpop"					\
14741562 			: "=r" (__val));				\
14751563 	else								\
14761564 		__asm__ vol(						\
1565
+			".set\tpush\n\t"				\
14771566 			".set\tmips64\n\t"				\
14781567 			"dmfc0\t%L0, " #source ", " #sel "\n\t"		\
14791568 			"dsra\t%M0, %L0, 32\n\t"			\
14801569 			"sll\t%L0, %L0, 0\n\t"				\
1481
-			".set\tmips0"					\
1570
+			".set\tpop"					\
14821571 			: "=r" (__val));				\
14831572 	local_irq_restore(__flags);					\
14841573 									\
....@@ -1501,23 +1590,25 @@
15011590 			: "+r" (__tmp));				\
15021591 	else if (sel == 0)						\
15031592 		__asm__ __volatile__(					\
1593
+			".set\tpush\n\t"				\
15041594 			".set\tmips64\n\t"				\
15051595 			"dsll\t%L0, %L0, 32\n\t"			\
15061596 			"dsrl\t%L0, %L0, 32\n\t"			\
15071597 			"dsll\t%M0, %M0, 32\n\t"			\
15081598 			"or\t%L0, %L0, %M0\n\t"				\
15091599 			"dmtc0\t%L0, " #source "\n\t"			\
1510
-			".set\tmips0"					\
1600
+			".set\tpop"					\
15111601 			: "+r" (__tmp));				\
15121602 	else								\
15131603 		__asm__ __volatile__(					\
1604
+			".set\tpush\n\t"				\
15141605 			".set\tmips64\n\t"				\
15151606 			"dsll\t%L0, %L0, 32\n\t"			\
15161607 			"dsrl\t%L0, %L0, 32\n\t"			\
15171608 			"dsll\t%M0, %M0, 32\n\t"			\
15181609 			"or\t%L0, %L0, %M0\n\t"				\
15191610 			"dmtc0\t%L0, " #source ", " #sel "\n\t"		\
1520
-			".set\tmips0"					\
1611
+			".set\tpop"					\
15211612 			: "+r" (__tmp));				\
15221613 	local_irq_restore(__flags);					\
15231614 } while (0)
....@@ -1596,6 +1687,9 @@
15961687 #define read_c0_xcontextconfig()	__read_ulong_c0_register($4, 3)
15971688 #define write_c0_xcontextconfig(val)	__write_ulong_c0_register($4, 3, val)
15981689 
1690
+#define read_c0_memorymapid()		__read_32bit_c0_register($4, 5)
1691
+#define write_c0_memorymapid(val)	__write_32bit_c0_register($4, 5, val)
1692
+
15991693 #define read_c0_pagemask()	__read_32bit_c0_register($5, 0)
16001694 #define write_c0_pagemask(val)	__write_32bit_c0_register($5, 0, val)
16011695 
....@@ -1619,12 +1713,6 @@
16191713 #define read_c0_count()		__read_32bit_c0_register($9, 0)
16201714 #define write_c0_count(val)	__write_32bit_c0_register($9, 0, val)
16211715 
1622
-#define read_c0_count2()	__read_32bit_c0_register($9, 6) /* pnx8550 */
1623
-#define write_c0_count2(val)	__write_32bit_c0_register($9, 6, val)
1624
-
1625
-#define read_c0_count3()	__read_32bit_c0_register($9, 7) /* pnx8550 */
1626
-#define write_c0_count3(val)	__write_32bit_c0_register($9, 7, val)
1627
-
16281716 #define read_c0_entryhi()	__read_ulong_c0_register($10, 0)
16291717 #define write_c0_entryhi(val)	__write_ulong_c0_register($10, 0, val)
16301718 
....@@ -1642,12 +1730,6 @@
16421730 
16431731 #define read_c0_guestctl0ext()	__read_32bit_c0_register($11, 4)
16441732 #define write_c0_guestctl0ext(val) __write_32bit_c0_register($11, 4, val)
1645
-
1646
-#define read_c0_compare2()	__read_32bit_c0_register($11, 6) /* pnx8550 */
1647
-#define write_c0_compare2(val)	__write_32bit_c0_register($11, 6, val)
1648
-
1649
-#define read_c0_compare3()	__read_32bit_c0_register($11, 7) /* pnx8550 */
1650
-#define write_c0_compare3(val)	__write_32bit_c0_register($11, 7, val)
16511733 
16521734 #define read_c0_status()	__read_32bit_c0_register($12, 0)
16531735 
....@@ -1690,6 +1772,8 @@
16901772 #define write_c0_lladdr(val)	__write_ulong_c0_register($17, 0, val)
16911773 #define read_c0_maar()		__read_ulong_c0_register($17, 1)
16921774 #define write_c0_maar(val)	__write_ulong_c0_register($17, 1, val)
1775
+#define readx_c0_maar()		__readx_32bit_c0_register($17, 1)
1776
+#define writex_c0_maar(val)	__writex_32bit_c0_register($17, 1, val)
16931777 #define read_c0_maari()		__read_32bit_c0_register($17, 2)
16941778 #define write_c0_maari(val)	__write_32bit_c0_register($17, 2, val)
16951779 
....@@ -1949,6 +2033,9 @@
19492033 
19502034 #define read_c0_brcm_sleepcount()	__read_32bit_c0_register($22, 7)
19512035 #define write_c0_brcm_sleepcount(val)	__write_32bit_c0_register($22, 7, val)
2036
+
2037
+/* Ingenic page ctrl register */
2038
+#define write_c0_page_ctrl(val)	__write_32bit_c0_register($5, 4, val)
19522039 
19532040 /*
19542041  * Macros to access the guest system control coprocessor
....@@ -2290,13 +2377,14 @@
22902377 	_write_32bit_cp1_register(dest, val, )
22912378 #endif
22922379 
2293
-#ifdef HAVE_AS_DSP
2380
+#ifdef TOOLCHAIN_SUPPORTS_DSP
22942381 #define rddsp(mask)							\
22952382 ({									\
22962383 	unsigned int __dspctl;						\
22972384 									\
22982385 	__asm__ __volatile__(						\
22992386 	"	.set push					\n"	\
2387
+	"	.set " MIPS_ISA_LEVEL "				\n"	\
23002388 	"	.set dsp					\n"	\
23012389 	"	rddsp	%0, %x1					\n"	\
23022390 	"	.set pop					\n"	\
....@@ -2309,6 +2397,7 @@
23092397 do {									\
23102398 	__asm__ __volatile__(						\
23112399 	"	.set push					\n"	\
2400
+	"	.set " MIPS_ISA_LEVEL "				\n"	\
23122401 	"	.set dsp					\n"	\
23132402 	"	wrdsp	%0, %x1					\n"	\
23142403 	"	.set pop					\n"	\
....@@ -2321,6 +2410,7 @@
23212410 	long mflo0;							\
23222411 	__asm__(							\
23232412 	"	.set push					\n"	\
2413
+	"	.set " MIPS_ISA_LEVEL "				\n"	\
23242414 	"	.set dsp					\n"	\
23252415 	"	mflo %0, $ac0					\n"	\
23262416 	"	.set pop					\n" 	\
....@@ -2333,6 +2423,7 @@
23332423 	long mflo1;							\
23342424 	__asm__(							\
23352425 	"	.set push					\n"	\
2426
+	"	.set " MIPS_ISA_LEVEL "				\n"	\
23362427 	"	.set dsp					\n"	\
23372428 	"	mflo %0, $ac1					\n"	\
23382429 	"	.set pop					\n" 	\
....@@ -2345,6 +2436,7 @@
23452436 	long mflo2;							\
23462437 	__asm__(							\
23472438 	"	.set push					\n"	\
2439
+	"	.set " MIPS_ISA_LEVEL "				\n"	\
23482440 	"	.set dsp					\n"	\
23492441 	"	mflo %0, $ac2					\n"	\
23502442 	"	.set pop					\n" 	\
....@@ -2357,6 +2449,7 @@
23572449 	long mflo3;							\
23582450 	__asm__(							\
23592451 	"	.set push					\n"	\
2452
+	"	.set " MIPS_ISA_LEVEL "				\n"	\
23602453 	"	.set dsp					\n"	\
23612454 	"	mflo %0, $ac3					\n"	\
23622455 	"	.set pop					\n" 	\
....@@ -2369,6 +2462,7 @@
23692462 	long mfhi0;							\
23702463 	__asm__(							\
23712464 	"	.set push					\n"	\
2465
+	"	.set " MIPS_ISA_LEVEL "				\n"	\
23722466 	"	.set dsp					\n"	\
23732467 	"	mfhi %0, $ac0					\n"	\
23742468 	"	.set pop					\n" 	\
....@@ -2381,6 +2475,7 @@
23812475 	long mfhi1;							\
23822476 	__asm__(							\
23832477 	"	.set push					\n"	\
2478
+	"	.set " MIPS_ISA_LEVEL "				\n"	\
23842479 	"	.set dsp					\n"	\
23852480 	"	mfhi %0, $ac1					\n"	\
23862481 	"	.set pop					\n" 	\
....@@ -2393,6 +2488,7 @@
23932488 	long mfhi2;							\
23942489 	__asm__(							\
23952490 	"	.set push					\n"	\
2491
+	"	.set " MIPS_ISA_LEVEL "				\n"	\
23962492 	"	.set dsp					\n"	\
23972493 	"	mfhi %0, $ac2					\n"	\
23982494 	"	.set pop					\n" 	\
....@@ -2405,6 +2501,7 @@
24052501 	long mfhi3;							\
24062502 	__asm__(							\
24072503 	"	.set push					\n"	\
2504
+	"	.set " MIPS_ISA_LEVEL "				\n"	\
24082505 	"	.set dsp					\n"	\
24092506 	"	mfhi %0, $ac3					\n"	\
24102507 	"	.set pop					\n" 	\
....@@ -2417,6 +2514,7 @@
24172514 ({									\
24182515 	__asm__(							\
24192516 	"	.set push					\n"	\
2517
+	"	.set " MIPS_ISA_LEVEL "				\n"	\
24202518 	"	.set dsp					\n"	\
24212519 	"	mtlo %0, $ac0					\n"	\
24222520 	"	.set pop					\n"	\
....@@ -2428,6 +2526,7 @@
24282526 ({									\
24292527 	__asm__(							\
24302528 	"	.set push					\n"	\
2529
+	"	.set " MIPS_ISA_LEVEL "				\n"	\
24312530 	"	.set dsp					\n"	\
24322531 	"	mtlo %0, $ac1					\n"	\
24332532 	"	.set pop					\n"	\
....@@ -2439,6 +2538,7 @@
24392538 ({									\
24402539 	__asm__(							\
24412540 	"	.set push					\n"	\
2541
+	"	.set " MIPS_ISA_LEVEL "				\n"	\
24422542 	"	.set dsp					\n"	\
24432543 	"	mtlo %0, $ac2					\n"	\
24442544 	"	.set pop					\n"	\
....@@ -2450,6 +2550,7 @@
24502550 ({									\
24512551 	__asm__(							\
24522552 	"	.set push					\n"	\
2553
+	"	.set " MIPS_ISA_LEVEL "				\n"	\
24532554 	"	.set dsp					\n"	\
24542555 	"	mtlo %0, $ac3					\n"	\
24552556 	"	.set pop					\n"	\
....@@ -2461,6 +2562,7 @@
24612562 ({									\
24622563 	__asm__(							\
24632564 	"	.set push					\n"	\
2565
+	"	.set " MIPS_ISA_LEVEL "				\n"	\
24642566 	"	.set dsp					\n"	\
24652567 	"	mthi %0, $ac0					\n"	\
24662568 	"	.set pop					\n"	\
....@@ -2472,6 +2574,7 @@
24722574 ({									\
24732575 	__asm__(							\
24742576 	"	.set push					\n"	\
2577
+	"	.set " MIPS_ISA_LEVEL "				\n"	\
24752578 	"	.set dsp					\n"	\
24762579 	"	mthi %0, $ac1					\n"	\
24772580 	"	.set pop					\n"	\
....@@ -2483,6 +2586,7 @@
24832586 ({									\
24842587 	__asm__(							\
24852588 	"	.set push					\n"	\
2589
+	"	.set " MIPS_ISA_LEVEL "				\n"	\
24862590 	"	.set dsp					\n"	\
24872591 	"	mthi %0, $ac2					\n"	\
24882592 	"	.set pop					\n"	\
....@@ -2494,6 +2598,7 @@
24942598 ({									\
24952599 	__asm__(							\
24962600 	"	.set push					\n"	\
2601
+	"	.set " MIPS_ISA_LEVEL "				\n"	\
24972602 	"	.set dsp					\n"	\
24982603 	"	mthi %0, $ac3					\n"	\
24992604 	"	.set pop					\n"	\
....@@ -2618,7 +2723,7 @@
26182723 
26192724 static inline void tlb_read(void)
26202725 {
2621
-#if MIPS34K_MISSED_ITLB_WAR
2726
+#ifdef CONFIG_WAR_MIPS34K_MISSED_ITLB
26222727 	int res = 0;
26232728 
26242729 	__asm__ __volatile__(
....@@ -2640,7 +2745,7 @@
26402745 		"tlbr\n\t"
26412746 		".set reorder");
26422747 
2643
-#if MIPS34K_MISSED_ITLB_WAR
2748
+#ifdef CONFIG_WAR_MIPS34K_MISSED_ITLB
26442749 	if ((res & _ULCAST_(1)))
26452750 		__asm__ __volatile__(
26462751 		"	.set	push				\n"
....@@ -2777,7 +2882,9 @@
27772882 __BUILD_SET_C0(cause)
27782883 __BUILD_SET_C0(config)
27792884 __BUILD_SET_C0(config5)
2885
+__BUILD_SET_C0(config6)
27802886 __BUILD_SET_C0(config7)
2887
+__BUILD_SET_C0(diag)
27812888 __BUILD_SET_C0(intcontrol)
27822889 __BUILD_SET_C0(intctl)
27832890 __BUILD_SET_C0(srsmap)