add ax88772_rst

hc

2024-05-10 9999e48639b3cecb08ffb37358bcba3b48161b29

 kernel/arch/arm/crypto/sha512-armv4.pl
..
..
@@ -13,7 +13,7 @@
13
13
 # Written by Andy Polyakov <appro@openssl.org> for the OpenSSL
14
14
 # project. The module is, however, dual licensed under OpenSSL and
15
15
 # CRYPTOGAMS licenses depending on where you obtain it. For further
16
-# details see http://www.openssl.org/~appro/cryptogams/.
16
+# details see https://www.openssl.org/~appro/cryptogams/.
17
17
 # ====================================================================
18
18
 
19
19
 # SHA512 block procedure for ARMv4. September 2007.
..
..
@@ -43,7 +43,7 @@
43
43
 # terms it's 22.6 cycles per byte, which is disappointing result.
44
44
 # Technical writers asserted that 3-way S4 pipeline can sustain
45
45
 # multiple NEON instructions per cycle, but dual NEON issue could
46
-# not be observed, see http://www.openssl.org/~appro/Snapdragon-S4.html
46
+# not be observed, see https://www.openssl.org/~appro/Snapdragon-S4.html
47
47
 # for further details. On side note Cortex-A15 processes one byte in
48
48
 # 16 cycles.
49
49
 
..
..
@@ -212,7 +212,6 @@
212
212
 #else
213
213
 .syntax unified
214
214
 # ifdef __thumb2__
215
-#  define adrl adr
216
215
 .thumb
217
216
 # else
218
217
 .code   32
..
..
@@ -602,7 +601,8 @@
602
601
 	dmb				@ errata #451034 on early Cortex A8
603
602
 	add	$len,$inp,$len,lsl#7	@ len to point at the end of inp
604
603
 	VFP_ABI_PUSH
605
-	adrl	$Ktbl,K512
604
+	adr	$Ktbl,.Lsha512_block_data_order
605
+	sub	$Ktbl,$Ktbl,.Lsha512_block_data_order-K512
606
606
 	vldmia	$ctx,{$A-$H}		@ load context
607
607
 .Loop_neon:
608
608
 ___