forked from ~ljy/RK356X_SDK_RELEASE

hc
2024-05-10 9999e48639b3cecb08ffb37358bcba3b48161b29
kernel/arch/arm/boot/dts/rk3288-linux.dtsi
....@@ -7,8 +7,15 @@
77 #include "rk3288-dram-default-timing.dtsi"
88
99 / {
10
+ aliases {
11
+ mshc0 = &emmc;
12
+ mshc1 = &sdmmc;
13
+ mshc2 = &sdio0;
14
+ mshc3 = &sdio1;
15
+ };
16
+
1017 chosen {
11
- bootargs = "earlycon=uart8250,mmio32,0xff690000 vmalloc=496M rw root=PARTUUID=614e0000-0000 rootfstype=ext4 rootwait";
18
+ bootargs = "earlycon=uart8250,mmio32,0xff690000 console=ttyFIQ0 vmalloc=496M rw root=PARTUUID=614e0000-0000 rootfstype=ext4 rootwait";
1219 };
1320
1421 /delete-node/ dmc@ff610000;
....@@ -74,12 +81,12 @@
7481 };
7582
7683 reserved-memory {
77
- ramoops_mem: ramoops@00000000 {
84
+ ramoops_mem: ramoops@8000000 {
7885 reg = <0x0 0x8000000 0x0 0xF0000>;
7986 };
8087
8188 drm_logo: drm-logo@00000000 {
82
- compatible = "rockchip,drm-logo";
89
+ compatible = "rockchip,drm-logo";
8390 reg = <0x0 0x0 0x0 0x0>;
8491 };
8592 };
....@@ -89,16 +96,10 @@
8996 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
9097 rockchip,serial-id = <2>;
9198 rockchip,wake-irq = <0>;
92
- /* If enable uart uses irq instead of fiq */
93
- rockchip,irq-mode-enable = <0>;
99
+ rockchip,irq-mode-enable = <1>; /* If enable uart uses irq instead of fiq */
94100 rockchip,baudrate = <115200>; /* Only 115200 and 1500000 */
95101 pinctrl-names = "default";
96102 pinctrl-0 = <&uart2_xfer>;
97
- };
98
-
99
- psci {
100
- compatible = "arm,psci-1.0";
101
- method = "smc";
102103 };
103104
104105 /delete-node/ timer@ff810000;
....@@ -158,22 +159,6 @@
158159 };
159160 };
160161
161
-&cpu0 {
162
- enable-method = "psci";
163
-};
164
-
165
-&cpu1 {
166
- enable-method = "psci";
167
-};
168
-
169
-&cpu2 {
170
- enable-method = "psci";
171
-};
172
-
173
-&cpu3 {
174
- enable-method = "psci";
175
-};
176
-
177162 &dmac_bus_s {
178163 /* change to non-secure dmac */
179164 reg = <0x0 0xff600000 0x0 0x4000>;
....@@ -195,6 +180,25 @@
195180 status = "okay";
196181 };
197182
183
+&iep {
184
+ status = "okay";
185
+};
186
+
187
+&iep_mmu {
188
+ status = "okay";
189
+};
190
+
191
+&rga {
192
+ compatible = "rockchip,rga2";
193
+ clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
194
+ clock-names = "aclk_rga", "hclk_rga", "clk_rga";
195
+ status = "okay";
196
+};
197
+
198
+&rng {
199
+ status = "okay";
200
+};
201
+
198202 &uart2 {
199203 status = "disabled";
200204 };